[PATCH] pciehp: Use dword accessors for PCI_ROM_ADDRESS

PCI_ROM_ADDRESS is a 32 bit register and as such should be accessed
using pci_bus_{read,write}_config_dword(). A recent audit of drivers/
turned up several cases of byte- and word-sized accesses. The harmful
ones were fixed by Linus directly. This patches up one of the remaining
harmless-but-still-wrong cases caught in the dragnet.

Signed-off-by: Adam Kropelin <akropel1@rochester.rr.com>
Cc: <kristen.c.accardi@intel.com>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

authored by Adam Kropelin and committed by Linus Torvalds c2fa4f4a d648daca

+1 -3
+1 -3
drivers/pci/hotplug/pciehp_ctrl.c
··· 2526 int cloop; 2527 u8 temp_byte; 2528 u8 class_code; 2529 - u16 temp_word; 2530 u32 rc; 2531 u32 temp_register; 2532 u32 base; ··· 2681 } /* End of base register loop */ 2682 2683 /* disable ROM base Address */ 2684 - temp_word = 0x00L; 2685 - rc = pci_bus_write_config_word (pci_bus, devfn, PCI_ROM_ADDRESS, temp_word); 2686 2687 /* Set HP parameters (Cache Line Size, Latency Timer) */ 2688 rc = pciehprm_set_hpp(ctrl, func, PCI_HEADER_TYPE_NORMAL);
··· 2526 int cloop; 2527 u8 temp_byte; 2528 u8 class_code; 2529 u32 rc; 2530 u32 temp_register; 2531 u32 base; ··· 2682 } /* End of base register loop */ 2683 2684 /* disable ROM base Address */ 2685 + rc = pci_bus_write_config_dword (pci_bus, devfn, PCI_ROM_ADDRESS, 0x00); 2686 2687 /* Set HP parameters (Cache Line Size, Latency Timer) */ 2688 rc = pciehprm_set_hpp(ctrl, func, PCI_HEADER_TYPE_NORMAL);