MIPS: Avoid potential hazard on Context register

set_saved_sp reads Context register. Avoid reading stale value from
earlier incomplete write.

Issue found and fixed for head.S by Chris Dearman <chris@mips.com>.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

+4
+3
arch/mips/include/asm/mmu_context.h
··· 16 #include <linux/smp.h> 17 #include <linux/slab.h> 18 #include <asm/cacheflush.h> 19 #include <asm/tlbflush.h> 20 #ifdef CONFIG_MIPS_MT_SMTC 21 #include <asm/mipsmtregs.h> ··· 37 #ifdef CONFIG_32BIT 38 #define TLBMISS_HANDLER_SETUP() \ 39 write_c0_context((unsigned long) smp_processor_id() << 25); \ 40 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 41 #endif 42 #ifdef CONFIG_64BIT 43 #define TLBMISS_HANDLER_SETUP() \ 44 write_c0_context((unsigned long) smp_processor_id() << 26); \ 45 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 46 #endif 47
··· 16 #include <linux/smp.h> 17 #include <linux/slab.h> 18 #include <asm/cacheflush.h> 19 + #include <asm/hazards.h> 20 #include <asm/tlbflush.h> 21 #ifdef CONFIG_MIPS_MT_SMTC 22 #include <asm/mipsmtregs.h> ··· 36 #ifdef CONFIG_32BIT 37 #define TLBMISS_HANDLER_SETUP() \ 38 write_c0_context((unsigned long) smp_processor_id() << 25); \ 39 + back_to_back_c0_hazard(); \ 40 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 41 #endif 42 #ifdef CONFIG_64BIT 43 #define TLBMISS_HANDLER_SETUP() \ 44 write_c0_context((unsigned long) smp_processor_id() << 26); \ 45 + back_to_back_c0_hazard(); \ 46 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 47 #endif 48
+1
arch/mips/kernel/head.S
··· 191 /* Set the SP after an empty pt_regs. */ 192 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE 193 PTR_ADDU sp, $28 194 set_saved_sp sp, t0, t1 195 PTR_SUBU sp, 4 * SZREG # init stack pointer 196
··· 191 /* Set the SP after an empty pt_regs. */ 192 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE 193 PTR_ADDU sp, $28 194 + back_to_back_c0_hazard 195 set_saved_sp sp, t0, t1 196 PTR_SUBU sp, 4 * SZREG # init stack pointer 197