tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
sh: Add some missing board headers.
Some of these were dropped in the header directory rework, add
the few missing ones back in.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
+420
+30
include/asm-sh/edosk7705.h
+30
include/asm-sh/edosk7705.h
···
1
+
/*
2
+
* include/asm-sh/edosk7705/io.h
3
+
*
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+
* Modified version of io_se.h for the EDOSK7705 specific functions.
5
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*
6
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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* IO functions for an Hitachi EDOSK7705 development board
10
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*/
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12
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#ifndef __ASM_SH_EDOSK7705_IO_H
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#define __ASM_SH_EDOSK7705_IO_H
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+
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#include <asm/io_generic.h>
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+
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extern unsigned char sh_edosk7705_inb(unsigned long port);
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extern unsigned int sh_edosk7705_inl(unsigned long port);
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+
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extern void sh_edosk7705_outb(unsigned char value, unsigned long port);
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extern void sh_edosk7705_outl(unsigned int value, unsigned long port);
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+
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extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count);
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extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count);
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extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count);
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extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count);
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+
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extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset);
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+
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+
#endif /* __ASM_SH_EDOSK7705_IO_H */
+80
include/asm-sh/hp6xx.h
+80
include/asm-sh/hp6xx.h
···
1
+
#ifndef __ASM_SH_HP6XX_H
2
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#define __ASM_SH_HP6XX_H
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+
4
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/*
5
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* Copyright (C) 2003, 2004, 2005 Andriy Skulysh
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*
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* This file is subject to the terms and conditions of the GNU General Public
8
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* License. See the file "COPYING" in the main directory of this archive
9
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* for more details.
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*
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*/
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+
13
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#define HP680_BTN_IRQ IRQ0_IRQ
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#define HP680_TS_IRQ IRQ3_IRQ
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#define HP680_HD64461_IRQ IRQ4_IRQ
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+
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#define DAC_LCD_BRIGHTNESS 0
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#define DAC_SPEAKER_VOLUME 1
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+
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#define PGDR_OPENED 0x01
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#define PGDR_MAIN_BATTERY_OUT 0x04
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#define PGDR_PLAY_BUTTON 0x08
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#define PGDR_REWIND_BUTTON 0x10
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#define PGDR_RECORD_BUTTON 0x20
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+
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#define PHDR_TS_PEN_DOWN 0x08
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+
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#define PJDR_LED_BLINK 0x02
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+
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#define PKDR_LED_GREEN 0x10
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#define SCPDR_TS_SCAN_ENABLE 0x20
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#define SCPDR_TS_SCAN_Y 0x02
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#define SCPDR_TS_SCAN_X 0x01
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+
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#define SCPCR_TS_ENABLE 0x405
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#define SCPCR_TS_MASK 0xc0f
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+
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#define ADC_CHANNEL_TS_Y 1
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#define ADC_CHANNEL_TS_X 2
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#define ADC_CHANNEL_BATTERY 3
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#define ADC_CHANNEL_BACKUP 4
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#define ADC_CHANNEL_CHARGE 5
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+
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#define HD64461_GPADR_SPEAKER 0x01
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#define HD64461_GPADR_PCMCIA0 (0x02|0x08)
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+
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#define HD64461_GPBDR_LCDOFF 0x01
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#define HD64461_GPBDR_LCD_CONTRAST_MASK 0x78
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#define HD64461_GPBDR_LED_RED 0x80
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+
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#include <asm/hd64461.h>
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#include <asm/io.h>
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+
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#define PJDR 0xa4000130
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#define PKDR 0xa4000132
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static inline void hp6xx_led_red(int on)
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{
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u16 v16;
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v16 = ctrl_inw(CONFIG_HD64461_IOBASE + HD64461_GPBDR - 0x10000);
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if (on)
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ctrl_outw(v16 & (~HD64461_GPBDR_LED_RED), CONFIG_HD64461_IOBASE + HD64461_GPBDR - 0x10000);
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else
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ctrl_outw(v16 | HD64461_GPBDR_LED_RED, CONFIG_HD64461_IOBASE + HD64461_GPBDR - 0x10000);
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}
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static inline void hp6xx_led_green(int on)
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{
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u8 v8;
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+
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v8 = ctrl_inb(PKDR);
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if (on)
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ctrl_outb(v8 & (~PKDR_LED_GREEN), PKDR);
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else
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ctrl_outb(v8 | PKDR_LED_GREEN, PKDR);
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}
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+
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+
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#endif /* __ASM_SH_HP6XX_H */
+54
include/asm-sh/hs7751rvoip.h
+54
include/asm-sh/hs7751rvoip.h
···
1
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#ifndef __ASM_SH_RENESAS_HS7751RVOIP_H
2
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#define __ASM_SH_RENESAS_HS7751RVOIP_H
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4
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/*
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* linux/include/asm-sh/hs7751rvoip/hs7751rvoip.h
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*
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* Copyright (C) 2000 Atom Create Engineering Co., Ltd.
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*
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* Renesas Technology Sales HS7751RVoIP support
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*/
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+
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/* Box specific addresses. */
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+
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#define PA_BCR 0xa4000000 /* FPGA */
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#define PA_SLICCNTR1 0xa4000006 /* SLIC PIO Control 1 */
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#define PA_SLICCNTR2 0xa4000008 /* SLIC PIO Control 2 */
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#define PA_DMACNTR 0xa400000a /* USB DMA Control */
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#define PA_INPORTR 0xa400000c /* Input Port Register */
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#define PA_OUTPORTR 0xa400000e /* Output Port Reguster */
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#define PA_VERREG 0xa4000014 /* FPGA Version Register */
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+
22
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#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
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+
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#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
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#define IRLCNTR2 (PA_BCR + 2) /* Interrupt Control Register2 */
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#define IRLCNTR3 (PA_BCR + 4) /* Interrupt Control Register3 */
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#define IRLCNTR4 (PA_BCR + 16) /* Interrupt Control Register4 */
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#define IRLCNTR5 (PA_BCR + 18) /* Interrupt Control Register5 */
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+
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#define IRQ_PCIETH 6 /* PCI Ethernet IRQ */
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#define IRQ_PCIHUB 7 /* PCI Ethernet Hub IRQ */
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#define IRQ_USBCOM 8 /* USB Comunication IRQ */
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#define IRQ_USBCON 9 /* USB Connect IRQ */
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#define IRQ_USBDMA 10 /* USB DMA IRQ */
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#define IRQ_CFCARD 11 /* CF Card IRQ */
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#define IRQ_PCMCIA 12 /* PCMCIA IRQ */
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#define IRQ_PCISLOT 13 /* PCI Slot #1 IRQ */
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#define IRQ_ONHOOK1 0 /* ON HOOK1 IRQ */
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#define IRQ_OFFHOOK1 1 /* OFF HOOK1 IRQ */
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#define IRQ_ONHOOK2 2 /* ON HOOK2 IRQ */
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#define IRQ_OFFHOOK2 3 /* OFF HOOK2 IRQ */
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#define IRQ_RINGING 4 /* Ringing IRQ */
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#define IRQ_CODEC 5 /* CODEC IRQ */
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+
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#define __IO_PREFIX hs7751rvoip
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#include <asm/io_generic.h>
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+
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/* arch/sh/boards/renesas/hs7751rvoip/irq.c */
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void init_hs7751rvoip_IRQ(void);
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+
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/* arch/sh/boards/renesas/hs7751rvoip/io.c */
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void *hs7751rvoip_ioremap(unsigned long, unsigned long);
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+
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#endif /* __ASM_SH_RENESAS_HS7751RVOIP */
+173
include/asm-sh/r7780rp.h
+173
include/asm-sh/r7780rp.h
···
1
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#ifndef __ASM_SH_RENESAS_R7780RP_H
2
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#define __ASM_SH_RENESAS_R7780RP_H
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+
4
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/*
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* linux/include/asm-sh/r7780rp.h
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*
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* Copyright (C) 2000 Atom Create Engineering Co., Ltd.
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*
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* Renesas Solutions Highlander R7780RP support
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*/
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+
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/* Box specific addresses. */
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#if defined(CONFIG_SH_R7780MP)
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#define PA_BCR 0xa4000000 /* FPGA */
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#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
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#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
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#define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
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#define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
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#define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
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#define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
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#define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
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#define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
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#define PA_PCICD (PA_BCR+0x0010) /* PCI Conector detect control */
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#define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */
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#define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
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#define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
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#define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
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#define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
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#define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */
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#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
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#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
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#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
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#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
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#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
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#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
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#define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */
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#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
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#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
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#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
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#define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
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#define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */
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#define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
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#define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
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#define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
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#define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
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#define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */
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#define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
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#define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
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#define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
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#define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */
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#define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
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#define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
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#define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */
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#define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
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#define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
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#define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */
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#define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
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#define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */
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#define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
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#define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
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#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
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#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
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#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
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#define PA_ICCR (PA_BCR+0x0600) /* Serial control */
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#define PA_SAR (PA_BCR+0x0602) /* Serial Slave control */
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#define PA_MDR (PA_BCR+0x0604) /* Serial Mode control */
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#define PA_ADR1 (PA_BCR+0x0606) /* Serial Address1 control */
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#define PA_DAR1 (PA_BCR+0x0646) /* Serial Data1 control */
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#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
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#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
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#define PA_PMR (PA_BCR+0x0900) /* */
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+
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#define PA_AX88796L 0xa4100400 /* AX88796L Area */
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+
#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
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+
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
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+
#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
77
+
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#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
79
+
80
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#define IRQ_PCISLOT1 65 /* PCI Slot #1 IRQ */
81
+
#define IRQ_PCISLOT2 66 /* PCI Slot #2 IRQ */
82
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#define IRQ_PCISLOT3 67 /* PCI Slot #3 IRQ */
83
+
#define IRQ_PCISLOT4 68 /* PCI Slot #4 IRQ */
84
+
#define IRQ_CFCARD 1 /* CF Card IRQ */
85
+
// #define IRQ_CFINST 0 /* CF Card Insert IRQ */
86
+
#define IRQ_TP 2 /* Touch Panel IRQ */
87
+
#define IRQ_SCI1 3 /* SCI1 IRQ */
88
+
#define IRQ_SCI0 4 /* SCI0 IRQ */
89
+
#define IRQ_2SERIAL 5 /* Serial IRQ */
90
+
#define IRQ_RTC 6 /* RTC A / B IRQ */
91
+
#define IRQ_EXTENTION6 7 /* EXT6n IRQ */
92
+
#define IRQ_EXTENTION5 8 /* EXT5n IRQ */
93
+
#define IRQ_EXTENTION4 9 /* EXT4n IRQ */
94
+
#define IRQ_EXTENTION2 10 /* EXT2n IRQ */
95
+
#define IRQ_EXTENTION1 11 /* EXT1n IRQ */
96
+
#define IRQ_ONETH 13 /* On board Ethernet IRQ */
97
+
#define IRQ_PSW 14 /* Push Switch IRQ */
98
+
99
+
#else /* R7780RP */
100
+
101
+
#define PA_BCR 0xa5000000 /* FPGA */
102
+
#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
103
+
#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
104
+
#define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */
105
+
#define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */
106
+
#define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */
107
+
#define PA_PCICD (PA_BCR+0x000a) /* PCI Conector detect control */
108
+
#define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
109
+
#define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */
110
+
#define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */
111
+
#define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */
112
+
#define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */
113
+
#define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */
114
+
#define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */
115
+
#define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */
116
+
#define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */
117
+
#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
118
+
#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
119
+
#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
120
+
#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
121
+
#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
122
+
#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
123
+
#define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */
124
+
#define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */
125
+
#define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */
126
+
#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
127
+
#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
128
+
#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
129
+
#define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */
130
+
#define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */
131
+
#define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */
132
+
#define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */
133
+
#define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */
134
+
#define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */
135
+
#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
136
+
#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
137
+
#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
138
+
#define PA_ICCR (PA_BCR+0x0500) /* Serial control */
139
+
#define PA_SAR (PA_BCR+0x0502) /* Serial Slave control */
140
+
#define PA_MDR (PA_BCR+0x0504) /* Serial Mode control */
141
+
#define PA_ADR1 (PA_BCR+0x0506) /* Serial Address1 control */
142
+
#define PA_DAR1 (PA_BCR+0x0546) /* Serial Data1 control */
143
+
#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
144
+
145
+
#define PA_AX88796L 0xa5800400 /* AX88796L Area */
146
+
#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
147
+
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
148
+
#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
149
+
150
+
#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
151
+
152
+
#define IRQ_PCISLOT1 0 /* PCI Slot #1 IRQ */
153
+
#define IRQ_PCISLOT2 1 /* PCI Slot #2 IRQ */
154
+
#define IRQ_PCISLOT3 2 /* PCI Slot #3 IRQ */
155
+
#define IRQ_PCISLOT4 3 /* PCI Slot #4 IRQ */
156
+
#define IRQ_CFCARD 4 /* CF Card IRQ */
157
+
#define IRQ_CFINST 5 /* CF Card Insert IRQ */
158
+
#define IRQ_M66596 6 /* M66596 IRQ */
159
+
#define IRQ_SDCARD 7 /* SD Card IRQ */
160
+
#define IRQ_TUCHPANEL 8 /* Touch Panel IRQ */
161
+
#define IRQ_SCI 9 /* SCI IRQ */
162
+
#define IRQ_2SERIAL 10 /* Serial IRQ */
163
+
#define IRQ_EXTENTION 11 /* EXTn IRQ */
164
+
#define IRQ_ONETH 12 /* On board Ethernet IRQ */
165
+
#define IRQ_PSW 13 /* Push Switch IRQ */
166
+
#define IRQ_ZIGBEE 14 /* Ziggbee IO IRQ */
167
+
168
+
#endif /* CONFIG_SH_R7780MP */
169
+
170
+
#define __IO_PREFIX r7780rp
171
+
#include <asm/io_generic.h>
172
+
173
+
#endif /* __ASM_SH_RENESAS_R7780RP */
+74
include/asm-sh/rts7751r2d.h
+74
include/asm-sh/rts7751r2d.h
···
1
+
#ifndef __ASM_SH_RENESAS_RTS7751R2D_H
2
+
#define __ASM_SH_RENESAS_RTS7751R2D_H
3
+
4
+
/*
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* linux/include/asm-sh/renesas_rts7751r2d.h
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*
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* Copyright (C) 2000 Atom Create Engineering Co., Ltd.
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*
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* Renesas Technology Sales RTS7751R2D support
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*/
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/* Box specific addresses. */
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#define PA_BCR 0xa4000000 /* FPGA */
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#define PA_IRLMON 0xa4000002 /* Interrupt Status control */
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#define PA_CFCTL 0xa4000004 /* CF Timing control */
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#define PA_CFPOW 0xa4000006 /* CF Power control */
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#define PA_DISPCTL 0xa4000008 /* Display Timing control */
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#define PA_SDMPOW 0xa400000a /* SD Power control */
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#define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */
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#define PA_PCICD 0xa400000e /* PCI Extention detect control */
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#define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */
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#if defined(CONFIG_RTS7751R2D_REV11)
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#define PA_AXRST 0xa4000022 /* AX_LAN Reset control */
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#define PA_CFRST 0xa4000024 /* CF Reset control */
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#define PA_ADMRTS 0xa4000026 /* SD Reset control */
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#define PA_EXTRST 0xa4000028 /* Extention Reset control */
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#define PA_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */
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#else
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#define PA_CFRST 0xa4000022 /* CF Reset control */
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#define PA_ADMRTS 0xa4000024 /* SD Reset control */
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#define PA_EXTRST 0xa4000026 /* Extention Reset control */
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#define PA_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */
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#define PA_KEYCTLCLR 0xa400002a /* Key Interrupt clear */
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#endif
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#define PA_POWOFF 0xa4000030 /* Board Power OFF control */
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#define PA_VERREG 0xa4000032 /* FPGA Version Register */
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#define PA_INPORT 0xa4000034 /* KEY Input Port control */
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#define PA_OUTPORT 0xa4000036 /* LED control */
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#define PA_DMPORT 0xa4000038 /* DM270 Output Port control */
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#define PA_AX88796L 0xaa000400 /* AX88796L Area */
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#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */
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#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
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#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
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#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
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#if defined(CONFIG_RTS7751R2D_REV11)
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#define IRQ_PCIETH 0 /* PCI Ethernet IRQ */
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#define IRQ_CFCARD 1 /* CF Card IRQ */
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#define IRQ_CFINST 2 /* CF Card Insert IRQ */
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#define IRQ_PCMCIA 3 /* PCMCIA IRQ */
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#define IRQ_VOYAGER 4 /* VOYAGER IRQ */
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#define IRQ_ONETH 5 /* On board Ethernet IRQ */
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#else
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#define IRQ_KEYIN 0 /* Key Input IRQ */
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#define IRQ_PCIETH 1 /* PCI Ethernet IRQ */
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#define IRQ_CFCARD 2 /* CF Card IRQ */
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#define IRQ_CFINST 3 /* CF Card Insert IRQ */
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#define IRQ_PCMCIA 4 /* PCMCIA IRQ */
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#define IRQ_VOYAGER 5 /* VOYAGER IRQ */
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#endif
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#define IRQ_RTCALM 6 /* RTC Alarm IRQ */
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#define IRQ_RTCTIME 7 /* RTC Timer IRQ */
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#define IRQ_SDCARD 8 /* SD Card IRQ */
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#define IRQ_PCISLOT1 9 /* PCI Slot #1 IRQ */
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#define IRQ_PCISLOT2 10 /* PCI Slot #2 IRQ */
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#define IRQ_EXTENTION 11 /* EXTn IRQ */
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#define __IO_PREFIX rts7751r2d
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#include <asm/io_generic.h>
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#endif /* __ASM_SH_RENESAS_RTS7751R2D */