Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

lib/crc: Use underlying functions instead of crypto_simd_usable()

Since crc_kunit now tests the fallback code paths without using
crypto_simd_disabled_for_test, make the CRC code just use the underlying
may_use_simd() and irq_fpu_usable() functions directly instead of
crypto_simd_usable(). This eliminates an unnecessary layer.

Take the opportunity to add likely() and unlikely() annotations as well.

Link: https://lore.kernel.org/r/20250811182631.376302-4-ebiggers@kernel.org
Signed-off-by: Eric Biggers <ebiggers@kernel.org>

+20 -24
+2 -4
lib/crc/arm/crc-t10dif.h
··· 5 5 * Copyright (C) 2016 Linaro Ltd <ard.biesheuvel@linaro.org> 6 6 */ 7 7 8 - #include <crypto/internal/simd.h> 9 - 10 8 #include <asm/neon.h> 11 9 #include <asm/simd.h> 12 10 ··· 21 23 { 22 24 if (length >= CRC_T10DIF_PMULL_CHUNK_SIZE) { 23 25 if (static_branch_likely(&have_pmull)) { 24 - if (crypto_simd_usable()) { 26 + if (likely(may_use_simd())) { 25 27 kernel_neon_begin(); 26 28 crc = crc_t10dif_pmull64(crc, data, length); 27 29 kernel_neon_end(); ··· 29 31 } 30 32 } else if (length > CRC_T10DIF_PMULL_CHUNK_SIZE && 31 33 static_branch_likely(&have_neon) && 32 - crypto_simd_usable()) { 34 + likely(may_use_simd())) { 33 35 u8 buf[16] __aligned(16); 34 36 35 37 kernel_neon_begin();
+2 -4
lib/crc/arm/crc32.h
··· 7 7 8 8 #include <linux/cpufeature.h> 9 9 10 - #include <crypto/internal/simd.h> 11 - 12 10 #include <asm/hwcap.h> 13 11 #include <asm/neon.h> 14 12 #include <asm/simd.h> ··· 32 34 static inline u32 crc32_le_arch(u32 crc, const u8 *p, size_t len) 33 35 { 34 36 if (len >= PMULL_MIN_LEN + 15 && 35 - static_branch_likely(&have_pmull) && crypto_simd_usable()) { 37 + static_branch_likely(&have_pmull) && likely(may_use_simd())) { 36 38 size_t n = -(uintptr_t)p & 15; 37 39 38 40 /* align p to 16-byte boundary */ ··· 61 63 static inline u32 crc32c_arch(u32 crc, const u8 *p, size_t len) 62 64 { 63 65 if (len >= PMULL_MIN_LEN + 15 && 64 - static_branch_likely(&have_pmull) && crypto_simd_usable()) { 66 + static_branch_likely(&have_pmull) && likely(may_use_simd())) { 65 67 size_t n = -(uintptr_t)p & 15; 66 68 67 69 /* align p to 16-byte boundary */
+2 -4
lib/crc/arm64/crc-t10dif.h
··· 7 7 8 8 #include <linux/cpufeature.h> 9 9 10 - #include <crypto/internal/simd.h> 11 - 12 10 #include <asm/neon.h> 13 11 #include <asm/simd.h> 14 12 ··· 23 25 { 24 26 if (length >= CRC_T10DIF_PMULL_CHUNK_SIZE) { 25 27 if (static_branch_likely(&have_pmull)) { 26 - if (crypto_simd_usable()) { 28 + if (likely(may_use_simd())) { 27 29 kernel_neon_begin(); 28 30 crc = crc_t10dif_pmull_p64(crc, data, length); 29 31 kernel_neon_end(); ··· 31 33 } 32 34 } else if (length > CRC_T10DIF_PMULL_CHUNK_SIZE && 33 35 static_branch_likely(&have_asimd) && 34 - crypto_simd_usable()) { 36 + likely(may_use_simd())) { 35 37 u8 buf[16]; 36 38 37 39 kernel_neon_begin();
+6 -5
lib/crc/arm64/crc32.h
··· 5 5 #include <asm/neon.h> 6 6 #include <asm/simd.h> 7 7 8 - #include <crypto/internal/simd.h> 9 - 10 8 // The minimum input length to consider the 4-way interleaved code path 11 9 static const size_t min_len = 1024; 12 10 ··· 21 23 if (!alternative_has_cap_likely(ARM64_HAS_CRC32)) 22 24 return crc32_le_base(crc, p, len); 23 25 24 - if (len >= min_len && cpu_have_named_feature(PMULL) && crypto_simd_usable()) { 26 + if (len >= min_len && cpu_have_named_feature(PMULL) && 27 + likely(may_use_simd())) { 25 28 kernel_neon_begin(); 26 29 crc = crc32_le_arm64_4way(crc, p, len); 27 30 kernel_neon_end(); ··· 42 43 if (!alternative_has_cap_likely(ARM64_HAS_CRC32)) 43 44 return crc32c_base(crc, p, len); 44 45 45 - if (len >= min_len && cpu_have_named_feature(PMULL) && crypto_simd_usable()) { 46 + if (len >= min_len && cpu_have_named_feature(PMULL) && 47 + likely(may_use_simd())) { 46 48 kernel_neon_begin(); 47 49 crc = crc32c_le_arm64_4way(crc, p, len); 48 50 kernel_neon_end(); ··· 63 63 if (!alternative_has_cap_likely(ARM64_HAS_CRC32)) 64 64 return crc32_be_base(crc, p, len); 65 65 66 - if (len >= min_len && cpu_have_named_feature(PMULL) && crypto_simd_usable()) { 66 + if (len >= min_len && cpu_have_named_feature(PMULL) && 67 + likely(may_use_simd())) { 67 68 kernel_neon_begin(); 68 69 crc = crc32_be_arm64_4way(crc, p, len); 69 70 kernel_neon_end();
+3 -2
lib/crc/powerpc/crc-t10dif.h
··· 6 6 * [based on crc32c-vpmsum_glue.c] 7 7 */ 8 8 9 + #include <asm/simd.h> 9 10 #include <asm/switch_to.h> 10 - #include <crypto/internal/simd.h> 11 11 #include <linux/cpufeature.h> 12 12 #include <linux/jump_label.h> 13 13 #include <linux/preempt.h> ··· 29 29 u32 crc = crci; 30 30 31 31 if (len < (VECTOR_BREAKPOINT + VMX_ALIGN) || 32 - !static_branch_likely(&have_vec_crypto) || !crypto_simd_usable()) 32 + !static_branch_likely(&have_vec_crypto) || 33 + unlikely(!may_use_simd())) 33 34 return crc_t10dif_generic(crc, p, len); 34 35 35 36 if ((unsigned long)p & VMX_ALIGN_MASK) {
+3 -2
lib/crc/powerpc/crc32.h
··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 + #include <asm/simd.h> 2 3 #include <asm/switch_to.h> 3 - #include <crypto/internal/simd.h> 4 4 #include <linux/cpufeature.h> 5 5 #include <linux/jump_label.h> 6 6 #include <linux/preempt.h> ··· 24 24 unsigned int tail; 25 25 26 26 if (len < (VECTOR_BREAKPOINT + VMX_ALIGN) || 27 - !static_branch_likely(&have_vec_crypto) || !crypto_simd_usable()) 27 + !static_branch_likely(&have_vec_crypto) || 28 + unlikely(!may_use_simd())) 28 29 return crc32c_base(crc, p, len); 29 30 30 31 if ((unsigned long)p & VMX_ALIGN_MASK) {
+1 -2
lib/crc/x86/crc-pclmul-template.h
··· 12 12 13 13 #include <asm/cpufeatures.h> 14 14 #include <asm/simd.h> 15 - #include <crypto/internal/simd.h> 16 15 #include <linux/static_call.h> 17 16 #include "crc-pclmul-consts.h" 18 17 ··· 56 57 #define CRC_PCLMUL(crc, p, len, prefix, consts, have_pclmulqdq) \ 57 58 do { \ 58 59 if ((len) >= 16 && static_branch_likely(&(have_pclmulqdq)) && \ 59 - crypto_simd_usable()) { \ 60 + likely(irq_fpu_usable())) { \ 60 61 const void *consts_ptr; \ 61 62 \ 62 63 consts_ptr = (consts).fold_across_128_bits_consts; \
+1 -1
lib/crc/x86/crc32.h
··· 44 44 return crc32c_base(crc, p, len); 45 45 46 46 if (IS_ENABLED(CONFIG_X86_64) && len >= CRC32C_PCLMUL_BREAKEVEN && 47 - static_branch_likely(&have_pclmulqdq) && crypto_simd_usable()) { 47 + static_branch_likely(&have_pclmulqdq) && likely(irq_fpu_usable())) { 48 48 /* 49 49 * Long length, the vector registers are usable, and the CPU is 50 50 * 64-bit and supports both CRC32 and PCLMULQDQ instructions.