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kernel
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linux
[ARM] oprofile: add ARM11 core support
Add basic support for the ARM11 profiling hardware. This is shared
between the ARM11 UP and ARM11 SMP oprofile support code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
authored by
Russell King
and committed by
Russell King
c265a762
62d0cfcb
+211
-1
+3
arch/arm/oprofile/Kconfig
+3
arch/arm/oprofile/Kconfig
+1
-1
arch/arm/oprofile/Makefile
+1
-1
arch/arm/oprofile/Makefile
+162
arch/arm/oprofile/op_model_arm11_core.c
+162
arch/arm/oprofile/op_model_arm11_core.c
···
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/**
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* @file op_model_arm11_core.c
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* ARM11 Event Monitor Driver
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* @remark Copyright 2004 ARM SMP Development Team
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*/
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/oprofile.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include "op_counter.h"
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#include "op_arm_model.h"
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#include "op_model_arm11_core.h"
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/*
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* ARM11 PMU support
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*/
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static inline void arm11_write_pmnc(u32 val)
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{
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/* upper 4bits and 7, 11 are write-as-0 */
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val &= 0x0ffff77f;
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asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r" (val));
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}
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static inline u32 arm11_read_pmnc(void)
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{
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u32 val;
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asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r" (val));
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return val;
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}
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static void arm11_reset_counter(unsigned int cnt)
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{
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u32 val = -(u32)counter_config[CPU_COUNTER(smp_processor_id(), cnt)].count;
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switch (cnt) {
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case CCNT:
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asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r" (val));
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break;
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case PMN0:
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asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r" (val));
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break;
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case PMN1:
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asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r" (val));
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break;
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}
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}
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int arm11_setup_pmu(void)
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{
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unsigned int cnt;
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u32 pmnc;
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if (arm11_read_pmnc() & PMCR_E) {
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printk(KERN_ERR "oprofile: CPU%u PMU still enabled when setup new event counter.\n", smp_processor_id());
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return -EBUSY;
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}
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/* initialize PMNC, reset overflow, D bit, C bit and P bit. */
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arm11_write_pmnc(PMCR_OFL_PMN0 | PMCR_OFL_PMN1 | PMCR_OFL_CCNT |
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PMCR_C | PMCR_P);
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for (pmnc = 0, cnt = PMN0; cnt <= CCNT; cnt++) {
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unsigned long event;
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if (!counter_config[CPU_COUNTER(smp_processor_id(), cnt)].enabled)
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continue;
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event = counter_config[CPU_COUNTER(smp_processor_id(), cnt)].event & 255;
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/*
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* Set event (if destined for PMNx counters)
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*/
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if (cnt == PMN0) {
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pmnc |= event << 20;
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} else if (cnt == PMN1) {
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pmnc |= event << 12;
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}
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/*
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* We don't need to set the event if it's a cycle count
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* Enable interrupt for this counter
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*/
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pmnc |= PMCR_IEN_PMN0 << cnt;
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arm11_reset_counter(cnt);
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}
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arm11_write_pmnc(pmnc);
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return 0;
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}
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int arm11_start_pmu(void)
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{
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arm11_write_pmnc(arm11_read_pmnc() | PMCR_E);
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return 0;
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}
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int arm11_stop_pmu(void)
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{
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unsigned int cnt;
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arm11_write_pmnc(arm11_read_pmnc() & ~PMCR_E);
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for (cnt = PMN0; cnt <= CCNT; cnt++)
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arm11_reset_counter(cnt);
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return 0;
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}
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/*
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* CPU counters' IRQ handler (one IRQ per CPU)
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*/
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static irqreturn_t arm11_pmu_interrupt(int irq, void *arg)
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{
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struct pt_regs *regs = get_irq_regs();
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unsigned int cnt;
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u32 pmnc;
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pmnc = arm11_read_pmnc();
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for (cnt = PMN0; cnt <= CCNT; cnt++) {
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if ((pmnc & (PMCR_OFL_PMN0 << cnt)) && (pmnc & (PMCR_IEN_PMN0 << cnt))) {
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arm11_reset_counter(cnt);
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oprofile_add_sample(regs, CPU_COUNTER(smp_processor_id(), cnt));
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}
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}
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/* Clear counter flag(s) */
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arm11_write_pmnc(pmnc);
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return IRQ_HANDLED;
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}
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int arm11_request_interrupts(int *irqs, int nr)
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{
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unsigned int i;
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int ret = 0;
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for(i = 0; i < nr; i++) {
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ret = request_irq(irqs[i], arm11_pmu_interrupt, IRQF_DISABLED, "CP15 PMU", NULL);
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if (ret != 0) {
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printk(KERN_ERR "oprofile: unable to request IRQ%u for MPCORE-EM\n",
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irqs[i]);
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break;
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}
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}
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if (i != nr)
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while (i-- != 0)
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free_irq(irqs[i], NULL);
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return ret;
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}
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void arm11_release_interrupts(int *irqs, int nr)
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{
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unsigned int i;
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for (i = 0; i < nr; i++)
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free_irq(irqs[i], NULL);
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}
+45
arch/arm/oprofile/op_model_arm11_core.h
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arch/arm/oprofile/op_model_arm11_core.h
···
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/**
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* @file op_model_arm11_core.h
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* ARM11 Event Monitor Driver
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* @remark Copyright 2004 ARM SMP Development Team
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* @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
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* @remark Copyright 2000-2004 MontaVista Software Inc
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* @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>
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* @remark Copyright 2004 Intel Corporation
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* @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
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* @remark Copyright 2004 Oprofile Authors
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*
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* @remark Read the file COPYING
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*
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* @author Zwane Mwaikambo
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*/
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#ifndef OP_MODEL_ARM11_CORE_H
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#define OP_MODEL_ARM11_CORE_H
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/*
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* Per-CPU PMCR
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*/
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#define PMCR_E (1 << 0) /* Enable */
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#define PMCR_P (1 << 1) /* Count reset */
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#define PMCR_C (1 << 2) /* Cycle counter reset */
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#define PMCR_D (1 << 3) /* Cycle counter counts every 64th cpu cycle */
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#define PMCR_IEN_PMN0 (1 << 4) /* Interrupt enable count reg 0 */
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#define PMCR_IEN_PMN1 (1 << 5) /* Interrupt enable count reg 1 */
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#define PMCR_IEN_CCNT (1 << 6) /* Interrupt enable cycle counter */
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#define PMCR_OFL_PMN0 (1 << 8) /* Count reg 0 overflow */
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#define PMCR_OFL_PMN1 (1 << 9) /* Count reg 1 overflow */
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#define PMCR_OFL_CCNT (1 << 10) /* Cycle counter overflow */
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#define PMN0 0
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#define PMN1 1
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#define CCNT 2
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#define CPU_COUNTER(cpu, counter) ((cpu) * 3 + (counter))
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int arm11_setup_pmu(void);
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int arm11_start_pmu(void);
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int arm11_stop_pmu(void);
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int arm11_request_interrupts(int *, int);
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void arm11_release_interrupts(int *, int);
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#endif