Merge branch 'icc-sm8350' into icc-next

+10

Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml

··· 71 71 - qcom,sm8250-mmss-noc 72 72 - qcom,sm8250-npu-noc 73 73 - qcom,sm8250-system-noc 74 + - qcom,sm8350-aggre1-noc 75 + - qcom,sm8350-aggre2-noc 76 + - qcom,sm8350-config-noc 77 + - qcom,sm8350-dc-noc 78 + - qcom,sm8350-gem-noc 79 + - qcom,sm8350-lpass-ag-noc 80 + - qcom,sm8350-mc-virt 81 + - qcom,sm8350-mmss-noc 82 + - qcom,sm8350-compute-noc 83 + - qcom,sm8350-system-noc 74 84 75 85 '#interconnect-cells': 76 86 enum: [ 1, 2 ]

+9

drivers/interconnect/qcom/Kconfig

··· 119 119 This is a driver for the Qualcomm Network-on-Chip on sm8250-based 120 120 platforms. 121 121 122 + config INTERCONNECT_QCOM_SM8350 123 + tristate "Qualcomm SM8350 interconnect driver" 124 + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE 125 + select INTERCONNECT_QCOM_RPMH 126 + select INTERCONNECT_QCOM_BCM_VOTER 127 + help 128 + This is a driver for the Qualcomm Network-on-Chip on SM8350-based 129 + platforms. 130 + 122 131 config INTERCONNECT_QCOM_SMD_RPM 123 132 tristate

+2

drivers/interconnect/qcom/Makefile

··· 13 13 qnoc-sdx55-objs := sdx55.o 14 14 qnoc-sm8150-objs := sm8150.o 15 15 qnoc-sm8250-objs := sm8250.o 16 + qnoc-sm8350-objs := sm8350.o 16 17 icc-smd-rpm-objs := smd-rpm.o icc-rpm.o 17 18 18 19 obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o ··· 29 28 obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o 30 29 obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o 31 30 obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o 31 + obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o 32 32 obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o

+633

drivers/interconnect/qcom/sm8350.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 4 + * Copyright (c) 2021, Linaro Limited 5 + * 6 + */ 7 + 8 + #include <linux/interconnect-provider.h> 9 + #include <linux/module.h> 10 + #include <linux/of_device.h> 11 + #include <dt-bindings/interconnect/qcom,sm8350.h> 12 + 13 + #include "bcm-voter.h" 14 + #include "icc-rpmh.h" 15 + #include "sm8350.h" 16 + 17 + DEFINE_QNODE(qhm_qspi, SM8350_MASTER_QSPI_0, 1, 4, SM8350_SLAVE_A1NOC_SNOC); 18 + DEFINE_QNODE(qhm_qup0, SM8350_MASTER_QUP_0, 1, 4, SM8350_SLAVE_A2NOC_SNOC); 19 + DEFINE_QNODE(qhm_qup1, SM8350_MASTER_QUP_1, 1, 4, SM8350_SLAVE_A1NOC_SNOC); 20 + DEFINE_QNODE(qhm_qup2, SM8350_MASTER_QUP_2, 1, 4, SM8350_SLAVE_A2NOC_SNOC); 21 + DEFINE_QNODE(qnm_a1noc_cfg, SM8350_MASTER_A1NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A1NOC); 22 + DEFINE_QNODE(xm_sdc4, SM8350_MASTER_SDCC_4, 1, 8, SM8350_SLAVE_A1NOC_SNOC); 23 + DEFINE_QNODE(xm_ufs_mem, SM8350_MASTER_UFS_MEM, 1, 8, SM8350_SLAVE_A1NOC_SNOC); 24 + DEFINE_QNODE(xm_usb3_0, SM8350_MASTER_USB3_0, 1, 8, SM8350_SLAVE_A1NOC_SNOC); 25 + DEFINE_QNODE(xm_usb3_1, SM8350_MASTER_USB3_1, 1, 8, SM8350_SLAVE_A1NOC_SNOC); 26 + DEFINE_QNODE(qhm_qdss_bam, SM8350_MASTER_QDSS_BAM, 1, 4, SM8350_SLAVE_A2NOC_SNOC); 27 + DEFINE_QNODE(qnm_a2noc_cfg, SM8350_MASTER_A2NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A2NOC); 28 + DEFINE_QNODE(qxm_crypto, SM8350_MASTER_CRYPTO, 1, 8, SM8350_SLAVE_A2NOC_SNOC); 29 + DEFINE_QNODE(qxm_ipa, SM8350_MASTER_IPA, 1, 8, SM8350_SLAVE_A2NOC_SNOC); 30 + DEFINE_QNODE(xm_pcie3_0, SM8350_MASTER_PCIE_0, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC); 31 + DEFINE_QNODE(xm_pcie3_1, SM8350_MASTER_PCIE_1, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC); 32 + DEFINE_QNODE(xm_qdss_etr, SM8350_MASTER_QDSS_ETR, 1, 8, SM8350_SLAVE_A2NOC_SNOC); 33 + DEFINE_QNODE(xm_sdc2, SM8350_MASTER_SDCC_2, 1, 8, SM8350_SLAVE_A2NOC_SNOC); 34 + DEFINE_QNODE(xm_ufs_card, SM8350_MASTER_UFS_CARD, 1, 8, SM8350_SLAVE_A2NOC_SNOC); 35 + DEFINE_QNODE(qnm_gemnoc_cnoc, SM8350_MASTER_GEM_NOC_CNOC, 1, 16, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU); 36 + DEFINE_QNODE(qnm_gemnoc_pcie, SM8350_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8350_SLAVE_PCIE_0, SM8350_SLAVE_PCIE_1); 37 + DEFINE_QNODE(xm_qdss_dap, SM8350_MASTER_QDSS_DAP, 1, 8, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU); 38 + DEFINE_QNODE(qnm_cnoc_dc_noc, SM8350_MASTER_CNOC_DC_NOC, 1, 4, SM8350_SLAVE_LLCC_CFG, SM8350_SLAVE_GEM_NOC_CFG); 39 + DEFINE_QNODE(alm_gpu_tcu, SM8350_MASTER_GPU_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); 40 + DEFINE_QNODE(alm_sys_tcu, SM8350_MASTER_SYS_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); 41 + DEFINE_QNODE(chm_apps, SM8350_MASTER_APPSS_PROC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC); 42 + DEFINE_QNODE(qnm_cmpnoc, SM8350_MASTER_COMPUTE_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); 43 + DEFINE_QNODE(qnm_gemnoc_cfg, SM8350_MASTER_GEM_NOC_CFG, 1, 4, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, SM8350_SLAVE_MCDMA_MS_MPU_CFG, SM8350_SLAVE_SERVICE_GEM_NOC_1, SM8350_SLAVE_SERVICE_GEM_NOC_2, SM8350_SLAVE_SERVICE_GEM_NOC); 44 + DEFINE_QNODE(qnm_gpu, SM8350_MASTER_GFX3D, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); 45 + DEFINE_QNODE(qnm_mnoc_hf, SM8350_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8350_SLAVE_LLCC); 46 + DEFINE_QNODE(qnm_mnoc_sf, SM8350_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); 47 + DEFINE_QNODE(qnm_pcie, SM8350_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); 48 + DEFINE_QNODE(qnm_snoc_gc, SM8350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8350_SLAVE_LLCC); 49 + DEFINE_QNODE(qnm_snoc_sf, SM8350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC); 50 + DEFINE_QNODE(qhm_config_noc, SM8350_MASTER_CNOC_LPASS_AG_NOC, 1, 4, SM8350_SLAVE_LPASS_CORE_CFG, SM8350_SLAVE_LPASS_LPI_CFG, SM8350_SLAVE_LPASS_MPU_CFG, SM8350_SLAVE_LPASS_TOP_CFG, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, SM8350_SLAVE_SERVICE_LPASS_AG_NOC); 51 + DEFINE_QNODE(llcc_mc, SM8350_MASTER_LLCC, 4, 4, SM8350_SLAVE_EBI1); 52 + DEFINE_QNODE(qnm_camnoc_hf, SM8350_MASTER_CAMNOC_HF, 2, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC); 53 + DEFINE_QNODE(qnm_camnoc_icp, SM8350_MASTER_CAMNOC_ICP, 1, 8, SM8350_SLAVE_MNOC_SF_MEM_NOC); 54 + DEFINE_QNODE(qnm_camnoc_sf, SM8350_MASTER_CAMNOC_SF, 2, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); 55 + DEFINE_QNODE(qnm_mnoc_cfg, SM8350_MASTER_CNOC_MNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_MNOC); 56 + DEFINE_QNODE(qnm_video0, SM8350_MASTER_VIDEO_P0, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); 57 + DEFINE_QNODE(qnm_video1, SM8350_MASTER_VIDEO_P1, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); 58 + DEFINE_QNODE(qnm_video_cvp, SM8350_MASTER_VIDEO_PROC, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); 59 + DEFINE_QNODE(qxm_mdp0, SM8350_MASTER_MDP0, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC); 60 + DEFINE_QNODE(qxm_mdp1, SM8350_MASTER_MDP1, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC); 61 + DEFINE_QNODE(qxm_rot, SM8350_MASTER_ROTATOR, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); 62 + DEFINE_QNODE(qhm_nsp_noc_config, SM8350_MASTER_CDSP_NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_NSP_NOC); 63 + DEFINE_QNODE(qxm_nsp, SM8350_MASTER_CDSP_PROC, 2, 32, SM8350_SLAVE_CDSP_MEM_NOC); 64 + DEFINE_QNODE(qnm_aggre1_noc, SM8350_MASTER_A1NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF); 65 + DEFINE_QNODE(qnm_aggre2_noc, SM8350_MASTER_A2NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF); 66 + DEFINE_QNODE(qnm_snoc_cfg, SM8350_MASTER_SNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_SNOC); 67 + DEFINE_QNODE(qxm_pimem, SM8350_MASTER_PIMEM, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC); 68 + DEFINE_QNODE(xm_gic, SM8350_MASTER_GIC, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC); 69 + DEFINE_QNODE(qnm_mnoc_hf_disp, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP); 70 + DEFINE_QNODE(qnm_mnoc_sf_disp, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP); 71 + DEFINE_QNODE(llcc_mc_disp, SM8350_MASTER_LLCC_DISP, 4, 4, SM8350_SLAVE_EBI1_DISP); 72 + DEFINE_QNODE(qxm_mdp0_disp, SM8350_MASTER_MDP0_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP); 73 + DEFINE_QNODE(qxm_mdp1_disp, SM8350_MASTER_MDP1_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP); 74 + DEFINE_QNODE(qxm_rot_disp, SM8350_MASTER_ROTATOR_DISP, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP); 75 + DEFINE_QNODE(qns_a1noc_snoc, SM8350_SLAVE_A1NOC_SNOC, 1, 16, SM8350_MASTER_A1NOC_SNOC); 76 + DEFINE_QNODE(srvc_aggre1_noc, SM8350_SLAVE_SERVICE_A1NOC, 1, 4); 77 + DEFINE_QNODE(qns_a2noc_snoc, SM8350_SLAVE_A2NOC_SNOC, 1, 16, SM8350_MASTER_A2NOC_SNOC); 78 + DEFINE_QNODE(qns_pcie_mem_noc, SM8350_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_MASTER_ANOC_PCIE_GEM_NOC); 79 + DEFINE_QNODE(srvc_aggre2_noc, SM8350_SLAVE_SERVICE_A2NOC, 1, 4); 80 + DEFINE_QNODE(qhs_ahb2phy0, SM8350_SLAVE_AHB2PHY_SOUTH, 1, 4); 81 + DEFINE_QNODE(qhs_ahb2phy1, SM8350_SLAVE_AHB2PHY_NORTH, 1, 4); 82 + DEFINE_QNODE(qhs_aoss, SM8350_SLAVE_AOSS, 1, 4); 83 + DEFINE_QNODE(qhs_apss, SM8350_SLAVE_APPSS, 1, 8); 84 + DEFINE_QNODE(qhs_camera_cfg, SM8350_SLAVE_CAMERA_CFG, 1, 4); 85 + DEFINE_QNODE(qhs_clk_ctl, SM8350_SLAVE_CLK_CTL, 1, 4); 86 + DEFINE_QNODE(qhs_compute_cfg, SM8350_SLAVE_CDSP_CFG, 1, 4); 87 + DEFINE_QNODE(qhs_cpr_cx, SM8350_SLAVE_RBCPR_CX_CFG, 1, 4); 88 + DEFINE_QNODE(qhs_cpr_mmcx, SM8350_SLAVE_RBCPR_MMCX_CFG, 1, 4); 89 + DEFINE_QNODE(qhs_cpr_mx, SM8350_SLAVE_RBCPR_MX_CFG, 1, 4); 90 + DEFINE_QNODE(qhs_crypto0_cfg, SM8350_SLAVE_CRYPTO_0_CFG, 1, 4); 91 + DEFINE_QNODE(qhs_cx_rdpm, SM8350_SLAVE_CX_RDPM, 1, 4); 92 + DEFINE_QNODE(qhs_dcc_cfg, SM8350_SLAVE_DCC_CFG, 1, 4); 93 + DEFINE_QNODE(qhs_display_cfg, SM8350_SLAVE_DISPLAY_CFG, 1, 4); 94 + DEFINE_QNODE(qhs_gpuss_cfg, SM8350_SLAVE_GFX3D_CFG, 1, 8); 95 + DEFINE_QNODE(qhs_hwkm, SM8350_SLAVE_HWKM, 1, 4); 96 + DEFINE_QNODE(qhs_imem_cfg, SM8350_SLAVE_IMEM_CFG, 1, 4); 97 + DEFINE_QNODE(qhs_ipa, SM8350_SLAVE_IPA_CFG, 1, 4); 98 + DEFINE_QNODE(qhs_ipc_router, SM8350_SLAVE_IPC_ROUTER_CFG, 1, 4); 99 + DEFINE_QNODE(qhs_lpass_cfg, SM8350_SLAVE_LPASS, 1, 4, SM8350_MASTER_CNOC_LPASS_AG_NOC); 100 + DEFINE_QNODE(qhs_mss_cfg, SM8350_SLAVE_CNOC_MSS, 1, 4); 101 + DEFINE_QNODE(qhs_mx_rdpm, SM8350_SLAVE_MX_RDPM, 1, 4); 102 + DEFINE_QNODE(qhs_pcie0_cfg, SM8350_SLAVE_PCIE_0_CFG, 1, 4); 103 + DEFINE_QNODE(qhs_pcie1_cfg, SM8350_SLAVE_PCIE_1_CFG, 1, 4); 104 + DEFINE_QNODE(qhs_pdm, SM8350_SLAVE_PDM, 1, 4); 105 + DEFINE_QNODE(qhs_pimem_cfg, SM8350_SLAVE_PIMEM_CFG, 1, 4); 106 + DEFINE_QNODE(qhs_pka_wrapper_cfg, SM8350_SLAVE_PKA_WRAPPER_CFG, 1, 4); 107 + DEFINE_QNODE(qhs_pmu_wrapper_cfg, SM8350_SLAVE_PMU_WRAPPER_CFG, 1, 4); 108 + DEFINE_QNODE(qhs_qdss_cfg, SM8350_SLAVE_QDSS_CFG, 1, 4); 109 + DEFINE_QNODE(qhs_qspi, SM8350_SLAVE_QSPI_0, 1, 4); 110 + DEFINE_QNODE(qhs_qup0, SM8350_SLAVE_QUP_0, 1, 4); 111 + DEFINE_QNODE(qhs_qup1, SM8350_SLAVE_QUP_1, 1, 4); 112 + DEFINE_QNODE(qhs_qup2, SM8350_SLAVE_QUP_2, 1, 4); 113 + DEFINE_QNODE(qhs_sdc2, SM8350_SLAVE_SDCC_2, 1, 4); 114 + DEFINE_QNODE(qhs_sdc4, SM8350_SLAVE_SDCC_4, 1, 4); 115 + DEFINE_QNODE(qhs_security, SM8350_SLAVE_SECURITY, 1, 4); 116 + DEFINE_QNODE(qhs_spss_cfg, SM8350_SLAVE_SPSS_CFG, 1, 4); 117 + DEFINE_QNODE(qhs_tcsr, SM8350_SLAVE_TCSR, 1, 4); 118 + DEFINE_QNODE(qhs_tlmm, SM8350_SLAVE_TLMM, 1, 4); 119 + DEFINE_QNODE(qhs_ufs_card_cfg, SM8350_SLAVE_UFS_CARD_CFG, 1, 4); 120 + DEFINE_QNODE(qhs_ufs_mem_cfg, SM8350_SLAVE_UFS_MEM_CFG, 1, 4); 121 + DEFINE_QNODE(qhs_usb3_0, SM8350_SLAVE_USB3_0, 1, 4); 122 + DEFINE_QNODE(qhs_usb3_1, SM8350_SLAVE_USB3_1, 1, 4); 123 + DEFINE_QNODE(qhs_venus_cfg, SM8350_SLAVE_VENUS_CFG, 1, 4); 124 + DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8350_SLAVE_VSENSE_CTRL_CFG, 1, 4); 125 + DEFINE_QNODE(qns_a1_noc_cfg, SM8350_SLAVE_A1NOC_CFG, 1, 4); 126 + DEFINE_QNODE(qns_a2_noc_cfg, SM8350_SLAVE_A2NOC_CFG, 1, 4); 127 + DEFINE_QNODE(qns_ddrss_cfg, SM8350_SLAVE_DDRSS_CFG, 1, 4); 128 + DEFINE_QNODE(qns_mnoc_cfg, SM8350_SLAVE_CNOC_MNOC_CFG, 1, 4); 129 + DEFINE_QNODE(qns_snoc_cfg, SM8350_SLAVE_SNOC_CFG, 1, 4); 130 + DEFINE_QNODE(qxs_boot_imem, SM8350_SLAVE_BOOT_IMEM, 1, 8); 131 + DEFINE_QNODE(qxs_imem, SM8350_SLAVE_IMEM, 1, 8); 132 + DEFINE_QNODE(qxs_pimem, SM8350_SLAVE_PIMEM, 1, 8); 133 + DEFINE_QNODE(srvc_cnoc, SM8350_SLAVE_SERVICE_CNOC, 1, 4); 134 + DEFINE_QNODE(xs_pcie_0, SM8350_SLAVE_PCIE_0, 1, 8); 135 + DEFINE_QNODE(xs_pcie_1, SM8350_SLAVE_PCIE_1, 1, 8); 136 + DEFINE_QNODE(xs_qdss_stm, SM8350_SLAVE_QDSS_STM, 1, 4); 137 + DEFINE_QNODE(xs_sys_tcu_cfg, SM8350_SLAVE_TCU, 1, 8); 138 + DEFINE_QNODE(qhs_llcc, SM8350_SLAVE_LLCC_CFG, 1, 4); 139 + DEFINE_QNODE(qns_gemnoc, SM8350_SLAVE_GEM_NOC_CFG, 1, 4); 140 + DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); 141 + DEFINE_QNODE(qhs_modem_ms_mpu_cfg, SM8350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4); 142 + DEFINE_QNODE(qns_gem_noc_cnoc, SM8350_SLAVE_GEM_NOC_CNOC, 1, 16, SM8350_MASTER_GEM_NOC_CNOC); 143 + DEFINE_QNODE(qns_llcc, SM8350_SLAVE_LLCC, 4, 16, SM8350_MASTER_LLCC); 144 + DEFINE_QNODE(qns_pcie, SM8350_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8); 145 + DEFINE_QNODE(srvc_even_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_1, 1, 4); 146 + DEFINE_QNODE(srvc_odd_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_2, 1, 4); 147 + DEFINE_QNODE(srvc_sys_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC, 1, 4); 148 + DEFINE_QNODE(qhs_lpass_core, SM8350_SLAVE_LPASS_CORE_CFG, 1, 4); 149 + DEFINE_QNODE(qhs_lpass_lpi, SM8350_SLAVE_LPASS_LPI_CFG, 1, 4); 150 + DEFINE_QNODE(qhs_lpass_mpu, SM8350_SLAVE_LPASS_MPU_CFG, 1, 4); 151 + DEFINE_QNODE(qhs_lpass_top, SM8350_SLAVE_LPASS_TOP_CFG, 1, 4); 152 + DEFINE_QNODE(srvc_niu_aml_noc, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, 1, 4); 153 + DEFINE_QNODE(srvc_niu_lpass_agnoc, SM8350_SLAVE_SERVICE_LPASS_AG_NOC, 1, 4); 154 + DEFINE_QNODE(ebi, SM8350_SLAVE_EBI1, 4, 4); 155 + DEFINE_QNODE(qns_mem_noc_hf, SM8350_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC); 156 + DEFINE_QNODE(qns_mem_noc_sf, SM8350_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC); 157 + DEFINE_QNODE(srvc_mnoc, SM8350_SLAVE_SERVICE_MNOC, 1, 4); 158 + DEFINE_QNODE(qns_nsp_gemnoc, SM8350_SLAVE_CDSP_MEM_NOC, 2, 32, SM8350_MASTER_COMPUTE_NOC); 159 + DEFINE_QNODE(service_nsp_noc, SM8350_SLAVE_SERVICE_NSP_NOC, 1, 4); 160 + DEFINE_QNODE(qns_gemnoc_gc, SM8350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8350_MASTER_SNOC_GC_MEM_NOC); 161 + DEFINE_QNODE(qns_gemnoc_sf, SM8350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8350_MASTER_SNOC_SF_MEM_NOC); 162 + DEFINE_QNODE(srvc_snoc, SM8350_SLAVE_SERVICE_SNOC, 1, 4); 163 + DEFINE_QNODE(qns_llcc_disp, SM8350_SLAVE_LLCC_DISP, 4, 16, SM8350_MASTER_LLCC_DISP); 164 + DEFINE_QNODE(ebi_disp, SM8350_SLAVE_EBI1_DISP, 4, 4); 165 + DEFINE_QNODE(qns_mem_noc_hf_disp, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP); 166 + DEFINE_QNODE(qns_mem_noc_sf_disp, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP); 167 + 168 + DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); 169 + DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); 170 + DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie); 171 + DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_apss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_cfg, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_hwkm, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_mss_cfg, &qhs_mx_rdpm, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_security, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, &qns_a2_noc_cfg, &qns_ddrss_cfg, &qns_mnoc_cfg, &qns_snoc_cfg, &srvc_cnoc); 172 + DEFINE_QBCM(bcm_cn2, "CN2", false, &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4); 173 + DEFINE_QBCM(bcm_co0, "CO0", false, &qns_nsp_gemnoc); 174 + DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_nsp); 175 + DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); 176 + DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); 177 + DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1); 178 + DEFINE_QBCM(bcm_mm4, "MM4", false, &qns_mem_noc_sf); 179 + DEFINE_QBCM(bcm_mm5, "MM5", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp, &qxm_rot); 180 + DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); 181 + DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu); 182 + DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); 183 + DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps); 184 + DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); 185 + DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); 186 + DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); 187 + DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); 188 + DEFINE_QBCM(bcm_sn5, "SN5", false, &xm_pcie3_0); 189 + DEFINE_QBCM(bcm_sn6, "SN6", false, &xm_pcie3_1); 190 + DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc); 191 + DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc); 192 + DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc); 193 + DEFINE_QBCM(bcm_acv_disp, "ACV", false, &ebi_disp); 194 + DEFINE_QBCM(bcm_mc0_disp, "MC0", false, &ebi_disp); 195 + DEFINE_QBCM(bcm_mm0_disp, "MM0", false, &qns_mem_noc_hf_disp); 196 + DEFINE_QBCM(bcm_mm1_disp, "MM1", false, &qxm_mdp0_disp, &qxm_mdp1_disp); 197 + DEFINE_QBCM(bcm_mm4_disp, "MM4", false, &qns_mem_noc_sf_disp); 198 + DEFINE_QBCM(bcm_mm5_disp, "MM5", false, &qxm_rot_disp); 199 + DEFINE_QBCM(bcm_sh0_disp, "SH0", false, &qns_llcc_disp); 200 + 201 + static struct qcom_icc_bcm *aggre1_noc_bcms[] = { 202 + }; 203 + 204 + static struct qcom_icc_node *aggre1_noc_nodes[] = { 205 + [MASTER_QSPI_0] = &qhm_qspi, 206 + [MASTER_QUP_1] = &qhm_qup1, 207 + [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, 208 + [MASTER_SDCC_4] = &xm_sdc4, 209 + [MASTER_UFS_MEM] = &xm_ufs_mem, 210 + [MASTER_USB3_0] = &xm_usb3_0, 211 + [MASTER_USB3_1] = &xm_usb3_1, 212 + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 213 + [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 214 + }; 215 + 216 + static struct qcom_icc_desc sm8350_aggre1_noc = { 217 + .nodes = aggre1_noc_nodes, 218 + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 219 + .bcms = aggre1_noc_bcms, 220 + .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 221 + }; 222 + 223 + static struct qcom_icc_bcm *aggre2_noc_bcms[] = { 224 + &bcm_ce0, 225 + &bcm_sn5, 226 + &bcm_sn6, 227 + &bcm_sn14, 228 + }; 229 + 230 + static struct qcom_icc_node *aggre2_noc_nodes[] = { 231 + [MASTER_QDSS_BAM] = &qhm_qdss_bam, 232 + [MASTER_QUP_0] = &qhm_qup0, 233 + [MASTER_QUP_2] = &qhm_qup2, 234 + [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, 235 + [MASTER_CRYPTO] = &qxm_crypto, 236 + [MASTER_IPA] = &qxm_ipa, 237 + [MASTER_PCIE_0] = &xm_pcie3_0, 238 + [MASTER_PCIE_1] = &xm_pcie3_1, 239 + [MASTER_QDSS_ETR] = &xm_qdss_etr, 240 + [MASTER_SDCC_2] = &xm_sdc2, 241 + [MASTER_UFS_CARD] = &xm_ufs_card, 242 + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 243 + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 244 + [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 245 + }; 246 + 247 + static struct qcom_icc_desc sm8350_aggre2_noc = { 248 + .nodes = aggre2_noc_nodes, 249 + .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 250 + .bcms = aggre2_noc_bcms, 251 + .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 252 + }; 253 + 254 + static struct qcom_icc_bcm *config_noc_bcms[] = { 255 + &bcm_cn0, 256 + &bcm_cn1, 257 + &bcm_cn2, 258 + &bcm_sn3, 259 + &bcm_sn4, 260 + }; 261 + 262 + static struct qcom_icc_node *config_noc_nodes[] = { 263 + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 264 + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 265 + [MASTER_QDSS_DAP] = &xm_qdss_dap, 266 + [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 267 + [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 268 + [SLAVE_AOSS] = &qhs_aoss, 269 + [SLAVE_APPSS] = &qhs_apss, 270 + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 271 + [SLAVE_CLK_CTL] = &qhs_clk_ctl, 272 + [SLAVE_CDSP_CFG] = &qhs_compute_cfg, 273 + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 274 + [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 275 + [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 276 + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 277 + [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 278 + [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 279 + [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 280 + [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 281 + [SLAVE_HWKM] = &qhs_hwkm, 282 + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 283 + [SLAVE_IPA_CFG] = &qhs_ipa, 284 + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 285 + [SLAVE_LPASS] = &qhs_lpass_cfg, 286 + [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 287 + [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 288 + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 289 + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 290 + [SLAVE_PDM] = &qhs_pdm, 291 + [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 292 + [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg, 293 + [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg, 294 + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 295 + [SLAVE_QSPI_0] = &qhs_qspi, 296 + [SLAVE_QUP_0] = &qhs_qup0, 297 + [SLAVE_QUP_1] = &qhs_qup1, 298 + [SLAVE_QUP_2] = &qhs_qup2, 299 + [SLAVE_SDCC_2] = &qhs_sdc2, 300 + [SLAVE_SDCC_4] = &qhs_sdc4, 301 + [SLAVE_SECURITY] = &qhs_security, 302 + [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 303 + [SLAVE_TCSR] = &qhs_tcsr, 304 + [SLAVE_TLMM] = &qhs_tlmm, 305 + [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 306 + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 307 + [SLAVE_USB3_0] = &qhs_usb3_0, 308 + [SLAVE_USB3_1] = &qhs_usb3_1, 309 + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 310 + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 311 + [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, 312 + [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, 313 + [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 314 + [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, 315 + [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 316 + [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 317 + [SLAVE_IMEM] = &qxs_imem, 318 + [SLAVE_PIMEM] = &qxs_pimem, 319 + [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 320 + [SLAVE_PCIE_0] = &xs_pcie_0, 321 + [SLAVE_PCIE_1] = &xs_pcie_1, 322 + [SLAVE_QDSS_STM] = &xs_qdss_stm, 323 + [SLAVE_TCU] = &xs_sys_tcu_cfg, 324 + }; 325 + 326 + static struct qcom_icc_desc sm8350_config_noc = { 327 + .nodes = config_noc_nodes, 328 + .num_nodes = ARRAY_SIZE(config_noc_nodes), 329 + .bcms = config_noc_bcms, 330 + .num_bcms = ARRAY_SIZE(config_noc_bcms), 331 + }; 332 + 333 + static struct qcom_icc_bcm *dc_noc_bcms[] = { 334 + }; 335 + 336 + static struct qcom_icc_node *dc_noc_nodes[] = { 337 + [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, 338 + [SLAVE_LLCC_CFG] = &qhs_llcc, 339 + [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 340 + }; 341 + 342 + static struct qcom_icc_desc sm8350_dc_noc = { 343 + .nodes = dc_noc_nodes, 344 + .num_nodes = ARRAY_SIZE(dc_noc_nodes), 345 + .bcms = dc_noc_bcms, 346 + .num_bcms = ARRAY_SIZE(dc_noc_bcms), 347 + }; 348 + 349 + static struct qcom_icc_bcm *gem_noc_bcms[] = { 350 + &bcm_sh0, 351 + &bcm_sh2, 352 + &bcm_sh3, 353 + &bcm_sh4, 354 + &bcm_sh0_disp, 355 + }; 356 + 357 + static struct qcom_icc_node *gem_noc_nodes[] = { 358 + [MASTER_GPU_TCU] = &alm_gpu_tcu, 359 + [MASTER_SYS_TCU] = &alm_sys_tcu, 360 + [MASTER_APPSS_PROC] = &chm_apps, 361 + [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 362 + [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, 363 + [MASTER_GFX3D] = &qnm_gpu, 364 + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 365 + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 366 + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 367 + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 368 + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 369 + [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 370 + [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg, 371 + [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 372 + [SLAVE_LLCC] = &qns_llcc, 373 + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 374 + [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 375 + [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 376 + [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 377 + [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp, 378 + [MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp, 379 + [SLAVE_LLCC_DISP] = &qns_llcc_disp, 380 + }; 381 + 382 + static struct qcom_icc_desc sm8350_gem_noc = { 383 + .nodes = gem_noc_nodes, 384 + .num_nodes = ARRAY_SIZE(gem_noc_nodes), 385 + .bcms = gem_noc_bcms, 386 + .num_bcms = ARRAY_SIZE(gem_noc_bcms), 387 + }; 388 + 389 + static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { 390 + }; 391 + 392 + static struct qcom_icc_node *lpass_ag_noc_nodes[] = { 393 + [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 394 + [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 395 + [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 396 + [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 397 + [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 398 + [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 399 + [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 400 + }; 401 + 402 + static struct qcom_icc_desc sm8350_lpass_ag_noc = { 403 + .nodes = lpass_ag_noc_nodes, 404 + .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 405 + .bcms = lpass_ag_noc_bcms, 406 + .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 407 + }; 408 + 409 + static struct qcom_icc_bcm *mc_virt_bcms[] = { 410 + &bcm_acv, 411 + &bcm_mc0, 412 + &bcm_acv_disp, 413 + &bcm_mc0_disp, 414 + }; 415 + 416 + static struct qcom_icc_node *mc_virt_nodes[] = { 417 + [MASTER_LLCC] = &llcc_mc, 418 + [SLAVE_EBI1] = &ebi, 419 + [MASTER_LLCC_DISP] = &llcc_mc_disp, 420 + [SLAVE_EBI1_DISP] = &ebi_disp, 421 + }; 422 + 423 + static struct qcom_icc_desc sm8350_mc_virt = { 424 + .nodes = mc_virt_nodes, 425 + .num_nodes = ARRAY_SIZE(mc_virt_nodes), 426 + .bcms = mc_virt_bcms, 427 + .num_bcms = ARRAY_SIZE(mc_virt_bcms), 428 + }; 429 + 430 + static struct qcom_icc_bcm *mmss_noc_bcms[] = { 431 + &bcm_mm0, 432 + &bcm_mm1, 433 + &bcm_mm4, 434 + &bcm_mm5, 435 + &bcm_mm0_disp, 436 + &bcm_mm1_disp, 437 + &bcm_mm4_disp, 438 + &bcm_mm5_disp, 439 + }; 440 + 441 + static struct qcom_icc_node *mmss_noc_nodes[] = { 442 + [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 443 + [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 444 + [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 445 + [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, 446 + [MASTER_VIDEO_P0] = &qnm_video0, 447 + [MASTER_VIDEO_P1] = &qnm_video1, 448 + [MASTER_VIDEO_PROC] = &qnm_video_cvp, 449 + [MASTER_MDP0] = &qxm_mdp0, 450 + [MASTER_MDP1] = &qxm_mdp1, 451 + [MASTER_ROTATOR] = &qxm_rot, 452 + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 453 + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 454 + [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 455 + [MASTER_MDP0_DISP] = &qxm_mdp0_disp, 456 + [MASTER_MDP1_DISP] = &qxm_mdp1_disp, 457 + [MASTER_ROTATOR_DISP] = &qxm_rot_disp, 458 + [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp, 459 + [SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp, 460 + }; 461 + 462 + static struct qcom_icc_desc sm8350_mmss_noc = { 463 + .nodes = mmss_noc_nodes, 464 + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 465 + .bcms = mmss_noc_bcms, 466 + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 467 + }; 468 + 469 + static struct qcom_icc_bcm *nsp_noc_bcms[] = { 470 + &bcm_co0, 471 + &bcm_co3, 472 + }; 473 + 474 + static struct qcom_icc_node *nsp_noc_nodes[] = { 475 + [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 476 + [MASTER_CDSP_PROC] = &qxm_nsp, 477 + [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 478 + [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 479 + }; 480 + 481 + static struct qcom_icc_desc sm8350_compute_noc = { 482 + .nodes = nsp_noc_nodes, 483 + .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 484 + .bcms = nsp_noc_bcms, 485 + .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 486 + }; 487 + 488 + static struct qcom_icc_bcm *system_noc_bcms[] = { 489 + &bcm_sn0, 490 + &bcm_sn2, 491 + &bcm_sn7, 492 + &bcm_sn8, 493 + }; 494 + 495 + static struct qcom_icc_node *system_noc_nodes[] = { 496 + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 497 + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 498 + [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 499 + [MASTER_PIMEM] = &qxm_pimem, 500 + [MASTER_GIC] = &xm_gic, 501 + [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 502 + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 503 + [SLAVE_SERVICE_SNOC] = &srvc_snoc, 504 + }; 505 + 506 + static struct qcom_icc_desc sm8350_system_noc = { 507 + .nodes = system_noc_nodes, 508 + .num_nodes = ARRAY_SIZE(system_noc_nodes), 509 + .bcms = system_noc_bcms, 510 + .num_bcms = ARRAY_SIZE(system_noc_bcms), 511 + }; 512 + 513 + static int qnoc_probe(struct platform_device *pdev) 514 + { 515 + const struct qcom_icc_desc *desc; 516 + struct icc_onecell_data *data; 517 + struct icc_provider *provider; 518 + struct qcom_icc_node **qnodes; 519 + struct qcom_icc_provider *qp; 520 + struct icc_node *node; 521 + size_t num_nodes, i; 522 + int ret; 523 + 524 + desc = of_device_get_match_data(&pdev->dev); 525 + if (!desc) 526 + return -EINVAL; 527 + 528 + qnodes = desc->nodes; 529 + num_nodes = desc->num_nodes; 530 + 531 + qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL); 532 + if (!qp) 533 + return -ENOMEM; 534 + 535 + data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL); 536 + if (!data) 537 + return -ENOMEM; 538 + 539 + provider = &qp->provider; 540 + provider->dev = &pdev->dev; 541 + provider->set = qcom_icc_set; 542 + provider->pre_aggregate = qcom_icc_pre_aggregate; 543 + provider->aggregate = qcom_icc_aggregate; 544 + provider->xlate = of_icc_xlate_onecell; 545 + INIT_LIST_HEAD(&provider->nodes); 546 + provider->data = data; 547 + 548 + qp->dev = &pdev->dev; 549 + qp->bcms = desc->bcms; 550 + qp->num_bcms = desc->num_bcms; 551 + 552 + qp->voter = of_bcm_voter_get(qp->dev, NULL); 553 + if (IS_ERR(qp->voter)) 554 + return PTR_ERR(qp->voter); 555 + 556 + ret = icc_provider_add(provider); 557 + if (ret) { 558 + dev_err(&pdev->dev, "error adding interconnect provider\n"); 559 + return ret; 560 + } 561 + 562 + for (i = 0; i < qp->num_bcms; i++) 563 + qcom_icc_bcm_init(qp->bcms[i], &pdev->dev); 564 + 565 + for (i = 0; i < num_nodes; i++) { 566 + size_t j; 567 + 568 + if (!qnodes[i]) 569 + continue; 570 + 571 + node = icc_node_create(qnodes[i]->id); 572 + if (IS_ERR(node)) { 573 + ret = PTR_ERR(node); 574 + goto err; 575 + } 576 + 577 + node->name = qnodes[i]->name; 578 + node->data = qnodes[i]; 579 + icc_node_add(node, provider); 580 + 581 + for (j = 0; j < qnodes[i]->num_links; j++) 582 + icc_link_create(node, qnodes[i]->links[j]); 583 + 584 + data->nodes[i] = node; 585 + } 586 + data->num_nodes = num_nodes; 587 + 588 + platform_set_drvdata(pdev, qp); 589 + 590 + return ret; 591 + 592 + err: 593 + icc_nodes_remove(provider); 594 + icc_provider_del(provider); 595 + return ret; 596 + } 597 + 598 + static int qnoc_remove(struct platform_device *pdev) 599 + { 600 + struct qcom_icc_provider *qp = platform_get_drvdata(pdev); 601 + 602 + icc_nodes_remove(&qp->provider); 603 + return icc_provider_del(&qp->provider); 604 + } 605 + 606 + static const struct of_device_id qnoc_of_match[] = { 607 + { .compatible = "qcom,sm8350-aggre1-noc", .data = &sm8350_aggre1_noc}, 608 + { .compatible = "qcom,sm8350-aggre2-noc", .data = &sm8350_aggre2_noc}, 609 + { .compatible = "qcom,sm8350-config-noc", .data = &sm8350_config_noc}, 610 + { .compatible = "qcom,sm8350-dc-noc", .data = &sm8350_dc_noc}, 611 + { .compatible = "qcom,sm8350-gem-noc", .data = &sm8350_gem_noc}, 612 + { .compatible = "qcom,sm8350-lpass-ag-noc", .data = &sm8350_lpass_ag_noc}, 613 + { .compatible = "qcom,sm8350-mc-virt", .data = &sm8350_mc_virt}, 614 + { .compatible = "qcom,sm8350-mmss-noc", .data = &sm8350_mmss_noc}, 615 + { .compatible = "qcom,sm8350-compute-noc", .data = &sm8350_compute_noc}, 616 + { .compatible = "qcom,sm8350-system-noc", .data = &sm8350_system_noc}, 617 + { } 618 + }; 619 + MODULE_DEVICE_TABLE(of, qnoc_of_match); 620 + 621 + static struct platform_driver qnoc_driver = { 622 + .probe = qnoc_probe, 623 + .remove = qnoc_remove, 624 + .driver = { 625 + .name = "qnoc-sm8350", 626 + .of_match_table = qnoc_of_match, 627 + .sync_state = icc_sync_state, 628 + }, 629 + }; 630 + module_platform_driver(qnoc_driver); 631 + 632 + MODULE_DESCRIPTION("SM8350 NoC driver"); 633 + MODULE_LICENSE("GPL v2");

+168

drivers/interconnect/qcom/sm8350.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Qualcomm SM8350 interconnect IDs 4 + * 5 + * Copyright (c) 2021, Linaro Limited 6 + */ 7 + 8 + #ifndef __DRIVERS_INTERCONNECT_QCOM_SM8350_H 9 + #define __DRIVERS_INTERCONNECT_QCOM_SM8350_H 10 + 11 + #define SM8350_MASTER_GPU_TCU 0 12 + #define SM8350_MASTER_SYS_TCU 1 13 + #define SM8350_MASTER_APPSS_PROC 2 14 + #define SM8350_MASTER_LLCC 3 15 + #define SM8350_MASTER_CNOC_LPASS_AG_NOC 4 16 + #define SM8350_MASTER_CDSP_NOC_CFG 5 17 + #define SM8350_MASTER_QDSS_BAM 6 18 + #define SM8350_MASTER_QSPI_0 7 19 + #define SM8350_MASTER_QUP_0 8 20 + #define SM8350_MASTER_QUP_1 9 21 + #define SM8350_MASTER_QUP_2 10 22 + #define SM8350_MASTER_A1NOC_CFG 11 23 + #define SM8350_MASTER_A2NOC_CFG 12 24 + #define SM8350_MASTER_A1NOC_SNOC 13 25 + #define SM8350_MASTER_A2NOC_SNOC 14 26 + #define SM8350_MASTER_CAMNOC_HF 15 27 + #define SM8350_MASTER_CAMNOC_ICP 16 28 + #define SM8350_MASTER_CAMNOC_SF 17 29 + #define SM8350_MASTER_COMPUTE_NOC 18 30 + #define SM8350_MASTER_CNOC_DC_NOC 19 31 + #define SM8350_MASTER_GEM_NOC_CFG 20 32 + #define SM8350_MASTER_GEM_NOC_CNOC 21 33 + #define SM8350_MASTER_GEM_NOC_PCIE_SNOC 22 34 + #define SM8350_MASTER_GFX3D 23 35 + #define SM8350_MASTER_CNOC_MNOC_CFG 24 36 + #define SM8350_MASTER_MNOC_HF_MEM_NOC 25 37 + #define SM8350_MASTER_MNOC_SF_MEM_NOC 26 38 + #define SM8350_MASTER_ANOC_PCIE_GEM_NOC 27 39 + #define SM8350_MASTER_SNOC_CFG 28 40 + #define SM8350_MASTER_SNOC_GC_MEM_NOC 29 41 + #define SM8350_MASTER_SNOC_SF_MEM_NOC 30 42 + #define SM8350_MASTER_VIDEO_P0 31 43 + #define SM8350_MASTER_VIDEO_P1 32 44 + #define SM8350_MASTER_VIDEO_PROC 33 45 + #define SM8350_MASTER_QUP_CORE_0 34 46 + #define SM8350_MASTER_QUP_CORE_1 35 47 + #define SM8350_MASTER_QUP_CORE_2 36 48 + #define SM8350_MASTER_CRYPTO 37 49 + #define SM8350_MASTER_IPA 38 50 + #define SM8350_MASTER_MDP0 39 51 + #define SM8350_MASTER_MDP1 40 52 + #define SM8350_MASTER_CDSP_PROC 41 53 + #define SM8350_MASTER_PIMEM 42 54 + #define SM8350_MASTER_ROTATOR 43 55 + #define SM8350_MASTER_GIC 44 56 + #define SM8350_MASTER_PCIE_0 45 57 + #define SM8350_MASTER_PCIE_1 46 58 + #define SM8350_MASTER_QDSS_DAP 47 59 + #define SM8350_MASTER_QDSS_ETR 48 60 + #define SM8350_MASTER_SDCC_2 49 61 + #define SM8350_MASTER_SDCC_4 50 62 + #define SM8350_MASTER_UFS_CARD 51 63 + #define SM8350_MASTER_UFS_MEM 52 64 + #define SM8350_MASTER_USB3_0 53 65 + #define SM8350_MASTER_USB3_1 54 66 + #define SM8350_SLAVE_EBI1 55 67 + #define SM8350_SLAVE_AHB2PHY_SOUTH 56 68 + #define SM8350_SLAVE_AHB2PHY_NORTH 57 69 + #define SM8350_SLAVE_AOSS 58 70 + #define SM8350_SLAVE_APPSS 59 71 + #define SM8350_SLAVE_CAMERA_CFG 60 72 + #define SM8350_SLAVE_CLK_CTL 61 73 + #define SM8350_SLAVE_CDSP_CFG 62 74 + #define SM8350_SLAVE_RBCPR_CX_CFG 63 75 + #define SM8350_SLAVE_RBCPR_MMCX_CFG 64 76 + #define SM8350_SLAVE_RBCPR_MX_CFG 65 77 + #define SM8350_SLAVE_CRYPTO_0_CFG 66 78 + #define SM8350_SLAVE_CX_RDPM 67 79 + #define SM8350_SLAVE_DCC_CFG 68 80 + #define SM8350_SLAVE_DISPLAY_CFG 69 81 + #define SM8350_SLAVE_GFX3D_CFG 70 82 + #define SM8350_SLAVE_HWKM 71 83 + #define SM8350_SLAVE_IMEM_CFG 72 84 + #define SM8350_SLAVE_IPA_CFG 73 85 + #define SM8350_SLAVE_IPC_ROUTER_CFG 74 86 + #define SM8350_SLAVE_LLCC_CFG 75 87 + #define SM8350_SLAVE_LPASS 76 88 + #define SM8350_SLAVE_LPASS_CORE_CFG 77 89 + #define SM8350_SLAVE_LPASS_LPI_CFG 78 90 + #define SM8350_SLAVE_LPASS_MPU_CFG 79 91 + #define SM8350_SLAVE_LPASS_TOP_CFG 80 92 + #define SM8350_SLAVE_MSS_PROC_MS_MPU_CFG 81 93 + #define SM8350_SLAVE_MCDMA_MS_MPU_CFG 82 94 + #define SM8350_SLAVE_CNOC_MSS 83 95 + #define SM8350_SLAVE_MX_RDPM 84 96 + #define SM8350_SLAVE_PCIE_0_CFG 85 97 + #define SM8350_SLAVE_PCIE_1_CFG 86 98 + #define SM8350_SLAVE_PDM 87 99 + #define SM8350_SLAVE_PIMEM_CFG 88 100 + #define SM8350_SLAVE_PKA_WRAPPER_CFG 89 101 + #define SM8350_SLAVE_PMU_WRAPPER_CFG 90 102 + #define SM8350_SLAVE_QDSS_CFG 91 103 + #define SM8350_SLAVE_QSPI_0 92 104 + #define SM8350_SLAVE_QUP_0 93 105 + #define SM8350_SLAVE_QUP_1 94 106 + #define SM8350_SLAVE_QUP_2 95 107 + #define SM8350_SLAVE_SDCC_2 96 108 + #define SM8350_SLAVE_SDCC_4 97 109 + #define SM8350_SLAVE_SECURITY 98 110 + #define SM8350_SLAVE_SPSS_CFG 99 111 + #define SM8350_SLAVE_TCSR 100 112 + #define SM8350_SLAVE_TLMM 101 113 + #define SM8350_SLAVE_UFS_CARD_CFG 102 114 + #define SM8350_SLAVE_UFS_MEM_CFG 103 115 + #define SM8350_SLAVE_USB3_0 104 116 + #define SM8350_SLAVE_USB3_1 105 117 + #define SM8350_SLAVE_VENUS_CFG 106 118 + #define SM8350_SLAVE_VSENSE_CTRL_CFG 107 119 + #define SM8350_SLAVE_A1NOC_CFG 108 120 + #define SM8350_SLAVE_A1NOC_SNOC 109 121 + #define SM8350_SLAVE_A2NOC_CFG 110 122 + #define SM8350_SLAVE_A2NOC_SNOC 111 123 + #define SM8350_SLAVE_DDRSS_CFG 112 124 + #define SM8350_SLAVE_GEM_NOC_CNOC 113 125 + #define SM8350_SLAVE_GEM_NOC_CFG 114 126 + #define SM8350_SLAVE_SNOC_GEM_NOC_GC 115 127 + #define SM8350_SLAVE_SNOC_GEM_NOC_SF 116 128 + #define SM8350_SLAVE_LLCC 117 129 + #define SM8350_SLAVE_MNOC_HF_MEM_NOC 118 130 + #define SM8350_SLAVE_MNOC_SF_MEM_NOC 119 131 + #define SM8350_SLAVE_CNOC_MNOC_CFG 120 132 + #define SM8350_SLAVE_CDSP_MEM_NOC 121 133 + #define SM8350_SLAVE_MEM_NOC_PCIE_SNOC 122 134 + #define SM8350_SLAVE_ANOC_PCIE_GEM_NOC 123 135 + #define SM8350_SLAVE_SNOC_CFG 124 136 + #define SM8350_SLAVE_QUP_CORE_0 125 137 + #define SM8350_SLAVE_QUP_CORE_1 126 138 + #define SM8350_SLAVE_QUP_CORE_2 127 139 + #define SM8350_SLAVE_BOOT_IMEM 128 140 + #define SM8350_SLAVE_IMEM 129 141 + #define SM8350_SLAVE_PIMEM 130 142 + #define SM8350_SLAVE_SERVICE_NSP_NOC 131 143 + #define SM8350_SLAVE_SERVICE_A1NOC 132 144 + #define SM8350_SLAVE_SERVICE_A2NOC 133 145 + #define SM8350_SLAVE_SERVICE_CNOC 134 146 + #define SM8350_SLAVE_SERVICE_GEM_NOC_1 135 147 + #define SM8350_SLAVE_SERVICE_MNOC 136 148 + #define SM8350_SLAVE_SERVICES_LPASS_AML_NOC 137 149 + #define SM8350_SLAVE_SERVICE_LPASS_AG_NOC 138 150 + #define SM8350_SLAVE_SERVICE_GEM_NOC_2 139 151 + #define SM8350_SLAVE_SERVICE_SNOC 140 152 + #define SM8350_SLAVE_SERVICE_GEM_NOC 141 153 + #define SM8350_SLAVE_PCIE_0 142 154 + #define SM8350_SLAVE_PCIE_1 143 155 + #define SM8350_SLAVE_QDSS_STM 144 156 + #define SM8350_SLAVE_TCU 145 157 + #define SM8350_MASTER_LLCC_DISP 146 158 + #define SM8350_MASTER_MNOC_HF_MEM_NOC_DISP 147 159 + #define SM8350_MASTER_MNOC_SF_MEM_NOC_DISP 148 160 + #define SM8350_MASTER_MDP0_DISP 149 161 + #define SM8350_MASTER_MDP1_DISP 150 162 + #define SM8350_MASTER_ROTATOR_DISP 151 163 + #define SM8350_SLAVE_EBI1_DISP 152 164 + #define SM8350_SLAVE_LLCC_DISP 153 165 + #define SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP 154 166 + #define SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP 155 167 + 168 + #endif

+172

include/dt-bindings/interconnect/qcom,sm8350.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Qualcomm SM8350 interconnect IDs 4 + * 5 + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 + * Copyright (c) 2021, Linaro Limited 7 + */ 8 + 9 + #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H 10 + #define __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H 11 + 12 + #define MASTER_QSPI_0 0 13 + #define MASTER_QUP_1 1 14 + #define MASTER_A1NOC_CFG 2 15 + #define MASTER_SDCC_4 3 16 + #define MASTER_UFS_MEM 4 17 + #define MASTER_USB3_0 5 18 + #define MASTER_USB3_1 6 19 + #define SLAVE_A1NOC_SNOC 7 20 + #define SLAVE_SERVICE_A1NOC 8 21 + 22 + #define MASTER_QDSS_BAM 0 23 + #define MASTER_QUP_0 1 24 + #define MASTER_QUP_2 2 25 + #define MASTER_A2NOC_CFG 3 26 + #define MASTER_CRYPTO 4 27 + #define MASTER_IPA 5 28 + #define MASTER_PCIE_0 6 29 + #define MASTER_PCIE_1 7 30 + #define MASTER_QDSS_ETR 8 31 + #define MASTER_SDCC_2 9 32 + #define MASTER_UFS_CARD 10 33 + #define SLAVE_A2NOC_SNOC 11 34 + #define SLAVE_ANOC_PCIE_GEM_NOC 12 35 + #define SLAVE_SERVICE_A2NOC 13 36 + 37 + #define MASTER_GEM_NOC_CNOC 0 38 + #define MASTER_GEM_NOC_PCIE_SNOC 1 39 + #define MASTER_QDSS_DAP 2 40 + #define SLAVE_AHB2PHY_SOUTH 3 41 + #define SLAVE_AHB2PHY_NORTH 4 42 + #define SLAVE_AOSS 5 43 + #define SLAVE_APPSS 6 44 + #define SLAVE_CAMERA_CFG 7 45 + #define SLAVE_CLK_CTL 8 46 + #define SLAVE_CDSP_CFG 9 47 + #define SLAVE_RBCPR_CX_CFG 10 48 + #define SLAVE_RBCPR_MMCX_CFG 11 49 + #define SLAVE_RBCPR_MX_CFG 12 50 + #define SLAVE_CRYPTO_0_CFG 13 51 + #define SLAVE_CX_RDPM 14 52 + #define SLAVE_DCC_CFG 15 53 + #define SLAVE_DISPLAY_CFG 16 54 + #define SLAVE_GFX3D_CFG 17 55 + #define SLAVE_HWKM 18 56 + #define SLAVE_IMEM_CFG 19 57 + #define SLAVE_IPA_CFG 20 58 + #define SLAVE_IPC_ROUTER_CFG 21 59 + #define SLAVE_LPASS 22 60 + #define SLAVE_CNOC_MSS 23 61 + #define SLAVE_MX_RDPM 24 62 + #define SLAVE_PCIE_0_CFG 25 63 + #define SLAVE_PCIE_1_CFG 26 64 + #define SLAVE_PDM 27 65 + #define SLAVE_PIMEM_CFG 28 66 + #define SLAVE_PKA_WRAPPER_CFG 29 67 + #define SLAVE_PMU_WRAPPER_CFG 30 68 + #define SLAVE_QDSS_CFG 31 69 + #define SLAVE_QSPI_0 32 70 + #define SLAVE_QUP_0 33 71 + #define SLAVE_QUP_1 34 72 + #define SLAVE_QUP_2 35 73 + #define SLAVE_SDCC_2 36 74 + #define SLAVE_SDCC_4 37 75 + #define SLAVE_SECURITY 38 76 + #define SLAVE_SPSS_CFG 39 77 + #define SLAVE_TCSR 40 78 + #define SLAVE_TLMM 41 79 + #define SLAVE_UFS_CARD_CFG 42 80 + #define SLAVE_UFS_MEM_CFG 43 81 + #define SLAVE_USB3_0 44 82 + #define SLAVE_USB3_1 45 83 + #define SLAVE_VENUS_CFG 46 84 + #define SLAVE_VSENSE_CTRL_CFG 47 85 + #define SLAVE_A1NOC_CFG 48 86 + #define SLAVE_A2NOC_CFG 49 87 + #define SLAVE_DDRSS_CFG 50 88 + #define SLAVE_CNOC_MNOC_CFG 51 89 + #define SLAVE_SNOC_CFG 52 90 + #define SLAVE_BOOT_IMEM 53 91 + #define SLAVE_IMEM 54 92 + #define SLAVE_PIMEM 55 93 + #define SLAVE_SERVICE_CNOC 56 94 + #define SLAVE_PCIE_0 57 95 + #define SLAVE_PCIE_1 58 96 + #define SLAVE_QDSS_STM 59 97 + #define SLAVE_TCU 60 98 + 99 + #define MASTER_CNOC_DC_NOC 0 100 + #define SLAVE_LLCC_CFG 1 101 + #define SLAVE_GEM_NOC_CFG 2 102 + 103 + #define MASTER_GPU_TCU 0 104 + #define MASTER_SYS_TCU 1 105 + #define MASTER_APPSS_PROC 2 106 + #define MASTER_COMPUTE_NOC 3 107 + #define MASTER_GEM_NOC_CFG 4 108 + #define MASTER_GFX3D 5 109 + #define MASTER_MNOC_HF_MEM_NOC 6 110 + #define MASTER_MNOC_SF_MEM_NOC 7 111 + #define MASTER_ANOC_PCIE_GEM_NOC 8 112 + #define MASTER_SNOC_GC_MEM_NOC 9 113 + #define MASTER_SNOC_SF_MEM_NOC 10 114 + #define SLAVE_MSS_PROC_MS_MPU_CFG 11 115 + #define SLAVE_MCDMA_MS_MPU_CFG 12 116 + #define SLAVE_GEM_NOC_CNOC 13 117 + #define SLAVE_LLCC 14 118 + #define SLAVE_MEM_NOC_PCIE_SNOC 15 119 + #define SLAVE_SERVICE_GEM_NOC_1 16 120 + #define SLAVE_SERVICE_GEM_NOC_2 17 121 + #define SLAVE_SERVICE_GEM_NOC 18 122 + #define MASTER_MNOC_HF_MEM_NOC_DISP 19 123 + #define MASTER_MNOC_SF_MEM_NOC_DISP 20 124 + #define SLAVE_LLCC_DISP 21 125 + 126 + #define MASTER_CNOC_LPASS_AG_NOC 0 127 + #define SLAVE_LPASS_CORE_CFG 1 128 + #define SLAVE_LPASS_LPI_CFG 2 129 + #define SLAVE_LPASS_MPU_CFG 3 130 + #define SLAVE_LPASS_TOP_CFG 4 131 + #define SLAVE_SERVICES_LPASS_AML_NOC 5 132 + #define SLAVE_SERVICE_LPASS_AG_NOC 6 133 + 134 + #define MASTER_LLCC 0 135 + #define SLAVE_EBI1 1 136 + #define MASTER_LLCC_DISP 2 137 + #define SLAVE_EBI1_DISP 3 138 + 139 + #define MASTER_CAMNOC_HF 0 140 + #define MASTER_CAMNOC_ICP 1 141 + #define MASTER_CAMNOC_SF 2 142 + #define MASTER_CNOC_MNOC_CFG 3 143 + #define MASTER_VIDEO_P0 4 144 + #define MASTER_VIDEO_P1 5 145 + #define MASTER_VIDEO_PROC 6 146 + #define MASTER_MDP0 7 147 + #define MASTER_MDP1 8 148 + #define MASTER_ROTATOR 9 149 + #define SLAVE_MNOC_HF_MEM_NOC 10 150 + #define SLAVE_MNOC_SF_MEM_NOC 11 151 + #define SLAVE_SERVICE_MNOC 12 152 + #define MASTER_MDP0_DISP 13 153 + #define MASTER_MDP1_DISP 14 154 + #define MASTER_ROTATOR_DISP 15 155 + #define SLAVE_MNOC_HF_MEM_NOC_DISP 16 156 + #define SLAVE_MNOC_SF_MEM_NOC_DISP 17 157 + 158 + #define MASTER_CDSP_NOC_CFG 0 159 + #define MASTER_CDSP_PROC 1 160 + #define SLAVE_CDSP_MEM_NOC 2 161 + #define SLAVE_SERVICE_NSP_NOC 3 162 + 163 + #define MASTER_A1NOC_SNOC 0 164 + #define MASTER_A2NOC_SNOC 1 165 + #define MASTER_SNOC_CFG 2 166 + #define MASTER_PIMEM 3 167 + #define MASTER_GIC 4 168 + #define SLAVE_SNOC_GEM_NOC_GC 5 169 + #define SLAVE_SNOC_GEM_NOC_SF 6 170 + #define SLAVE_SERVICE_SNOC 7 171 + 172 + #endif