tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64/hwcap: Define hwcaps for 2023 DPISA features
The 2023 architecture extensions include a large number of floating point
features, most of which simply add new instructions. Add hwcaps so that
userspace can enumerate these features.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240306-arm64-2023-dpisa-v5-6-c568edc8ed7f@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
authored by
Mark Brown
and committed by
Catalin Marinas
c1932cac
4035c22e
+129
+49
Documentation/arch/arm64/elf_hwcaps.rst
+49
Documentation/arch/arm64/elf_hwcaps.rst
···
317
317
HWCAP2_LSE128
318
318
Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011.
319
319
320
+
HWCAP2_FPMR
321
+
Functionality implied by ID_AA64PFR2_EL1.FMR == 0b0001.
322
+
323
+
HWCAP2_LUT
324
+
Functionality implied by ID_AA64ISAR2_EL1.LUT == 0b0001.
325
+
326
+
HWCAP2_FAMINMAX
327
+
Functionality implied by ID_AA64ISAR3_EL1.FAMINMAX == 0b0001.
328
+
329
+
HWCAP2_F8CVT
330
+
Functionality implied by ID_AA64FPFR0_EL1.F8CVT == 0b1.
331
+
332
+
HWCAP2_F8FMA
333
+
Functionality implied by ID_AA64FPFR0_EL1.F8FMA == 0b1.
334
+
335
+
HWCAP2_F8DP4
336
+
Functionality implied by ID_AA64FPFR0_EL1.F8DP4 == 0b1.
337
+
338
+
HWCAP2_F8DP2
339
+
Functionality implied by ID_AA64FPFR0_EL1.F8DP2 == 0b1.
340
+
341
+
HWCAP2_F8E4M3
342
+
Functionality implied by ID_AA64FPFR0_EL1.F8E4M3 == 0b1.
343
+
344
+
HWCAP2_F8E5M2
345
+
Functionality implied by ID_AA64FPFR0_EL1.F8E5M2 == 0b1.
346
+
347
+
HWCAP2_SME_LUTV2
348
+
Functionality implied by ID_AA64SMFR0_EL1.LUTv2 == 0b1.
349
+
350
+
HWCAP2_SME_F8F16
351
+
Functionality implied by ID_AA64SMFR0_EL1.F8F16 == 0b1.
352
+
353
+
HWCAP2_SME_F8F32
354
+
Functionality implied by ID_AA64SMFR0_EL1.F8F32 == 0b1.
355
+
356
+
HWCAP2_SME_SF8FMA
357
+
Functionality implied by ID_AA64SMFR0_EL1.SF8FMA == 0b1.
358
+
359
+
HWCAP2_SME_SF8DP4
360
+
Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.
361
+
362
+
HWCAP2_SME_SF8DP2
363
+
Functionality implied by ID_AA64SMFR0_EL1.SF8DP2 == 0b1.
364
+
365
+
HWCAP2_SME_SF8DP4
366
+
Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.
367
+
368
+
320
369
4. Unused AT_HWCAP bits
321
370
-----------------------
322
371
+15
arch/arm64/include/asm/hwcap.h
+15
arch/arm64/include/asm/hwcap.h
···
142
142
#define KERNEL_HWCAP_SVE_B16B16 __khwcap2_feature(SVE_B16B16)
143
143
#define KERNEL_HWCAP_LRCPC3 __khwcap2_feature(LRCPC3)
144
144
#define KERNEL_HWCAP_LSE128 __khwcap2_feature(LSE128)
145
+
#define KERNEL_HWCAP_FPMR __khwcap2_feature(FPMR)
146
+
#define KERNEL_HWCAP_LUT __khwcap2_feature(LUT)
147
+
#define KERNEL_HWCAP_FAMINMAX __khwcap2_feature(FAMINMAX)
148
+
#define KERNEL_HWCAP_F8CVT __khwcap2_feature(F8CVT)
149
+
#define KERNEL_HWCAP_F8FMA __khwcap2_feature(F8FMA)
150
+
#define KERNEL_HWCAP_F8DP4 __khwcap2_feature(F8DP4)
151
+
#define KERNEL_HWCAP_F8DP2 __khwcap2_feature(F8DP2)
152
+
#define KERNEL_HWCAP_F8E4M3 __khwcap2_feature(F8E4M3)
153
+
#define KERNEL_HWCAP_F8E5M2 __khwcap2_feature(F8E5M2)
154
+
#define KERNEL_HWCAP_SME_LUTV2 __khwcap2_feature(SME_LUTV2)
155
+
#define KERNEL_HWCAP_SME_F8F16 __khwcap2_feature(SME_F8F16)
156
+
#define KERNEL_HWCAP_SME_F8F32 __khwcap2_feature(SME_F8F32)
157
+
#define KERNEL_HWCAP_SME_SF8FMA __khwcap2_feature(SME_SF8FMA)
158
+
#define KERNEL_HWCAP_SME_SF8DP4 __khwcap2_feature(SME_SF8DP4)
159
+
#define KERNEL_HWCAP_SME_SF8DP2 __khwcap2_feature(SME_SF8DP2)
145
160
146
161
/*
147
162
* This yields a mask that user programs can use to figure out what
+15
arch/arm64/include/uapi/asm/hwcap.h
+15
arch/arm64/include/uapi/asm/hwcap.h
···
107
107
#define HWCAP2_SVE_B16B16 (1UL << 45)
108
108
#define HWCAP2_LRCPC3 (1UL << 46)
109
109
#define HWCAP2_LSE128 (1UL << 47)
110
+
#define HWCAP2_FPMR (1UL << 48)
111
+
#define HWCAP2_LUT (1UL << 49)
112
+
#define HWCAP2_FAMINMAX (1UL << 50)
113
+
#define HWCAP2_F8CVT (1UL << 51)
114
+
#define HWCAP2_F8FMA (1UL << 52)
115
+
#define HWCAP2_F8DP4 (1UL << 53)
116
+
#define HWCAP2_F8DP2 (1UL << 54)
117
+
#define HWCAP2_F8E4M3 (1UL << 55)
118
+
#define HWCAP2_F8E5M2 (1UL << 56)
119
+
#define HWCAP2_SME_LUTV2 (1UL << 57)
120
+
#define HWCAP2_SME_F8F16 (1UL << 58)
121
+
#define HWCAP2_SME_F8F32 (1UL << 59)
122
+
#define HWCAP2_SME_SF8FMA (1UL << 60)
123
+
#define HWCAP2_SME_SF8DP4 (1UL << 61)
124
+
#define HWCAP2_SME_SF8DP2 (1UL << 62)
110
125
111
126
#endif /* _UAPI__ASM_HWCAP_H */
+35
arch/arm64/kernel/cpufeature.c
+35
arch/arm64/kernel/cpufeature.c
···
220
220
};
221
221
222
222
static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
223
+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0),
223
224
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
224
225
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
225
226
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0),
···
236
235
};
237
236
238
237
static const struct arm64_ftr_bits ftr_id_aa64isar3[] = {
238
+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0),
239
239
ARM64_FTR_END,
240
240
};
241
241
···
306
304
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
307
305
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0),
308
306
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
307
+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0),
308
+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
309
309
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0),
310
310
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
311
311
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0),
···
320
316
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
321
317
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0),
322
318
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
319
+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0),
320
+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
321
+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0),
322
+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
323
323
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0),
324
324
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
325
325
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0),
···
333
325
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0),
334
326
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
335
327
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0),
328
+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
329
+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0),
330
+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
331
+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0),
332
+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
333
+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0),
336
334
ARM64_FTR_END,
337
335
};
338
336
339
337
static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = {
338
+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0),
339
+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0),
340
+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0),
341
+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0),
342
+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0),
343
+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0),
340
344
ARM64_FTR_END,
341
345
};
342
346
···
2879
2859
HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2880
2860
HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2881
2861
HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT),
2862
+
HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR),
2882
2863
HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2883
2864
HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2884
2865
HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
···
2893
2872
HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16),
2894
2873
HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH),
2895
2874
HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2875
+
HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT),
2876
+
HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX),
2896
2877
HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2897
2878
#ifdef CONFIG_ARM64_SVE
2898
2879
HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),
···
2935
2912
#ifdef CONFIG_ARM64_SME
2936
2913
HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
2937
2914
HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
2915
+
HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2),
2938
2916
HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1),
2939
2917
HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2),
2940
2918
HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
···
2943
2919
HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32),
2944
2920
HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16),
2945
2921
HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16),
2922
+
HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16),
2923
+
HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32),
2946
2924
HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
2947
2925
HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
2948
2926
HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
2949
2927
HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32),
2950
2928
HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
2929
+
HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA),
2930
+
HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4),
2931
+
HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2),
2951
2932
#endif /* CONFIG_ARM64_SME */
2933
+
HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT),
2934
+
HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA),
2935
+
HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4),
2936
+
HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2),
2937
+
HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3),
2938
+
HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2),
2952
2939
{},
2953
2940
};
2954
2941
+15
arch/arm64/kernel/cpuinfo.c
+15
arch/arm64/kernel/cpuinfo.c
···
128
128
[KERNEL_HWCAP_SVE_B16B16] = "sveb16b16",
129
129
[KERNEL_HWCAP_LRCPC3] = "lrcpc3",
130
130
[KERNEL_HWCAP_LSE128] = "lse128",
131
+
[KERNEL_HWCAP_FPMR] = "fpmr",
132
+
[KERNEL_HWCAP_LUT] = "lut",
133
+
[KERNEL_HWCAP_FAMINMAX] = "faminmax",
134
+
[KERNEL_HWCAP_F8CVT] = "f8cvt",
135
+
[KERNEL_HWCAP_F8FMA] = "f8fma",
136
+
[KERNEL_HWCAP_F8DP4] = "f8dp4",
137
+
[KERNEL_HWCAP_F8DP2] = "f8dp2",
138
+
[KERNEL_HWCAP_F8E4M3] = "f8e4m3",
139
+
[KERNEL_HWCAP_F8E5M2] = "f8e5m2",
140
+
[KERNEL_HWCAP_SME_LUTV2] = "smelutv2",
141
+
[KERNEL_HWCAP_SME_F8F16] = "smef8f16",
142
+
[KERNEL_HWCAP_SME_F8F32] = "smef8f32",
143
+
[KERNEL_HWCAP_SME_SF8FMA] = "smesf8fma",
144
+
[KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4",
145
+
[KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2",
131
146
};
132
147
133
148
#ifdef CONFIG_COMPAT