tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

[media] davinci: vpss: dm365: enable ISP registers

enable the clocks required for VPFE to work in PCCR register,
and enbale ISIF out on BCR to get the correct operation from ISIF.

Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

authored by

Manjunath Hadli and committed by
Mauro Carvalho Chehab c1819fc5 47800bc4

+22 -1
+22 -1
drivers/media/platform/davinci/vpss.c
··· 51 51 /* VENCINT - vpss_int8 */ 52 52 #define DM355_VPSSBL_EVTSEL_DEFAULT 0x4 53 53 54 - #define DM365_ISP5_PCCR 0x04 54 + #define DM365_ISP5_PCCR 0x04 55 + #define DM365_ISP5_PCCR_BL_CLK_ENABLE BIT(0) 56 + #define DM365_ISP5_PCCR_ISIF_CLK_ENABLE BIT(1) 57 + #define DM365_ISP5_PCCR_H3A_CLK_ENABLE BIT(2) 58 + #define DM365_ISP5_PCCR_RSZ_CLK_ENABLE BIT(3) 59 + #define DM365_ISP5_PCCR_IPIPE_CLK_ENABLE BIT(4) 60 + #define DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE BIT(5) 61 + #define DM365_ISP5_PCCR_RSV BIT(6) 62 + 63 + #define DM365_ISP5_BCR 0x08 64 + #define DM365_ISP5_BCR_ISIF_OUT_ENABLE BIT(1) 65 + 55 66 #define DM365_ISP5_INTSEL1 0x10 56 67 #define DM365_ISP5_INTSEL2 0x14 57 68 #define DM365_ISP5_INTSEL3 0x18 ··· 437 426 oper_cfg.hw_ops.enable_clock = dm365_enable_clock; 438 427 oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source; 439 428 /* Setup vpss interrupts */ 429 + isp5_write((isp5_read(DM365_ISP5_PCCR) | 430 + DM365_ISP5_PCCR_BL_CLK_ENABLE | 431 + DM365_ISP5_PCCR_ISIF_CLK_ENABLE | 432 + DM365_ISP5_PCCR_H3A_CLK_ENABLE | 433 + DM365_ISP5_PCCR_RSZ_CLK_ENABLE | 434 + DM365_ISP5_PCCR_IPIPE_CLK_ENABLE | 435 + DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE | 436 + DM365_ISP5_PCCR_RSV), DM365_ISP5_PCCR); 437 + isp5_write((isp5_read(DM365_ISP5_BCR) | 438 + DM365_ISP5_BCR_ISIF_OUT_ENABLE), DM365_ISP5_BCR); 440 439 isp5_write(DM365_ISP5_INTSEL1_DEFAULT, DM365_ISP5_INTSEL1); 441 440 isp5_write(DM365_ISP5_INTSEL2_DEFAULT, DM365_ISP5_INTSEL2); 442 441 isp5_write(DM365_ISP5_INTSEL3_DEFAULT, DM365_ISP5_INTSEL3);