tjh.dev / kernel
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video: mmp: Remove references to CPU_PXA988

References to the Kconfig symbol CPU_PXA988 were added to the tree in
v3.9. But that Kconfig symbol has never been part of the tree. So get
rid of these references.

Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

authored by

Richard Weinberger and committed by
Tomi Valkeinen c150a280 6e860a1a

+4 -36
+1 -1
drivers/video/fbdev/mmp/Kconfig
··· 1 1 menuconfig MMP_DISP 2 2 tristate "Marvell MMP Display Subsystem support" 3 - depends on CPU_PXA910 || CPU_MMP2 || CPU_PXA988 3 + depends on CPU_PXA910 || CPU_MMP2 4 4 help 5 5 Marvell Display Subsystem support. 6 6
+3 -3
drivers/video/fbdev/mmp/hw/Kconfig
··· 2 2 3 3 config MMP_DISP_CONTROLLER 4 4 bool "mmp display controller hw support" 5 - depends on CPU_PXA910 || CPU_MMP2 || CPU_PXA988 5 + depends on CPU_PXA910 || CPU_MMP2 6 6 default n 7 7 help 8 8 Marvell MMP display hw controller support 9 - this controller is used on Marvell PXA910, 10 - MMP2, PXA988 chips 9 + this controller is used on Marvell PXA910 and 10 + MMP2 chips 11 11 12 12 config MMP_DISP_SPI 13 13 bool "mmp display controller spi port"
-32
drivers/video/fbdev/mmp/hw/mmp_ctrl.h
··· 167 167 PN2_IOPAD_CONTROL) : LCD_TOP_CTRL) 168 168 169 169 /* dither configure */ 170 - #ifdef CONFIG_CPU_PXA988 171 - #define LCD_DITHER_CTRL (0x01EC) 172 - #else 173 170 #define LCD_DITHER_CTRL (0x00A0) 174 - #endif 175 171 176 172 #define DITHER_TBL_INDEX_SEL(s) ((s) << 16) 177 173 #define DITHER_MODE2(m) ((m) << 12) ··· 182 186 #define DITHER_EN1 (1) 183 187 184 188 /* dither table data was fixed by video bpp of input and output*/ 185 - #ifdef CONFIG_CPU_PXA988 186 - #define DITHER_TB_4X4_INDEX0 (0x6e4ca280) 187 - #define DITHER_TB_4X4_INDEX1 (0x5d7f91b3) 188 - #define DITHER_TB_4X8_INDEX0 (0xb391a280) 189 - #define DITHER_TB_4X8_INDEX1 (0x7f5d6e4c) 190 - #define DITHER_TB_4X8_INDEX2 (0x80a291b3) 191 - #define DITHER_TB_4X8_INDEX3 (0x4c6e5d7f) 192 - #define LCD_DITHER_TBL_DATA (0x01F0) 193 - #else 194 189 #define DITHER_TB_4X4_INDEX0 (0x3b19f7d5) 195 190 #define DITHER_TB_4X4_INDEX1 (0x082ac4e6) 196 191 #define DITHER_TB_4X8_INDEX0 (0xf7d508e6) ··· 189 202 #define DITHER_TB_4X8_INDEX2 (0xc4e6d5f7) 190 203 #define DITHER_TB_4X8_INDEX3 (0x082a193b) 191 204 #define LCD_DITHER_TBL_DATA (0x00A4) 192 - #endif 193 205 194 206 /* Video Frame 0&1 start address registers */ 195 207 #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0 ··· 919 933 #define LCD_PN2_SQULN2_CTRL (0x02F0) 920 934 #define ALL_LAYER_ALPHA_SEL (0x02F4) 921 935 922 - /* pxa988 has different MASTER_CTRL from MMP3/MMP2 */ 923 - #ifdef CONFIG_CPU_PXA988 924 - #define TIMING_MASTER_CONTROL (0x01F4) 925 - #define MASTER_ENH(id) (1 << ((id) + 5)) 926 - #define MASTER_ENV(id) (1 << ((id) + 6)) 927 - #else 928 936 #define TIMING_MASTER_CONTROL (0x02F8) 929 937 #define MASTER_ENH(id) (1 << (id)) 930 938 #define MASTER_ENV(id) (1 << ((id) + 4)) 931 - #endif 932 939 933 940 #define DSI_START_SEL_SHIFT(id) (((id) << 1) + 8) 934 941 #define timing_master_config(path, dsi_id, lcd_id) \ ··· 1291 1312 #define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_MASK (0xff) 1292 1313 #define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_SHIFT 0 1293 1314 1294 - /* 1295 - * DSI timings 1296 - * PXA988 has diffrent ESC CLK with MMP2/MMP3 1297 - * it will be used in dsi_set_dphy() in pxa688_phy.c 1298 - * as low power mode clock. 1299 - */ 1300 - #ifdef CONFIG_CPU_PXA988 1301 - #define DSI_ESC_CLK 52 /* Unit: Mhz */ 1302 - #define DSI_ESC_CLK_T 19 /* Unit: ns */ 1303 - #else 1304 1315 #define DSI_ESC_CLK 66 /* Unit: Mhz */ 1305 1316 #define DSI_ESC_CLK_T 15 /* Unit: ns */ 1306 - #endif 1307 1317 1308 1318 /* LVDS */ 1309 1319 /* LVDS_PHY_CTRL */