tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Disintegrate asm/system.h for IA64
Disintegrate asm/system.h for IA64.
Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Tony Luck <tony.luck@intel.com>
cc: linux-ia64@vger.kernel.org
+233
-249
+1
-1
arch/ia64/dig/setup.c
+1
-1
arch/ia64/dig/setup.c
-1
arch/ia64/hp/common/sba_iommu.c
-1
arch/ia64/hp/common/sba_iommu.c
-1
arch/ia64/hp/sim/boot/bootloader.c
-1
arch/ia64/hp/sim/boot/bootloader.c
+1
arch/ia64/hp/sim/boot/fw-emu.c
+1
arch/ia64/hp/sim/boot/fw-emu.c
-1
arch/ia64/hp/sim/simeth.c
-1
arch/ia64/hp/sim/simeth.c
-1
arch/ia64/include/asm/acpi.h
-1
arch/ia64/include/asm/acpi.h
-1
arch/ia64/include/asm/atomic.h
-1
arch/ia64/include/asm/atomic.h
+2
arch/ia64/include/asm/auxvec.h
+2
arch/ia64/include/asm/auxvec.h
+68
arch/ia64/include/asm/barrier.h
+68
arch/ia64/include/asm/barrier.h
···
1
+
/*
2
+
* Memory barrier definitions. This is based on information published
3
+
* in the Processor Abstraction Layer and the System Abstraction Layer
4
+
* manual.
5
+
*
6
+
* Copyright (C) 1998-2003 Hewlett-Packard Co
7
+
* David Mosberger-Tang <davidm@hpl.hp.com>
8
+
* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
9
+
* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
10
+
*/
11
+
#ifndef _ASM_IA64_BARRIER_H
12
+
#define _ASM_IA64_BARRIER_H
13
+
14
+
#include <linux/compiler.h>
15
+
16
+
/*
17
+
* Macros to force memory ordering. In these descriptions, "previous"
18
+
* and "subsequent" refer to program order; "visible" means that all
19
+
* architecturally visible effects of a memory access have occurred
20
+
* (at a minimum, this means the memory has been read or written).
21
+
*
22
+
* wmb(): Guarantees that all preceding stores to memory-
23
+
* like regions are visible before any subsequent
24
+
* stores and that all following stores will be
25
+
* visible only after all previous stores.
26
+
* rmb(): Like wmb(), but for reads.
27
+
* mb(): wmb()/rmb() combo, i.e., all previous memory
28
+
* accesses are visible before all subsequent
29
+
* accesses and vice versa. This is also known as
30
+
* a "fence."
31
+
*
32
+
* Note: "mb()" and its variants cannot be used as a fence to order
33
+
* accesses to memory mapped I/O registers. For that, mf.a needs to
34
+
* be used. However, we don't want to always use mf.a because (a)
35
+
* it's (presumably) much slower than mf and (b) mf.a is supported for
36
+
* sequential memory pages only.
37
+
*/
38
+
#define mb() ia64_mf()
39
+
#define rmb() mb()
40
+
#define wmb() mb()
41
+
#define read_barrier_depends() do { } while(0)
42
+
43
+
#ifdef CONFIG_SMP
44
+
# define smp_mb() mb()
45
+
# define smp_rmb() rmb()
46
+
# define smp_wmb() wmb()
47
+
# define smp_read_barrier_depends() read_barrier_depends()
48
+
#else
49
+
# define smp_mb() barrier()
50
+
# define smp_rmb() barrier()
51
+
# define smp_wmb() barrier()
52
+
# define smp_read_barrier_depends() do { } while(0)
53
+
#endif
54
+
55
+
/*
56
+
* XXX check on this ---I suspect what Linus really wants here is
57
+
* acquire vs release semantics but we can't discuss this stuff with
58
+
* Linus just yet. Grrr...
59
+
*/
60
+
#define set_mb(var, value) do { (var) = (value); mb(); } while (0)
61
+
62
+
/*
63
+
* The group barrier in front of the rsm & ssm are necessary to ensure
64
+
* that none of the previous instructions in the same group are
65
+
* affected by the rsm/ssm.
66
+
*/
67
+
68
+
#endif /* _ASM_IA64_BARRIER_H */
+14
arch/ia64/include/asm/exec.h
+14
arch/ia64/include/asm/exec.h
···
1
+
/*
2
+
* Process execution defines.
3
+
*
4
+
* Copyright (C) 1998-2003 Hewlett-Packard Co
5
+
* David Mosberger-Tang <davidm@hpl.hp.com>
6
+
* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
7
+
* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
8
+
*/
9
+
#ifndef _ASM_IA64_EXEC_H
10
+
#define _ASM_IA64_EXEC_H
11
+
12
+
#define arch_align_stack(x) (x)
13
+
14
+
#endif /* _ASM_IA64_EXEC_H */
-1
arch/ia64/include/asm/futex.h
-1
arch/ia64/include/asm/futex.h
-1
arch/ia64/include/asm/io.h
-1
arch/ia64/include/asm/io.h
+2
arch/ia64/include/asm/irqflags.h
+2
arch/ia64/include/asm/irqflags.h
+1
arch/ia64/include/asm/kexec.h
+1
arch/ia64/include/asm/kexec.h
+2
arch/ia64/include/asm/mca_asm.h
+2
arch/ia64/include/asm/mca_asm.h
+10
arch/ia64/include/asm/page.h
+10
arch/ia64/include/asm/page.h
···
221
221
(((current->personality & READ_IMPLIES_EXEC) != 0) \
222
222
? VM_EXEC : 0))
223
223
224
+
#define GATE_ADDR RGN_BASE(RGN_GATE)
225
+
226
+
/*
227
+
* 0xa000000000000000+2*PERCPU_PAGE_SIZE
228
+
* - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
229
+
*/
230
+
#define KERNEL_START (GATE_ADDR+__IA64_UL_CONST(0x100000000))
231
+
#define PERCPU_ADDR (-PERCPU_PAGE_SIZE)
232
+
#define LOAD_OFFSET (KERNEL_START - KERNEL_TR_PAGE_SIZE)
233
+
224
234
#endif /* _ASM_IA64_PAGE_H */
+8
arch/ia64/include/asm/pci.h
+8
arch/ia64/include/asm/pci.h
···
11
11
#include <asm/scatterlist.h>
12
12
#include <asm/hw_irq.h>
13
13
14
+
struct pci_vector_struct {
15
+
__u16 segment; /* PCI Segment number */
16
+
__u16 bus; /* PCI Bus number */
17
+
__u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
18
+
__u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
19
+
__u32 irq; /* IRQ assigned */
20
+
};
21
+
14
22
/*
15
23
* Can be used to override the logic in pci_scan_bus for skipping already-configured bus
16
24
* numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
-1
arch/ia64/include/asm/pgtable.h
-1
arch/ia64/include/asm/pgtable.h
+8
arch/ia64/include/asm/processor.h
+8
arch/ia64/include/asm/processor.h
···
19
19
#include <asm/ptrace.h>
20
20
#include <asm/ustack.h>
21
21
22
+
#define __ARCH_WANT_UNLOCKED_CTXSW
23
+
#define ARCH_HAS_PREFETCH_SWITCH_STACK
24
+
22
25
#define IA64_NUM_PHYS_STACK_REG 96
23
26
#define IA64_NUM_DBG_REGS 8
24
27
···
722
719
723
720
enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT,
724
721
IDLE_NOMWAIT, IDLE_POLL};
722
+
723
+
void cpu_idle_wait(void);
724
+
void default_idle(void);
725
+
726
+
#define ia64_platform_is(x) (strcmp(x, platform_name) == 0)
725
727
726
728
#endif /* !__ASSEMBLY__ */
727
729
-1
arch/ia64/include/asm/sal.h
-1
arch/ia64/include/asm/sal.h
+18
arch/ia64/include/asm/setup.h
+18
arch/ia64/include/asm/setup.h
···
3
3
4
4
#define COMMAND_LINE_SIZE 2048
5
5
6
+
extern struct ia64_boot_param {
7
+
__u64 command_line; /* physical address of command line arguments */
8
+
__u64 efi_systab; /* physical address of EFI system table */
9
+
__u64 efi_memmap; /* physical address of EFI memory map */
10
+
__u64 efi_memmap_size; /* size of EFI memory map */
11
+
__u64 efi_memdesc_size; /* size of an EFI memory map descriptor */
12
+
__u32 efi_memdesc_version; /* memory descriptor version */
13
+
struct {
14
+
__u16 num_cols; /* number of columns on console output device */
15
+
__u16 num_rows; /* number of rows on console output device */
16
+
__u16 orig_x; /* cursor's x position */
17
+
__u16 orig_y; /* cursor's y position */
18
+
} console_info;
19
+
__u64 fpswa; /* physical address of the fpswa interface */
20
+
__u64 initrd_start;
21
+
__u64 initrd_size;
22
+
} *ia64_boot_param;
23
+
6
24
#endif
-1
arch/ia64/include/asm/sn/pda.h
-1
arch/ia64/include/asm/sn/pda.h
-1
arch/ia64/include/asm/spinlock.h
-1
arch/ia64/include/asm/spinlock.h
+87
arch/ia64/include/asm/switch_to.h
+87
arch/ia64/include/asm/switch_to.h
···
1
+
/*
2
+
* Low-level task switching. This is based on information published in
3
+
* the Processor Abstraction Layer and the System Abstraction Layer
4
+
* manual.
5
+
*
6
+
* Copyright (C) 1998-2003 Hewlett-Packard Co
7
+
* David Mosberger-Tang <davidm@hpl.hp.com>
8
+
* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
9
+
* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
10
+
*/
11
+
#ifndef _ASM_IA64_SWITCH_TO_H
12
+
#define _ASM_IA64_SWITCH_TO_H
13
+
14
+
#include <linux/percpu.h>
15
+
16
+
struct task_struct;
17
+
18
+
/*
19
+
* Context switch from one thread to another. If the two threads have
20
+
* different address spaces, schedule() has already taken care of
21
+
* switching to the new address space by calling switch_mm().
22
+
*
23
+
* Disabling access to the fph partition and the debug-register
24
+
* context switch MUST be done before calling ia64_switch_to() since a
25
+
* newly created thread returns directly to
26
+
* ia64_ret_from_syscall_clear_r8.
27
+
*/
28
+
extern struct task_struct *ia64_switch_to (void *next_task);
29
+
30
+
extern void ia64_save_extra (struct task_struct *task);
31
+
extern void ia64_load_extra (struct task_struct *task);
32
+
33
+
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
34
+
extern void ia64_account_on_switch (struct task_struct *prev, struct task_struct *next);
35
+
# define IA64_ACCOUNT_ON_SWITCH(p,n) ia64_account_on_switch(p,n)
36
+
#else
37
+
# define IA64_ACCOUNT_ON_SWITCH(p,n)
38
+
#endif
39
+
40
+
#ifdef CONFIG_PERFMON
41
+
DECLARE_PER_CPU(unsigned long, pfm_syst_info);
42
+
# define PERFMON_IS_SYSWIDE() (__get_cpu_var(pfm_syst_info) & 0x1)
43
+
#else
44
+
# define PERFMON_IS_SYSWIDE() (0)
45
+
#endif
46
+
47
+
#define IA64_HAS_EXTRA_STATE(t) \
48
+
((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID) \
49
+
|| PERFMON_IS_SYSWIDE())
50
+
51
+
#define __switch_to(prev,next,last) do { \
52
+
IA64_ACCOUNT_ON_SWITCH(prev, next); \
53
+
if (IA64_HAS_EXTRA_STATE(prev)) \
54
+
ia64_save_extra(prev); \
55
+
if (IA64_HAS_EXTRA_STATE(next)) \
56
+
ia64_load_extra(next); \
57
+
ia64_psr(task_pt_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
58
+
(last) = ia64_switch_to((next)); \
59
+
} while (0)
60
+
61
+
#ifdef CONFIG_SMP
62
+
/*
63
+
* In the SMP case, we save the fph state when context-switching away from a thread that
64
+
* modified fph. This way, when the thread gets scheduled on another CPU, the CPU can
65
+
* pick up the state from task->thread.fph, avoiding the complication of having to fetch
66
+
* the latest fph state from another CPU. In other words: eager save, lazy restore.
67
+
*/
68
+
# define switch_to(prev,next,last) do { \
69
+
if (ia64_psr(task_pt_regs(prev))->mfh && ia64_is_local_fpu_owner(prev)) { \
70
+
ia64_psr(task_pt_regs(prev))->mfh = 0; \
71
+
(prev)->thread.flags |= IA64_THREAD_FPH_VALID; \
72
+
__ia64_save_fpu((prev)->thread.fph); \
73
+
} \
74
+
__switch_to(prev, next, last); \
75
+
/* "next" in old context is "current" in new context */ \
76
+
if (unlikely((current->thread.flags & IA64_THREAD_MIGRATION) && \
77
+
(task_cpu(current) != \
78
+
task_thread_info(current)->last_cpu))) { \
79
+
platform_migrate(current); \
80
+
task_thread_info(current)->last_cpu = task_cpu(current); \
81
+
} \
82
+
} while (0)
83
+
#else
84
+
# define switch_to(prev,next,last) __switch_to(prev, next, last)
85
+
#endif
86
+
87
+
#endif /* _ASM_IA64_SWITCH_TO_H */
+4
-203
arch/ia64/include/asm/system.h
+4
-203
arch/ia64/include/asm/system.h
···
1
-
#ifndef _ASM_IA64_SYSTEM_H
2
-
#define _ASM_IA64_SYSTEM_H
3
-
4
-
/*
5
-
* System defines. Note that this is included both from .c and .S
6
-
* files, so it does only defines, not any C code. This is based
7
-
* on information published in the Processor Abstraction Layer
8
-
* and the System Abstraction Layer manual.
9
-
*
10
-
* Copyright (C) 1998-2003 Hewlett-Packard Co
11
-
* David Mosberger-Tang <davidm@hpl.hp.com>
12
-
* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
13
-
* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
14
-
*/
15
-
16
-
#include <asm/kregs.h>
17
-
#include <asm/page.h>
18
-
#include <asm/pal.h>
19
-
#include <asm/percpu.h>
20
-
21
-
#define GATE_ADDR RGN_BASE(RGN_GATE)
22
-
23
-
/*
24
-
* 0xa000000000000000+2*PERCPU_PAGE_SIZE
25
-
* - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
26
-
*/
27
-
#define KERNEL_START (GATE_ADDR+__IA64_UL_CONST(0x100000000))
28
-
#define PERCPU_ADDR (-PERCPU_PAGE_SIZE)
29
-
#define LOAD_OFFSET (KERNEL_START - KERNEL_TR_PAGE_SIZE)
30
-
31
-
#ifndef __ASSEMBLY__
32
-
33
-
#include <linux/kernel.h>
34
-
#include <linux/types.h>
35
-
36
-
#define AT_VECTOR_SIZE_ARCH 2 /* entries in ARCH_DLINFO */
37
-
38
-
struct pci_vector_struct {
39
-
__u16 segment; /* PCI Segment number */
40
-
__u16 bus; /* PCI Bus number */
41
-
__u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
42
-
__u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
43
-
__u32 irq; /* IRQ assigned */
44
-
};
45
-
46
-
extern struct ia64_boot_param {
47
-
__u64 command_line; /* physical address of command line arguments */
48
-
__u64 efi_systab; /* physical address of EFI system table */
49
-
__u64 efi_memmap; /* physical address of EFI memory map */
50
-
__u64 efi_memmap_size; /* size of EFI memory map */
51
-
__u64 efi_memdesc_size; /* size of an EFI memory map descriptor */
52
-
__u32 efi_memdesc_version; /* memory descriptor version */
53
-
struct {
54
-
__u16 num_cols; /* number of columns on console output device */
55
-
__u16 num_rows; /* number of rows on console output device */
56
-
__u16 orig_x; /* cursor's x position */
57
-
__u16 orig_y; /* cursor's y position */
58
-
} console_info;
59
-
__u64 fpswa; /* physical address of the fpswa interface */
60
-
__u64 initrd_start;
61
-
__u64 initrd_size;
62
-
} *ia64_boot_param;
63
-
64
-
/*
65
-
* Macros to force memory ordering. In these descriptions, "previous"
66
-
* and "subsequent" refer to program order; "visible" means that all
67
-
* architecturally visible effects of a memory access have occurred
68
-
* (at a minimum, this means the memory has been read or written).
69
-
*
70
-
* wmb(): Guarantees that all preceding stores to memory-
71
-
* like regions are visible before any subsequent
72
-
* stores and that all following stores will be
73
-
* visible only after all previous stores.
74
-
* rmb(): Like wmb(), but for reads.
75
-
* mb(): wmb()/rmb() combo, i.e., all previous memory
76
-
* accesses are visible before all subsequent
77
-
* accesses and vice versa. This is also known as
78
-
* a "fence."
79
-
*
80
-
* Note: "mb()" and its variants cannot be used as a fence to order
81
-
* accesses to memory mapped I/O registers. For that, mf.a needs to
82
-
* be used. However, we don't want to always use mf.a because (a)
83
-
* it's (presumably) much slower than mf and (b) mf.a is supported for
84
-
* sequential memory pages only.
85
-
*/
86
-
#define mb() ia64_mf()
87
-
#define rmb() mb()
88
-
#define wmb() mb()
89
-
#define read_barrier_depends() do { } while(0)
90
-
91
-
#ifdef CONFIG_SMP
92
-
# define smp_mb() mb()
93
-
# define smp_rmb() rmb()
94
-
# define smp_wmb() wmb()
95
-
# define smp_read_barrier_depends() read_barrier_depends()
96
-
#else
97
-
# define smp_mb() barrier()
98
-
# define smp_rmb() barrier()
99
-
# define smp_wmb() barrier()
100
-
# define smp_read_barrier_depends() do { } while(0)
101
-
#endif
102
-
103
-
/*
104
-
* XXX check on this ---I suspect what Linus really wants here is
105
-
* acquire vs release semantics but we can't discuss this stuff with
106
-
* Linus just yet. Grrr...
107
-
*/
108
-
#define set_mb(var, value) do { (var) = (value); mb(); } while (0)
109
-
110
-
/*
111
-
* The group barrier in front of the rsm & ssm are necessary to ensure
112
-
* that none of the previous instructions in the same group are
113
-
* affected by the rsm/ssm.
114
-
*/
115
-
116
-
#ifdef __KERNEL__
117
-
118
-
/*
119
-
* Context switch from one thread to another. If the two threads have
120
-
* different address spaces, schedule() has already taken care of
121
-
* switching to the new address space by calling switch_mm().
122
-
*
123
-
* Disabling access to the fph partition and the debug-register
124
-
* context switch MUST be done before calling ia64_switch_to() since a
125
-
* newly created thread returns directly to
126
-
* ia64_ret_from_syscall_clear_r8.
127
-
*/
128
-
extern struct task_struct *ia64_switch_to (void *next_task);
129
-
130
-
struct task_struct;
131
-
132
-
extern void ia64_save_extra (struct task_struct *task);
133
-
extern void ia64_load_extra (struct task_struct *task);
134
-
135
-
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
136
-
extern void ia64_account_on_switch (struct task_struct *prev, struct task_struct *next);
137
-
# define IA64_ACCOUNT_ON_SWITCH(p,n) ia64_account_on_switch(p,n)
138
-
#else
139
-
# define IA64_ACCOUNT_ON_SWITCH(p,n)
140
-
#endif
141
-
142
-
#ifdef CONFIG_PERFMON
143
-
DECLARE_PER_CPU(unsigned long, pfm_syst_info);
144
-
# define PERFMON_IS_SYSWIDE() (__get_cpu_var(pfm_syst_info) & 0x1)
145
-
#else
146
-
# define PERFMON_IS_SYSWIDE() (0)
147
-
#endif
148
-
149
-
#define IA64_HAS_EXTRA_STATE(t) \
150
-
((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID) \
151
-
|| PERFMON_IS_SYSWIDE())
152
-
153
-
#define __switch_to(prev,next,last) do { \
154
-
IA64_ACCOUNT_ON_SWITCH(prev, next); \
155
-
if (IA64_HAS_EXTRA_STATE(prev)) \
156
-
ia64_save_extra(prev); \
157
-
if (IA64_HAS_EXTRA_STATE(next)) \
158
-
ia64_load_extra(next); \
159
-
ia64_psr(task_pt_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
160
-
(last) = ia64_switch_to((next)); \
161
-
} while (0)
162
-
163
-
#ifdef CONFIG_SMP
164
-
/*
165
-
* In the SMP case, we save the fph state when context-switching away from a thread that
166
-
* modified fph. This way, when the thread gets scheduled on another CPU, the CPU can
167
-
* pick up the state from task->thread.fph, avoiding the complication of having to fetch
168
-
* the latest fph state from another CPU. In other words: eager save, lazy restore.
169
-
*/
170
-
# define switch_to(prev,next,last) do { \
171
-
if (ia64_psr(task_pt_regs(prev))->mfh && ia64_is_local_fpu_owner(prev)) { \
172
-
ia64_psr(task_pt_regs(prev))->mfh = 0; \
173
-
(prev)->thread.flags |= IA64_THREAD_FPH_VALID; \
174
-
__ia64_save_fpu((prev)->thread.fph); \
175
-
} \
176
-
__switch_to(prev, next, last); \
177
-
/* "next" in old context is "current" in new context */ \
178
-
if (unlikely((current->thread.flags & IA64_THREAD_MIGRATION) && \
179
-
(task_cpu(current) != \
180
-
task_thread_info(current)->last_cpu))) { \
181
-
platform_migrate(current); \
182
-
task_thread_info(current)->last_cpu = task_cpu(current); \
183
-
} \
184
-
} while (0)
185
-
#else
186
-
# define switch_to(prev,next,last) __switch_to(prev, next, last)
187
-
#endif
188
-
189
-
#define __ARCH_WANT_UNLOCKED_CTXSW
190
-
#define ARCH_HAS_PREFETCH_SWITCH_STACK
191
-
#define ia64_platform_is(x) (strcmp(x, platform_name) == 0)
192
-
193
-
void cpu_idle_wait(void);
194
-
195
-
#define arch_align_stack(x) (x)
196
-
197
-
void default_idle(void);
198
-
199
-
#endif /* __KERNEL__ */
200
-
201
-
#endif /* __ASSEMBLY__ */
202
-
203
-
#endif /* _ASM_IA64_SYSTEM_H */
1
+
/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
2
+
#include <asm/barrier.h>
3
+
#include <asm/exec.h>
4
+
#include <asm/switch_to.h>
-1
arch/ia64/include/asm/uv/uv.h
-1
arch/ia64/include/asm/uv/uv.h
-1
arch/ia64/kernel/acpi.c
-1
arch/ia64/kernel/acpi.c
+1
arch/ia64/kernel/efi.c
+1
arch/ia64/kernel/efi.c
-1
arch/ia64/kernel/fsys.S
-1
arch/ia64/kernel/fsys.S
+2
-1
arch/ia64/kernel/gate.S
+2
-1
arch/ia64/kernel/gate.S
+1
-2
arch/ia64/kernel/gate.lds.S
+1
-2
arch/ia64/kernel/gate.lds.S
-1
arch/ia64/kernel/head.S
-1
arch/ia64/kernel/head.S
-1
arch/ia64/kernel/iosapic.c
-1
arch/ia64/kernel/iosapic.c
-1
arch/ia64/kernel/irq_ia64.c
-1
arch/ia64/kernel/irq_ia64.c
-1
arch/ia64/kernel/ivt.S
-1
arch/ia64/kernel/ivt.S
-1
arch/ia64/kernel/machvec.c
-1
arch/ia64/kernel/machvec.c
-1
arch/ia64/kernel/mca.c
-1
arch/ia64/kernel/mca.c
-1
arch/ia64/kernel/mca_drv.c
-1
arch/ia64/kernel/mca_drv.c
-1
arch/ia64/kernel/patch.c
-1
arch/ia64/kernel/patch.c
-1
arch/ia64/kernel/pci-dma.c
-1
arch/ia64/kernel/pci-dma.c
-1
arch/ia64/kernel/perfmon.c
-1
arch/ia64/kernel/perfmon.c
-1
arch/ia64/kernel/ptrace.c
-1
arch/ia64/kernel/ptrace.c
-1
arch/ia64/kernel/setup.c
-1
arch/ia64/kernel/setup.c
-1
arch/ia64/kernel/smp.c
-1
arch/ia64/kernel/smp.c
-1
arch/ia64/kernel/smpboot.c
-1
arch/ia64/kernel/smpboot.c
-1
arch/ia64/kernel/time.c
-1
arch/ia64/kernel/time.c
+1
arch/ia64/kernel/traps.c
+1
arch/ia64/kernel/traps.c
-1
arch/ia64/kernel/uncached.c
-1
arch/ia64/kernel/uncached.c
-1
arch/ia64/kernel/unwind.c
-1
arch/ia64/kernel/unwind.c
-1
arch/ia64/kernel/vmlinux.lds.S
-1
arch/ia64/kernel/vmlinux.lds.S
-1
arch/ia64/mm/fault.c
-1
arch/ia64/mm/fault.c
-1
arch/ia64/mm/init.c
-1
arch/ia64/mm/init.c
-1
arch/ia64/oprofile/backtrace.c
-1
arch/ia64/oprofile/backtrace.c
-1
arch/ia64/pci/pci.c
-1
arch/ia64/pci/pci.c
+1
-1
arch/ia64/sn/kernel/setup.c
+1
-1
arch/ia64/sn/kernel/setup.c
-1
arch/ia64/sn/kernel/sn2/prominfo_proc.c
-1
arch/ia64/sn/kernel/sn2/prominfo_proc.c
-1
arch/ia64/sn/kernel/sn2/sn2_smp.c
-1
arch/ia64/sn/kernel/sn2/sn2_smp.c
-1
arch/ia64/sn/kernel/sn2/timer.c
-1
arch/ia64/sn/kernel/sn2/timer.c
-1
arch/ia64/sn/kernel/tiocx.c
-1
arch/ia64/sn/kernel/tiocx.c
-1
arch/ia64/xen/xensetup.S
-1
arch/ia64/xen/xensetup.S