Merge branch 'drm-next-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-next

+2 -10

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

··· 826 826 { 827 827 struct drm_minor *minor = adev->ddev->primary; 828 828 struct dentry *ent, *root = minor->debugfs_root; 829 - unsigned i, j; 829 + unsigned int i; 830 830 831 831 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { 832 832 ent = debugfs_create_file(debugfs_regs_names[i], 833 833 S_IFREG | S_IRUGO, root, 834 834 adev, debugfs_regs[i]); 835 - if (IS_ERR(ent)) { 836 - for (j = 0; j < i; j++) { 837 - debugfs_remove(adev->debugfs_regs[i]); 838 - adev->debugfs_regs[i] = NULL; 839 - } 840 - return PTR_ERR(ent); 841 - } 842 - 843 - if (!i) 835 + if (!i && !IS_ERR_OR_NULL(ent)) 844 836 i_size_write(ent->d_inode, adev->rmmio_size); 845 837 adev->debugfs_regs[i] = ent; 846 838 }

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c

··· 574 574 /* skip over VMID 0, since it is the system VM */ 575 575 for (j = 1; j < id_mgr->num_ids; ++j) { 576 576 amdgpu_vmid_reset(adev, i, j); 577 - amdgpu_sync_create(&id_mgr->ids[i].active); 577 + amdgpu_sync_create(&id_mgr->ids[j].active); 578 578 list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru); 579 579 } 580 580 }

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c

··· 1 - // SPDX-License-Identifier: GPL-2.0 1 + // SPDX-License-Identifier: MIT 2 2 /* Copyright Red Hat Inc 2010. 3 3 * 4 4 * Permission is hereby granted, free of charge, to any person obtaining a

+15 -1

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

··· 97 97 static const struct soc15_reg_golden golden_settings_gc_9_0[] = 98 98 { 99 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 100 + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), 100 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 101 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 102 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), ··· 4905 4904 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 4906 4905 { 4907 4906 /* init asci gds info */ 4908 - adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); 4907 + switch (adev->asic_type) { 4908 + case CHIP_VEGA10: 4909 + case CHIP_VEGA12: 4910 + case CHIP_VEGA20: 4911 + adev->gds.mem.total_size = 0x10000; 4912 + break; 4913 + case CHIP_RAVEN: 4914 + adev->gds.mem.total_size = 0x1000; 4915 + break; 4916 + default: 4917 + adev->gds.mem.total_size = 0x10000; 4918 + break; 4919 + } 4920 + 4909 4921 adev->gds.gws.total_size = 64; 4910 4922 adev->gds.oa.total_size = 16; 4911 4923

+2

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

··· 148 148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 149 149 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 150 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 151 + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xFE000000, 0x00000000), 151 152 }; 152 153 153 154 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { ··· 178 177 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 179 178 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 180 179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 180 + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xFE000000, 0x00000000), 181 181 }; 182 182 183 183 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =

+171 -121

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

··· 37 37 38 38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 39 39 40 + #define mmUVD_RBC_XX_IB_REG_CHECK 0x05ab 41 + #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1 42 + #define mmUVD_REG_XX_MASK 0x05ac 43 + #define mmUVD_REG_XX_MASK_BASE_IDX 1 44 + 40 45 static int vcn_v1_0_stop(struct amdgpu_device *adev); 41 46 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 42 47 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); ··· 325 320 adev->gfx.config.gb_addr_config); 326 321 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 327 322 adev->gfx.config.gb_addr_config); 323 + WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 324 + adev->gfx.config.gb_addr_config); 325 + WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 326 + adev->gfx.config.gb_addr_config); 327 + WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 328 + adev->gfx.config.gb_addr_config); 329 + WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 330 + adev->gfx.config.gb_addr_config); 331 + WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 332 + adev->gfx.config.gb_addr_config); 333 + WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 334 + adev->gfx.config.gb_addr_config); 335 + WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 336 + adev->gfx.config.gb_addr_config); 337 + WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 338 + adev->gfx.config.gb_addr_config); 339 + WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 340 + adev->gfx.config.gb_addr_config); 328 341 } 329 342 330 343 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) ··· 394 371 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 395 372 0xFFFFFFFF, 0); 396 373 374 + /* VCN global tiling registers */ 397 375 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 398 376 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 399 377 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 400 378 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 401 379 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 402 380 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 403 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 404 - adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 405 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 406 - adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 381 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 382 + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 383 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 384 + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 385 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 386 + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 387 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 388 + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 389 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 390 + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 391 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 392 + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 393 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 394 + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 407 395 } 408 396 409 397 /** ··· 777 743 lmi_swap_cntl = 0; 778 744 779 745 vcn_1_0_disable_static_power_gating(adev); 746 + 747 + tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 748 + WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 749 + 780 750 /* disable clock gating */ 781 751 vcn_v1_0_disable_clock_gating(adev); 782 - 783 - vcn_v1_0_mc_resume_spg_mode(adev); 784 752 785 753 /* disable interupt */ 786 754 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 787 755 ~UVD_MASTINT_EN__VCPU_EN_MASK); 788 756 789 - /* stall UMC and register bus before resetting VCPU */ 790 - WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 791 - UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 792 - ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 793 - mdelay(1); 794 - 795 - /* put LMI, VCPU, RBC etc... into reset */ 796 - WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 797 - UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 798 - UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 799 - UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 800 - UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 801 - UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 802 - UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 803 - UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 804 - UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 805 - mdelay(5); 806 - 807 757 /* initialize VCN memory controller */ 808 - WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, 809 - (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 810 - UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 811 - UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 812 - UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 813 - UVD_LMI_CTRL__REQ_MODE_MASK | 814 - 0x00100000L); 758 + tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 759 + WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 760 + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 761 + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 762 + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 763 + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 815 764 816 765 #ifdef __BIG_ENDIAN 817 766 /* swap (8 in 32) RB and IB */ ··· 802 785 #endif 803 786 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 804 787 805 - WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040); 806 - WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0); 807 - WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040); 808 - WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0); 809 - WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0); 810 - WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88); 788 + tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 789 + tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 790 + tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 791 + WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); 811 792 812 - /* take all subblocks out of reset, except VCPU */ 813 - WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 814 - UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 815 - mdelay(5); 793 + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 794 + ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 795 + (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 796 + (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 797 + (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 798 + 799 + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 800 + ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 801 + (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 802 + (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 803 + (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 804 + 805 + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 806 + ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 807 + (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 808 + (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 809 + 810 + vcn_v1_0_mc_resume_spg_mode(adev); 811 + 812 + WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK, 0x10); 813 + WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 814 + RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3); 816 815 817 816 /* enable VCPU clock */ 818 - WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 819 - UVD_VCPU_CNTL__CLK_EN_MASK); 817 + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 818 + 819 + /* boot up the VCPU */ 820 + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 821 + ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 820 822 821 823 /* enable UMC */ 822 824 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 823 825 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 824 826 825 - /* boot up the VCPU */ 826 - WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0); 827 - mdelay(10); 827 + tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); 828 + tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 829 + tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 830 + WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); 828 831 829 832 for (i = 0; i < 10; ++i) { 830 833 uint32_t status; ··· 876 839 } 877 840 /* enable master interrupt */ 878 841 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 879 - (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 880 - ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 842 + UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK); 881 843 882 844 /* enable system interrupt for JRBC, TODO: move to set interrupt*/ 883 845 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 884 846 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 885 847 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); 886 848 887 - /* clear the bit 4 of VCN_STATUS */ 888 - WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, 889 - ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 849 + /* clear the busy bit of UVD_STATUS */ 850 + tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; 851 + WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 890 852 891 853 /* force RBC into idle state */ 892 854 rb_bufsz = order_base_2(ring->ring_size); 893 855 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 894 856 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 895 857 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 896 - tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 897 858 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 898 859 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 899 860 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); ··· 958 923 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 959 924 { 960 925 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 961 - uint32_t rb_bufsz, tmp, reg_data; 926 + uint32_t rb_bufsz, tmp; 962 927 uint32_t lmi_swap_cntl; 963 928 964 929 /* disable byte swapping */ ··· 967 932 vcn_1_0_enable_static_power_gating(adev); 968 933 969 934 /* enable dynamic power gating mode */ 970 - reg_data = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 971 - reg_data |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 972 - reg_data |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 973 - WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data); 935 + tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 936 + tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 937 + tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 938 + WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 974 939 975 940 /* enable clock gating */ 976 941 vcn_v1_0_clock_gating_dpg_mode(adev, 0); 977 942 978 943 /* enable VCPU clock */ 979 - reg_data = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 980 - reg_data |= UVD_VCPU_CNTL__CLK_EN_MASK; 981 - reg_data |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 982 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, reg_data, 0xFFFFFFFF, 0); 944 + tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 945 + tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 946 + tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 947 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); 983 948 984 949 /* disable interupt */ 985 950 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 986 951 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 987 952 988 - /* stall UMC and register bus before resetting VCPU */ 989 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, 990 - UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); 991 - 992 - /* put LMI, VCPU, RBC etc... into reset */ 993 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 994 - UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 995 - UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 996 - UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 997 - UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 998 - UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 999 - UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 1000 - UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 1001 - UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1002 - 0xFFFFFFFF, 0); 1003 - 1004 953 /* initialize VCN memory controller */ 1005 954 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 1006 - (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 955 + (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1007 956 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1008 957 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1009 958 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1010 959 UVD_LMI_CTRL__REQ_MODE_MASK | 960 + UVD_LMI_CTRL__CRC_RESET_MASK | 961 + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1011 962 0x00100000L, 0xFFFFFFFF, 0); 1012 963 1013 964 #ifdef __BIG_ENDIAN ··· 1002 981 #endif 1003 982 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); 1004 983 1005 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040, 0xFFFFFFFF, 0); 1006 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0, 0xFFFFFFFF, 0); 1007 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040, 0xFFFFFFFF, 0); 1008 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0, 0xFFFFFFFF, 0); 1009 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_ALU, 0, 0xFFFFFFFF, 0); 1010 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, 0x88, 0xFFFFFFFF, 0); 984 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL, 985 + 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0); 986 + 987 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, 988 + ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 989 + (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 990 + (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 991 + (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); 992 + 993 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, 994 + ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 995 + (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 996 + (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 997 + (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); 998 + 999 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, 1000 + ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1001 + (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1002 + (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); 1011 1003 1012 1004 vcn_v1_0_mc_resume_dpg_mode(adev); 1013 1005 1014 - /* take all subblocks out of reset, except VCPU */ 1015 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 1016 - UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0xFFFFFFFF, 0); 1017 - 1018 - /* enable VCPU clock */ 1019 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, 1020 - UVD_VCPU_CNTL__CLK_EN_MASK, 0xFFFFFFFF, 0); 1021 - 1022 - /* enable UMC */ 1023 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, 1024 - 0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); 1006 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); 1007 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); 1025 1008 1026 1009 /* boot up the VCPU */ 1027 1010 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1028 1011 1012 + /* enable UMC */ 1013 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, 1014 + 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 1015 + 0xFFFFFFFF, 0); 1016 + 1029 1017 /* enable master interrupt */ 1030 1018 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 1031 - (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 1032 - (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 0); 1019 + UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 1033 1020 1034 1021 vcn_v1_0_clock_gating_dpg_mode(adev, 1); 1035 1022 /* setup mmUVD_LMI_CTRL */ 1036 1023 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 1037 - (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1038 - UVD_LMI_CTRL__CRC_RESET_MASK | 1039 - UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1040 - UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1041 - UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1042 - (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1043 - 0x00100000L), 0xFFFFFFFF, 1); 1024 + (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1025 + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1026 + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1027 + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1028 + UVD_LMI_CTRL__REQ_MODE_MASK | 1029 + UVD_LMI_CTRL__CRC_RESET_MASK | 1030 + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1031 + 0x00100000L, 0xFFFFFFFF, 1); 1044 1032 1045 1033 tmp = adev->gfx.config.gb_addr_config; 1046 1034 /* setup VCN global tiling registers */ ··· 1065 1035 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1066 1036 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1067 1037 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1068 - tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 1069 1038 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1070 1039 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1071 1040 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); ··· 1124 1095 */ 1125 1096 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 1126 1097 { 1127 - /* force RBC into idle state */ 1128 - WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101); 1098 + int ret_code, tmp; 1129 1099 1130 - /* Stall UMC and register bus before resetting VCPU */ 1131 - WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 1132 - UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1133 - ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1134 - mdelay(1); 1100 + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code); 1101 + 1102 + tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1103 + UVD_LMI_STATUS__READ_CLEAN_MASK | 1104 + UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1105 + UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1106 + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1135 1107 1136 1108 /* put VCPU into reset */ 1137 - WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 1138 - UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1139 - mdelay(5); 1109 + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1110 + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1111 + ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1112 + 1113 + tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1114 + UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1115 + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1140 1116 1141 1117 /* disable VCPU clock */ 1142 - WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0); 1118 + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1119 + ~UVD_VCPU_CNTL__CLK_EN_MASK); 1143 1120 1144 - /* Unstall UMC and register bus */ 1145 - WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 1146 - ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1121 + /* reset LMI UMC/LMI */ 1122 + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1123 + UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1124 + ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1147 1125 1148 - WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); 1126 + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1127 + UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1128 + ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1129 + 1130 + WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); 1149 1131 1150 1132 vcn_v1_0_enable_clock_gating(adev); 1151 1133 vcn_1_0_enable_static_power_gating(adev); ··· 1165 1125 1166 1126 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) 1167 1127 { 1168 - int ret_code; 1128 + int ret_code = 0; 1169 1129 1170 1130 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1171 1131 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1172 1132 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1173 1133 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1134 + 1135 + if (!ret_code) { 1136 + int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1137 + /* wait for read ptr to be equal to write ptr */ 1138 + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1139 + 1140 + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1141 + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1142 + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1143 + } 1174 1144 1175 1145 /* disable dynamic power gating mode */ 1176 1146 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,

+2 -1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

··· 705 705 int i; 706 706 struct dentry *ent, *dir = connector->base.debugfs_entry; 707 707 708 - if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 708 + if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 709 + connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 709 710 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 710 711 ent = debugfs_create_file(dp_debugfs_entries[i].name, 711 712 0644,

+6 -2

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

··· 1069 1069 struct dividers dividers) 1070 1070 { 1071 1071 struct gamma_pixel *p = points; 1072 - struct gamma_pixel *p_last = p + numberof_points - 1; 1072 + struct gamma_pixel *p_last; 1073 1073 1074 1074 uint32_t i = 0; 1075 + 1076 + // This function should not gets called with 0 as a parameter 1077 + ASSERT(numberof_points > 0); 1078 + p_last = p + numberof_points - 1; 1075 1079 1076 1080 do { 1077 1081 struct fixed31_32 value = dc_fixpt_from_fraction(i, ··· 1087 1083 1088 1084 ++p; 1089 1085 ++i; 1090 - } while (i != numberof_points); 1086 + } while (i < numberof_points); 1091 1087 1092 1088 p->r = dc_fixpt_div(p_last->r, dividers.divider1); 1093 1089 p->g = dc_fixpt_div(p_last->g, dividers.divider1);

+14

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

··· 82 82 #define mmUVD_LCM_CGC_CNTRL 0x0123 83 83 #define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1 84 84 85 + #define mmUVD_MIF_CURR_UV_ADDR_CONFIG 0x0184 86 + #define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX 1 87 + #define mmUVD_MIF_REF_UV_ADDR_CONFIG 0x0185 88 + #define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX 1 89 + #define mmUVD_MIF_RECON1_UV_ADDR_CONFIG 0x0186 90 + #define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX 1 91 + #define mmUVD_MIF_CURR_ADDR_CONFIG 0x0192 92 + #define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX 1 93 + #define mmUVD_MIF_REF_ADDR_CONFIG 0x0193 94 + #define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX 1 95 + #define mmUVD_MIF_RECON1_ADDR_CONFIG 0x01c5 96 + #define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX 1 85 97 86 98 // addressBlock: uvd_uvdnpdec 87 99 // base address: 0x20000 ··· 339 327 #define mmUVD_LMI_VM_CTRL_BASE_IDX 1 340 328 #define mmUVD_LMI_SWAP_CNTL 0x056d 341 329 #define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1 330 + #define mmUVD_MPC_CNTL 0x0577 331 + #define mmUVD_MPC_CNTL_BASE_IDX 1 342 332 #define mmUVD_MPC_SET_MUXA0 0x0579 343 333 #define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 344 334 #define mmUVD_MPC_SET_MUXA1 0x057a

+18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

··· 985 985 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 986 986 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 987 987 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 988 + #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 988 989 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 989 990 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 990 991 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L ··· 994 993 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 995 994 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 996 995 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 996 + #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L 997 997 //UVD_MASTINT_EN 998 998 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 999 999 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 ··· 1047 1045 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 1048 1046 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 1049 1047 #define UVD_LMI_CTRL__RFU_MASK 0xF8000000L 1048 + //UVD_LMI_STATUS 1049 + #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 1050 + #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 1051 + #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 1052 + #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 1053 + #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 1054 + #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 1055 + #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L 1056 + #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L 1057 + #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L 1058 + #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L 1059 + #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L 1060 + #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L 1050 1061 //UVD_LMI_SWAP_CNTL 1051 1062 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1052 1063 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 ··· 1093 1078 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L 1094 1079 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L 1095 1080 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L 1081 + //UVD_MPC_CNTL 1082 + #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 1083 + #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L 1096 1084 //UVD_MPC_SET_MUXA0 1097 1085 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 1098 1086 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

+88

drivers/gpu/drm/amd/include/atomfirmware.h

··· 1532 1532 uint32_t boardreserved[10]; 1533 1533 }; 1534 1534 1535 + struct smudpm_i2ccontrollerconfig_t { 1536 + uint32_t enabled; 1537 + uint32_t slaveaddress; 1538 + uint32_t controllerport; 1539 + uint32_t controllername; 1540 + uint32_t thermalthrottler; 1541 + uint32_t i2cprotocol; 1542 + uint32_t i2cspeed; 1543 + }; 1544 + 1545 + struct atom_smc_dpm_info_v4_4 1546 + { 1547 + struct atom_common_table_header table_header; 1548 + uint32_t i2c_padding[3]; 1549 + 1550 + uint16_t maxvoltagestepgfx; 1551 + uint16_t maxvoltagestepsoc; 1552 + 1553 + uint8_t vddgfxvrmapping; 1554 + uint8_t vddsocvrmapping; 1555 + uint8_t vddmem0vrmapping; 1556 + uint8_t vddmem1vrmapping; 1557 + 1558 + uint8_t gfxulvphasesheddingmask; 1559 + uint8_t soculvphasesheddingmask; 1560 + uint8_t externalsensorpresent; 1561 + uint8_t padding8_v; 1562 + 1563 + uint16_t gfxmaxcurrent; 1564 + uint8_t gfxoffset; 1565 + uint8_t padding_telemetrygfx; 1566 + 1567 + uint16_t socmaxcurrent; 1568 + uint8_t socoffset; 1569 + uint8_t padding_telemetrysoc; 1570 + 1571 + uint16_t mem0maxcurrent; 1572 + uint8_t mem0offset; 1573 + uint8_t padding_telemetrymem0; 1574 + 1575 + uint16_t mem1maxcurrent; 1576 + uint8_t mem1offset; 1577 + uint8_t padding_telemetrymem1; 1578 + 1579 + 1580 + uint8_t acdcgpio; 1581 + uint8_t acdcpolarity; 1582 + uint8_t vr0hotgpio; 1583 + uint8_t vr0hotpolarity; 1584 + 1585 + uint8_t vr1hotgpio; 1586 + uint8_t vr1hotpolarity; 1587 + uint8_t padding1; 1588 + uint8_t padding2; 1589 + 1590 + 1591 + uint8_t ledpin0; 1592 + uint8_t ledpin1; 1593 + uint8_t ledpin2; 1594 + uint8_t padding8_4; 1595 + 1596 + 1597 + uint8_t pllgfxclkspreadenabled; 1598 + uint8_t pllgfxclkspreadpercent; 1599 + uint16_t pllgfxclkspreadfreq; 1600 + 1601 + 1602 + uint8_t uclkspreadenabled; 1603 + uint8_t uclkspreadpercent; 1604 + uint16_t uclkspreadfreq; 1605 + 1606 + 1607 + uint8_t fclkspreadenabled; 1608 + uint8_t fclkspreadpercent; 1609 + uint16_t fclkspreadfreq; 1610 + 1611 + 1612 + uint8_t fllgfxclkspreadenabled; 1613 + uint8_t fllgfxclkspreadpercent; 1614 + uint16_t fllgfxclkspreadfreq; 1615 + 1616 + 1617 + struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7]; 1618 + 1619 + 1620 + uint32_t boardreserved[10]; 1621 + }; 1622 + 1535 1623 /* 1536 1624 *************************************************************************** 1537 1625 Data Table asic_profiling_info structure

+7 -2

drivers/gpu/drm/amd/powerplay/amd_powerplay.c

··· 894 894 pr_info("%s was not implemented.\n", __func__); 895 895 return ret; 896 896 } 897 + 898 + if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 899 + pr_info("power profile setting is for manual dpm mode only.\n"); 900 + return ret; 901 + } 902 + 897 903 mutex_lock(&hwmgr->smu_lock); 898 - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) 899 - ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size); 904 + ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size); 900 905 mutex_unlock(&hwmgr->smu_lock); 901 906 return ret; 902 907 }

+39 -3

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

··· 3175 3175 return result; 3176 3176 } 3177 3177 3178 + static int conv_power_profile_to_pplib_workload(int power_profile) 3179 + { 3180 + int pplib_workload = 0; 3181 + 3182 + switch (power_profile) { 3183 + case PP_SMC_POWER_PROFILE_FULLSCREEN3D: 3184 + pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT; 3185 + break; 3186 + case PP_SMC_POWER_PROFILE_POWERSAVING: 3187 + pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT; 3188 + break; 3189 + case PP_SMC_POWER_PROFILE_VIDEO: 3190 + pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT; 3191 + break; 3192 + case PP_SMC_POWER_PROFILE_VR: 3193 + pplib_workload = WORKLOAD_PPLIB_VR_BIT; 3194 + break; 3195 + case PP_SMC_POWER_PROFILE_COMPUTE: 3196 + pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT; 3197 + break; 3198 + case PP_SMC_POWER_PROFILE_CUSTOM: 3199 + pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT; 3200 + break; 3201 + } 3202 + 3203 + return pplib_workload; 3204 + } 3205 + 3178 3206 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 3179 3207 { 3180 3208 DpmActivityMonitorCoeffInt_t activity_monitor; ··· 3238 3210 3239 3211 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 3240 3212 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 3241 - workload_type = i + 1; 3213 + workload_type = conv_power_profile_to_pplib_workload(i); 3242 3214 result = vega20_get_activity_monitor_coeff(hwmgr, 3243 3215 (uint8_t *)(&activity_monitor), workload_type); 3244 3216 PP_ASSERT_WITH_CODE(!result, ··· 3311 3283 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 3312 3284 { 3313 3285 DpmActivityMonitorCoeffInt_t activity_monitor; 3314 - int result = 0; 3286 + int workload_type, result = 0; 3315 3287 3316 3288 hwmgr->power_profile_mode = input[size]; 3289 + 3290 + if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 3291 + pr_err("Invalid power profile mode %d\n", hwmgr->power_profile_mode); 3292 + return -EINVAL; 3293 + } 3317 3294 3318 3295 if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 3319 3296 if (size < 10) ··· 3386 3353 return result); 3387 3354 } 3388 3355 3356 + /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 3357 + workload_type = 3358 + conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode); 3389 3359 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, 3390 - 1 << hwmgr->power_profile_mode); 3360 + 1 << workload_type); 3391 3361 3392 3362 return 0; 3393 3363 }

+67 -37

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c

··· 100 100 pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold); 101 101 102 102 pr_info("MemoryOnPackage = 0x%02x\n", pptable->MemoryOnPackage); 103 - pr_info("padding8_limits[0] = 0x%02x\n", pptable->padding8_limits[0]); 104 - pr_info("padding8_limits[1] = 0x%02x\n", pptable->padding8_limits[1]); 105 - pr_info("padding8_limits[2] = 0x%02x\n", pptable->padding8_limits[2]); 103 + pr_info("padding8_limits = 0x%02x\n", pptable->padding8_limits); 104 + pr_info("Tvr_SocLimit = %d\n", pptable->Tvr_SocLimit); 106 105 107 106 pr_info("UlvVoltageOffsetSoc = %d\n", pptable->UlvVoltageOffsetSoc); 108 107 pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx); ··· 416 417 pr_info("FanGainEdge = %d\n", pptable->FanGainEdge); 417 418 pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot); 418 419 pr_info("FanGainLiquid = %d\n", pptable->FanGainLiquid); 419 - pr_info("FanGainVrVddc = %d\n", pptable->FanGainVrVddc); 420 - pr_info("FanGainVrMvdd = %d\n", pptable->FanGainVrMvdd); 420 + pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx); 421 + pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc); 421 422 pr_info("FanGainPlx = %d\n", pptable->FanGainPlx); 422 423 pr_info("FanGainHbm = %d\n", pptable->FanGainHbm); 423 424 pr_info("FanPwmMin = %d\n", pptable->FanPwmMin); ··· 532 533 pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx); 533 534 pr_info("MinVoltageUlvSoc = %d\n", pptable->MinVoltageUlvSoc); 534 535 535 - for (i = 0; i < 14; i++) 536 + pr_info("MGpuFanBoostLimitRpm = %d\n", pptable->MGpuFanBoostLimitRpm); 537 + pr_info("padding16_Fan = %d\n", pptable->padding16_Fan); 538 + 539 + pr_info("FanGainVrMem0 = %d\n", pptable->FanGainVrMem0); 540 + pr_info("FanGainVrMem0 = %d\n", pptable->FanGainVrMem0); 541 + 542 + pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 543 + pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 544 + 545 + for (i = 0; i < 11; i++) 536 546 pr_info("Reserved[%d] = 0x%x\n", i, pptable->Reserved[i]); 537 547 538 - pr_info("Liquid1_I2C_address = 0x%x\n", pptable->Liquid1_I2C_address); 539 - pr_info("Liquid2_I2C_address = 0x%x\n", pptable->Liquid2_I2C_address); 540 - pr_info("Vr_I2C_address = 0x%x\n", pptable->Vr_I2C_address); 541 - pr_info("Plx_I2C_address = 0x%x\n", pptable->Plx_I2C_address); 542 - 543 - pr_info("Liquid_I2C_LineSCL = 0x%x\n", pptable->Liquid_I2C_LineSCL); 544 - pr_info("Liquid_I2C_LineSDA = 0x%x\n", pptable->Liquid_I2C_LineSDA); 545 - pr_info("Vr_I2C_LineSCL = 0x%x\n", pptable->Vr_I2C_LineSCL); 546 - pr_info("Vr_I2C_LineSDA = 0x%x\n", pptable->Vr_I2C_LineSDA); 547 - 548 - pr_info("Plx_I2C_LineSCL = 0x%x\n", pptable->Plx_I2C_LineSCL); 549 - pr_info("Plx_I2C_LineSDA = 0x%x\n", pptable->Plx_I2C_LineSDA); 550 - pr_info("VrSensorPresent = 0x%x\n", pptable->VrSensorPresent); 551 - pr_info("LiquidSensorPresent = 0x%x\n", pptable->LiquidSensorPresent); 548 + for (i = 0; i < 3; i++) 549 + pr_info("Padding32[%d] = 0x%x\n", i, pptable->Padding32[i]); 552 550 553 551 pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx); 554 552 pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc); ··· 606 610 pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled); 607 611 pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent); 608 612 pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq); 613 + 614 + for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) { 615 + pr_info("I2cControllers[%d]:\n", i); 616 + pr_info(" .Enabled = %d\n", 617 + pptable->I2cControllers[i].Enabled); 618 + pr_info(" .SlaveAddress = 0x%x\n", 619 + pptable->I2cControllers[i].SlaveAddress); 620 + pr_info(" .ControllerPort = %d\n", 621 + pptable->I2cControllers[i].ControllerPort); 622 + pr_info(" .ControllerName = %d\n", 623 + pptable->I2cControllers[i].ControllerName); 624 + pr_info(" .ThermalThrottler = %d\n", 625 + pptable->I2cControllers[i].ThermalThrottler); 626 + pr_info(" .I2cProtocol = %d\n", 627 + pptable->I2cControllers[i].I2cProtocol); 628 + pr_info(" .I2cSpeed = %d\n", 629 + pptable->I2cControllers[i].I2cSpeed); 630 + } 609 631 610 632 for (i = 0; i < 10; i++) 611 633 pr_info("BoardReserved[%d] = 0x%x\n", i, pptable->BoardReserved[i]); ··· 707 693 708 694 static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable) 709 695 { 710 - struct atom_smc_dpm_info_v4_3 *smc_dpm_table; 696 + struct atom_smc_dpm_info_v4_4 *smc_dpm_table; 711 697 int index = GetIndexIntoMasterDataTable(smc_dpm_info); 698 + int i; 712 699 713 700 PP_ASSERT_WITH_CODE( 714 701 smc_dpm_table = smu_atom_get_data_table(hwmgr->adev, index, NULL, NULL, NULL), 715 702 "[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!", 716 703 return -1); 717 704 718 - ppsmc_pptable->Liquid1_I2C_address = smc_dpm_table->liquid1_i2c_address; 719 - ppsmc_pptable->Liquid2_I2C_address = smc_dpm_table->liquid2_i2c_address; 720 - ppsmc_pptable->Vr_I2C_address = smc_dpm_table->vr_i2c_address; 721 - ppsmc_pptable->Plx_I2C_address = smc_dpm_table->plx_i2c_address; 722 - 723 - ppsmc_pptable->Liquid_I2C_LineSCL = smc_dpm_table->liquid_i2c_linescl; 724 - ppsmc_pptable->Liquid_I2C_LineSDA = smc_dpm_table->liquid_i2c_linesda; 725 - ppsmc_pptable->Vr_I2C_LineSCL = smc_dpm_table->vr_i2c_linescl; 726 - ppsmc_pptable->Vr_I2C_LineSDA = smc_dpm_table->vr_i2c_linesda; 727 - 728 - ppsmc_pptable->Plx_I2C_LineSCL = smc_dpm_table->plx_i2c_linescl; 729 - ppsmc_pptable->Plx_I2C_LineSDA = smc_dpm_table->plx_i2c_linesda; 730 - ppsmc_pptable->VrSensorPresent = smc_dpm_table->vrsensorpresent; 731 - ppsmc_pptable->LiquidSensorPresent = smc_dpm_table->liquidsensorpresent; 732 - 705 + memset(ppsmc_pptable->Padding32, 706 + 0, 707 + sizeof(struct atom_smc_dpm_info_v4_4) - 708 + sizeof(struct atom_common_table_header)); 733 709 ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx; 734 710 ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc; 735 711 ··· 777 773 ppsmc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled; 778 774 ppsmc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent; 779 775 ppsmc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq; 776 + 777 + if ((smc_dpm_table->table_header.format_revision == 4) && 778 + (smc_dpm_table->table_header.content_revision == 4)) { 779 + for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) { 780 + ppsmc_pptable->I2cControllers[i].Enabled = 781 + smc_dpm_table->i2ccontrollers[i].enabled; 782 + ppsmc_pptable->I2cControllers[i].SlaveAddress = 783 + smc_dpm_table->i2ccontrollers[i].slaveaddress; 784 + ppsmc_pptable->I2cControllers[i].ControllerPort = 785 + smc_dpm_table->i2ccontrollers[i].controllerport; 786 + ppsmc_pptable->I2cControllers[i].ThermalThrottler = 787 + smc_dpm_table->i2ccontrollers[i].thermalthrottler; 788 + ppsmc_pptable->I2cControllers[i].I2cProtocol = 789 + smc_dpm_table->i2ccontrollers[i].i2cprotocol; 790 + ppsmc_pptable->I2cControllers[i].I2cSpeed = 791 + smc_dpm_table->i2ccontrollers[i].i2cspeed; 792 + } 793 + } 780 794 781 795 return 0; 782 796 } ··· 882 860 if (pptable_information->smc_pptable == NULL) 883 861 return -ENOMEM; 884 862 885 - memcpy(pptable_information->smc_pptable, &(powerplay_table->smcPPTable), sizeof(PPTable_t)); 863 + if (powerplay_table->smcPPTable.Version <= 2) 864 + memcpy(pptable_information->smc_pptable, 865 + &(powerplay_table->smcPPTable), 866 + sizeof(PPTable_t) - 867 + sizeof(I2cControllerConfig_t) * I2C_CONTROLLER_NAME_COUNT); 868 + else 869 + memcpy(pptable_information->smc_pptable, 870 + &(powerplay_table->smcPPTable), 871 + sizeof(PPTable_t)); 886 872 887 873 result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable)); 888 874

+83 -32

drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h

··· 27 27 // *** IMPORTANT *** 28 28 // SMU TEAM: Always increment the interface version if 29 29 // any structure is changed in this file 30 - #define SMU11_DRIVER_IF_VERSION 0x11 30 + #define SMU11_DRIVER_IF_VERSION 0x12 31 31 32 32 #define PPTABLE_V20_SMU_VERSION 2 33 33 ··· 165 165 #define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT ) 166 166 #define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT ) 167 167 #define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT ) 168 - 168 + #define FEATURE_XGMI_MASK (1 << FEATURE_XGMI_BIT ) 169 169 170 170 #define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001 171 171 #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 ··· 185 185 #define DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH 0x00008000 186 186 #define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH 0x00010000 187 187 #define DPM_OVERRIDE_ENABLE_GFXOFF_FCLK_SWITCH 0x00020000 188 + 189 + #define I2C_CONTROLLER_ENABLED 1 190 + #define I2C_CONTROLLER_DISABLED 0 188 191 189 192 #define VR_MAPPING_VR_SELECT_MASK 0x01 190 193 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 ··· 211 208 #define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2 212 209 #define THROTTLER_STATUS_TEMP_HBM_BIT 3 213 210 #define THROTTLER_STATUS_TEMP_VR_GFX_BIT 4 214 - #define THROTTLER_STATUS_TEMP_VR_MEM_BIT 5 215 - #define THROTTLER_STATUS_TEMP_LIQUID_BIT 6 216 - #define THROTTLER_STATUS_TEMP_PLX_BIT 7 217 - #define THROTTLER_STATUS_TEMP_SKIN_BIT 8 218 - #define THROTTLER_STATUS_TDC_GFX_BIT 9 219 - #define THROTTLER_STATUS_TDC_SOC_BIT 10 220 - #define THROTTLER_STATUS_PPT_BIT 11 221 - #define THROTTLER_STATUS_FIT_BIT 12 222 - #define THROTTLER_STATUS_PPM_BIT 13 211 + #define THROTTLER_STATUS_TEMP_VR_SOC_BIT 5 212 + #define THROTTLER_STATUS_TEMP_VR_MEM0_BIT 6 213 + #define THROTTLER_STATUS_TEMP_VR_MEM1_BIT 7 214 + #define THROTTLER_STATUS_TEMP_LIQUID_BIT 8 215 + #define THROTTLER_STATUS_TEMP_PLX_BIT 9 216 + #define THROTTLER_STATUS_TEMP_SKIN_BIT 10 217 + #define THROTTLER_STATUS_TDC_GFX_BIT 11 218 + #define THROTTLER_STATUS_TDC_SOC_BIT 12 219 + #define THROTTLER_STATUS_PPT_BIT 13 220 + #define THROTTLER_STATUS_FIT_BIT 14 221 + #define THROTTLER_STATUS_PPM_BIT 15 223 222 224 223 225 224 #define TABLE_TRANSFER_OK 0x0 ··· 240 235 241 236 #define XGMI_STATE_D0 1 242 237 #define XGMI_STATE_D3 0 238 + 239 + typedef enum { 240 + I2C_CONTROLLER_PORT_0 = 0, 241 + I2C_CONTROLLER_PORT_1 = 1, 242 + } I2cControllerPort_e; 243 + 244 + typedef enum { 245 + I2C_CONTROLLER_NAME_VR_GFX = 0, 246 + I2C_CONTROLLER_NAME_VR_SOC, 247 + I2C_CONTROLLER_NAME_VR_VDDCI, 248 + I2C_CONTROLLER_NAME_VR_HBM, 249 + I2C_CONTROLLER_NAME_LIQUID_0, 250 + I2C_CONTROLLER_NAME_LIQUID_1, 251 + I2C_CONTROLLER_NAME_PLX, 252 + I2C_CONTROLLER_NAME_COUNT, 253 + } I2cControllerName_e; 254 + 255 + typedef enum { 256 + I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 257 + I2C_CONTROLLER_THROTTLER_VR_GFX, 258 + I2C_CONTROLLER_THROTTLER_VR_SOC, 259 + I2C_CONTROLLER_THROTTLER_VR_VDDCI, 260 + I2C_CONTROLLER_THROTTLER_VR_HBM, 261 + I2C_CONTROLLER_THROTTLER_LIQUID_0, 262 + I2C_CONTROLLER_THROTTLER_LIQUID_1, 263 + I2C_CONTROLLER_THROTTLER_PLX, 264 + } I2cControllerThrottler_e; 265 + 266 + typedef enum { 267 + I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 268 + I2C_CONTROLLER_PROTOCOL_VR_IR35217, 269 + I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 270 + I2C_CONTROLLER_PROTOCOL_SPARE_0, 271 + I2C_CONTROLLER_PROTOCOL_SPARE_1, 272 + I2C_CONTROLLER_PROTOCOL_SPARE_2, 273 + } I2cControllerProtocol_e; 274 + 275 + typedef enum { 276 + I2C_CONTROLLER_SPEED_SLOW = 0, 277 + I2C_CONTROLLER_SPEED_FAST = 1, 278 + } I2cControllerSpeed_e; 279 + 280 + typedef struct { 281 + uint32_t Enabled; 282 + uint32_t SlaveAddress; 283 + uint32_t ControllerPort; 284 + uint32_t ControllerName; 285 + 286 + uint32_t ThermalThrottler; 287 + uint32_t I2cProtocol; 288 + uint32_t I2cSpeed; 289 + } I2cControllerConfig_t; 243 290 244 291 typedef struct { 245 292 uint32_t a; ··· 391 334 uint16_t PpmTemperatureThreshold; 392 335 393 336 uint8_t MemoryOnPackage; 394 - uint8_t padding8_limits[3]; 395 - 337 + uint8_t padding8_limits; 338 + uint16_t Tvr_SocLimit; 396 339 397 340 uint16_t UlvVoltageOffsetSoc; 398 341 uint16_t UlvVoltageOffsetGfx; ··· 463 406 uint16_t FanGainEdge; 464 407 uint16_t FanGainHotspot; 465 408 uint16_t FanGainLiquid; 466 - uint16_t FanGainVrVddc; 467 - uint16_t FanGainVrMvdd; 409 + uint16_t FanGainVrGfx; 410 + uint16_t FanGainVrSoc; 468 411 uint16_t FanGainPlx; 469 412 uint16_t FanGainHbm; 470 413 uint16_t FanPwmMin; ··· 501 444 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 502 445 uint8_t Padding8_GfxBtc[2]; 503 446 504 - uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; 447 + int16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; 505 448 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; 506 449 507 450 ··· 524 467 uint16_t MGpuFanBoostLimitRpm; 525 468 uint16_t padding16_Fan; 526 469 527 - uint32_t Reserved[13]; 470 + uint16_t FanGainVrMem0; 471 + uint16_t FanGainVrMem1; 528 472 473 + uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; 529 474 475 + uint32_t Reserved[11]; 530 476 531 - uint8_t Liquid1_I2C_address; 532 - uint8_t Liquid2_I2C_address; 533 - uint8_t Vr_I2C_address; 534 - uint8_t Plx_I2C_address; 535 - 536 - uint8_t Liquid_I2C_LineSCL; 537 - uint8_t Liquid_I2C_LineSDA; 538 - uint8_t Vr_I2C_LineSCL; 539 - uint8_t Vr_I2C_LineSDA; 540 - 541 - uint8_t Plx_I2C_LineSCL; 542 - uint8_t Plx_I2C_LineSDA; 543 - uint8_t VrSensorPresent; 544 - uint8_t LiquidSensorPresent; 477 + uint32_t Padding32[3]; 545 478 546 479 uint16_t MaxVoltageStepGfx; 547 480 uint16_t MaxVoltageStepSoc; ··· 598 551 uint8_t FllGfxclkSpreadPercent; 599 552 uint16_t FllGfxclkSpreadFreq; 600 553 554 + I2cControllerConfig_t I2cControllers[I2C_CONTROLLER_NAME_COUNT]; 555 + 601 556 uint32_t BoardReserved[10]; 602 557 603 558 ··· 656 607 uint16_t TemperatureHotspot ; 657 608 uint16_t TemperatureHBM ; 658 609 uint16_t TemperatureVrGfx ; 659 - uint16_t TemperatureVrMem ; 610 + uint16_t TemperatureVrSoc ; 611 + uint16_t TemperatureVrMem0 ; 612 + uint16_t TemperatureVrMem1 ; 660 613 uint16_t TemperatureLiquid ; 661 614 uint16_t TemperaturePlx ; 662 615 uint32_t ThrottlerStatus ;

+1 -1

drivers/gpu/drm/radeon/mkregtable.c

··· 1 - // SPDX-License-Identifier: GPL-2.0 1 + // SPDX-License-Identifier: MIT 2 2 /* utility to create the register check tables 3 3 * this includes inlined list.h safe for userspace. 4 4 *

+1 -1

drivers/gpu/drm/radeon/r100_track.h

··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 1 + /* SPDX-License-Identifier: MIT */ 2 2 3 3 #define R100_TRACK_MAX_TEXTURE 3 4 4 #define R200_TRACK_MAX_TEXTURE 6

+1 -1

drivers/gpu/drm/radeon/radeon_dp_mst.c

··· 1 - // SPDX-License-Identifier: GPL-2.0 1 + // SPDX-License-Identifier: MIT 2 2 3 3 #include <drm/drmP.h> 4 4 #include <drm/drm_dp_mst_helper.h>

+1 -1

drivers/gpu/drm/radeon/radeon_legacy_tv.c

··· 1 - // SPDX-License-Identifier: GPL-2.0 1 + // SPDX-License-Identifier: MIT 2 2 #include <drm/drmP.h> 3 3 #include <drm/drm_crtc_helper.h> 4 4 #include "radeon.h"

+1 -1

drivers/gpu/drm/radeon/radeon_trace.h

··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 1 + /* SPDX-License-Identifier: MIT */ 2 2 #if !defined(_RADEON_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) 3 3 #define _RADEON_TRACE_H_ 4 4

+1 -1

drivers/gpu/drm/radeon/radeon_trace_points.c

··· 1 - // SPDX-License-Identifier: GPL-2.0 1 + // SPDX-License-Identifier: MIT 2 2 /* Copyright Red Hat Inc 2010. 3 3 * Author : Dave Airlie <airlied@redhat.com> 4 4 */

+46 -13

drivers/gpu/drm/scheduler/sched_main.c

··· 182 182 } 183 183 EXPORT_SYMBOL(drm_sched_dependency_optimized); 184 184 185 + /** 186 + * drm_sched_start_timeout - start timeout for reset worker 187 + * 188 + * @sched: scheduler instance to start the worker for 189 + * 190 + * Start the timeout for the given scheduler. 191 + */ 192 + static void drm_sched_start_timeout(struct drm_gpu_scheduler *sched) 193 + { 194 + if (sched->timeout != MAX_SCHEDULE_TIMEOUT && 195 + !list_empty(&sched->ring_mirror_list)) 196 + schedule_delayed_work(&sched->work_tdr, sched->timeout); 197 + } 198 + 185 199 /* job_finish is called after hw fence signaled 186 200 */ 187 201 static void drm_sched_job_finish(struct work_struct *work) ··· 217 203 /* remove job from ring_mirror_list */ 218 204 list_del(&s_job->node); 219 205 /* queue TDR for next job */ 220 - if (sched->timeout != MAX_SCHEDULE_TIMEOUT && 221 - !list_empty(&sched->ring_mirror_list)) 222 - schedule_delayed_work(&sched->work_tdr, sched->timeout); 206 + drm_sched_start_timeout(sched); 223 207 spin_unlock(&sched->job_list_lock); 224 208 225 209 dma_fence_put(&s_job->s_fence->finished); ··· 241 229 242 230 spin_lock(&sched->job_list_lock); 243 231 list_add_tail(&s_job->node, &sched->ring_mirror_list); 244 - if (sched->timeout != MAX_SCHEDULE_TIMEOUT && 245 - list_first_entry_or_null(&sched->ring_mirror_list, 246 - struct drm_sched_job, node) == s_job) 247 - schedule_delayed_work(&sched->work_tdr, sched->timeout); 232 + drm_sched_start_timeout(sched); 248 233 spin_unlock(&sched->job_list_lock); 249 234 } 250 235 ··· 249 240 { 250 241 struct drm_gpu_scheduler *sched; 251 242 struct drm_sched_job *job; 243 + int r; 252 244 253 245 sched = container_of(work, struct drm_gpu_scheduler, work_tdr.work); 246 + 247 + spin_lock(&sched->job_list_lock); 248 + list_for_each_entry_reverse(job, &sched->ring_mirror_list, node) { 249 + struct drm_sched_fence *fence = job->s_fence; 250 + 251 + if (!dma_fence_remove_callback(fence->parent, &fence->cb)) 252 + goto already_signaled; 253 + } 254 + 254 255 job = list_first_entry_or_null(&sched->ring_mirror_list, 255 256 struct drm_sched_job, node); 257 + spin_unlock(&sched->job_list_lock); 256 258 257 259 if (job) 258 - job->sched->ops->timedout_job(job); 260 + sched->ops->timedout_job(job); 261 + 262 + spin_lock(&sched->job_list_lock); 263 + list_for_each_entry(job, &sched->ring_mirror_list, node) { 264 + struct drm_sched_fence *fence = job->s_fence; 265 + 266 + if (!fence->parent || !list_empty(&fence->cb.node)) 267 + continue; 268 + 269 + r = dma_fence_add_callback(fence->parent, &fence->cb, 270 + drm_sched_process_job); 271 + if (r) 272 + drm_sched_process_job(fence->parent, &fence->cb); 273 + 274 + already_signaled: 275 + ; 276 + } 277 + spin_unlock(&sched->job_list_lock); 259 278 } 260 279 261 280 /** ··· 350 313 int r; 351 314 352 315 spin_lock(&sched->job_list_lock); 353 - s_job = list_first_entry_or_null(&sched->ring_mirror_list, 354 - struct drm_sched_job, node); 355 - if (s_job && sched->timeout != MAX_SCHEDULE_TIMEOUT) 356 - schedule_delayed_work(&sched->work_tdr, sched->timeout); 357 - 358 316 list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) { 359 317 struct drm_sched_fence *s_fence = s_job->s_fence; 360 318 struct dma_fence *fence; ··· 382 350 } 383 351 spin_lock(&sched->job_list_lock); 384 352 } 353 + drm_sched_start_timeout(sched); 385 354 spin_unlock(&sched->job_list_lock); 386 355 } 387 356 EXPORT_SYMBOL(drm_sched_job_recovery);

+1 -1

include/drm/drm_pciids.h

··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 1 + /* SPDX-License-Identifier: MIT */ 2 2 #define radeon_PCI_IDS \ 3 3 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 4 4 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \