pinctrl: sunxi: Declare the interrupt function for the A31

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

The primary pinctrl device has 4 interrupt banks. As usual, to be able to
generate interrupts, the pins supporting it need to be muxed to a special
function. Declare these functions in the pins array.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Maxime Ripard and committed by

Linus Walleij 11 years ago c11a33c1 8966ada2

+144 -72

1 changed file

expand all

drivers

pinctrl

sunxi

pinctrl-sun6i-a31.c

+144 -72

drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c

··· 24 24 SUNXI_FUNCTION(0x1, "gpio_out"), 25 25 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */ 26 26 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */ 27 - SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ 27 + SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ 28 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ 28 29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), 29 30 SUNXI_FUNCTION(0x0, "gpio_in"), 30 31 SUNXI_FUNCTION(0x1, "gpio_out"), 31 32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */ 32 33 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */ 33 - SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ 34 + SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ 35 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ 34 36 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), 35 37 SUNXI_FUNCTION(0x0, "gpio_in"), 36 38 SUNXI_FUNCTION(0x1, "gpio_out"), 37 39 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */ 38 40 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */ 39 - SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ 41 + SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ 42 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ 40 43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), 41 44 SUNXI_FUNCTION(0x0, "gpio_in"), 42 45 SUNXI_FUNCTION(0x1, "gpio_out"), 43 46 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */ 44 47 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */ 45 - SUNXI_FUNCTION(0x4, "uart1")), /* RING */ 48 + SUNXI_FUNCTION(0x4, "uart1"), /* RING */ 49 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ 46 50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), 47 51 SUNXI_FUNCTION(0x0, "gpio_in"), 48 52 SUNXI_FUNCTION(0x1, "gpio_out"), 49 53 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */ 50 54 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */ 51 - SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 55 + SUNXI_FUNCTION(0x4, "uart1"), /* TX */ 56 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ 52 57 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), 53 58 SUNXI_FUNCTION(0x0, "gpio_in"), 54 59 SUNXI_FUNCTION(0x1, "gpio_out"), 55 60 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */ 56 61 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */ 57 - SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 62 + SUNXI_FUNCTION(0x4, "uart1"), /* RX */ 63 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ 58 64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), 59 65 SUNXI_FUNCTION(0x0, "gpio_in"), 60 66 SUNXI_FUNCTION(0x1, "gpio_out"), 61 67 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */ 62 68 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */ 63 - SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ 69 + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ 70 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ 64 71 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), 65 72 SUNXI_FUNCTION(0x0, "gpio_in"), 66 73 SUNXI_FUNCTION(0x1, "gpio_out"), 67 74 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */ 68 75 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */ 69 - SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ 76 + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ 77 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ 70 78 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), 71 79 SUNXI_FUNCTION(0x0, "gpio_in"), 72 80 SUNXI_FUNCTION(0x1, "gpio_out"), 73 81 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */ 74 - SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */ 82 + SUNXI_FUNCTION(0x3, "lcd1"), /* D8 */ 83 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ 75 84 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), 76 85 SUNXI_FUNCTION(0x0, "gpio_in"), 77 86 SUNXI_FUNCTION(0x1, "gpio_out"), 78 87 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */ 79 88 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */ 80 89 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */ 81 - SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */ 90 + SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */ 91 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ 82 92 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), 83 93 SUNXI_FUNCTION(0x0, "gpio_in"), 84 94 SUNXI_FUNCTION(0x1, "gpio_out"), 85 95 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */ 86 96 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */ 87 97 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */ 88 - SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */ 98 + SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */ 99 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ 89 100 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), 90 101 SUNXI_FUNCTION(0x0, "gpio_in"), 91 102 SUNXI_FUNCTION(0x1, "gpio_out"), 92 103 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */ 93 104 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */ 94 105 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */ 95 - SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */ 106 + SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */ 107 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ 96 108 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), 97 109 SUNXI_FUNCTION(0x0, "gpio_in"), 98 110 SUNXI_FUNCTION(0x1, "gpio_out"), 99 111 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */ 100 112 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */ 101 113 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */ 102 - SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */ 114 + SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */ 115 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ 103 116 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), 104 117 SUNXI_FUNCTION(0x0, "gpio_in"), 105 118 SUNXI_FUNCTION(0x1, "gpio_out"), 106 119 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */ 107 120 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */ 108 121 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */ 109 - SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */ 122 + SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */ 123 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */ 110 124 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), 111 125 SUNXI_FUNCTION(0x0, "gpio_in"), 112 126 SUNXI_FUNCTION(0x1, "gpio_out"), 113 127 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */ 114 128 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */ 115 129 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */ 116 - SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */ 130 + SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */ 131 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */ 117 132 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), 118 133 SUNXI_FUNCTION(0x0, "gpio_in"), 119 134 SUNXI_FUNCTION(0x1, "gpio_out"), 120 135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */ 121 - SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */ 136 + SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */ 137 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ 122 138 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), 123 139 SUNXI_FUNCTION(0x0, "gpio_in"), 124 140 SUNXI_FUNCTION(0x1, "gpio_out"), 125 141 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */ 126 - SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */ 142 + SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */ 143 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ 127 144 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), 128 145 SUNXI_FUNCTION(0x0, "gpio_in"), 129 146 SUNXI_FUNCTION(0x1, "gpio_out"), 130 147 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */ 131 - SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */ 148 + SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */ 149 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ 132 150 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), 133 151 SUNXI_FUNCTION(0x0, "gpio_in"), 134 152 SUNXI_FUNCTION(0x1, "gpio_out"), 135 153 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */ 136 - SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */ 154 + SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */ 155 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ 137 156 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), 138 157 SUNXI_FUNCTION(0x0, "gpio_in"), 139 158 SUNXI_FUNCTION(0x1, "gpio_out"), 140 159 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */ 141 160 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */ 142 - SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */ 161 + SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */ 162 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */ 143 163 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), 144 164 SUNXI_FUNCTION(0x0, "gpio_in"), 145 165 SUNXI_FUNCTION(0x1, "gpio_out"), 146 166 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */ 147 167 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */ 148 - SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */ 168 + SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */ 169 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */ 149 170 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), 150 171 SUNXI_FUNCTION(0x0, "gpio_in"), 151 172 SUNXI_FUNCTION(0x1, "gpio_out"), 152 173 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */ 153 174 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */ 154 - SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */ 175 + SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */ 176 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */ 155 177 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22), 156 178 SUNXI_FUNCTION(0x0, "gpio_in"), 157 179 SUNXI_FUNCTION(0x1, "gpio_out"), 158 180 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */ 159 181 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */ 160 - SUNXI_FUNCTION(0x4, "spi3")), /* CLK */ 182 + SUNXI_FUNCTION(0x4, "spi3"), /* CLK */ 183 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */ 161 184 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23), 162 185 SUNXI_FUNCTION(0x0, "gpio_in"), 163 186 SUNXI_FUNCTION(0x1, "gpio_out"), 164 187 SUNXI_FUNCTION(0x2, "gmac"), /* COL */ 165 188 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */ 166 - SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */ 189 + SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */ 190 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */ 167 191 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24), 168 192 SUNXI_FUNCTION(0x0, "gpio_in"), 169 193 SUNXI_FUNCTION(0x1, "gpio_out"), 170 194 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */ 171 195 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */ 172 - SUNXI_FUNCTION(0x4, "spi3")), /* MISO */ 196 + SUNXI_FUNCTION(0x4, "spi3"), /* MISO */ 197 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */ 173 198 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25), 174 199 SUNXI_FUNCTION(0x0, "gpio_in"), 175 200 SUNXI_FUNCTION(0x1, "gpio_out"), 176 201 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */ 177 202 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */ 178 - SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */ 203 + SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */ 204 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */ 179 205 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26), 180 206 SUNXI_FUNCTION(0x0, "gpio_in"), 181 207 SUNXI_FUNCTION(0x1, "gpio_out"), 182 208 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */ 183 - SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */ 209 + SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */ 210 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */ 184 211 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27), 185 212 SUNXI_FUNCTION(0x0, "gpio_in"), 186 213 SUNXI_FUNCTION(0x1, "gpio_out"), 187 214 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */ 188 - SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */ 215 + SUNXI_FUNCTION(0x3, "lcd1"), /* VSYNC */ 216 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */ 189 217 /* Hole */ 190 218 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), 191 219 SUNXI_FUNCTION(0x0, "gpio_in"), 192 220 SUNXI_FUNCTION(0x1, "gpio_out"), 193 221 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ 194 222 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 195 - SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */ 223 + SUNXI_FUNCTION(0x4, "csi"), /* MCLK1 */ 224 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */ 196 225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), 197 226 SUNXI_FUNCTION(0x0, "gpio_in"), 198 227 SUNXI_FUNCTION(0x1, "gpio_out"), 199 - SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */ 228 + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ 229 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */ 200 230 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), 201 231 SUNXI_FUNCTION(0x0, "gpio_in"), 202 232 SUNXI_FUNCTION(0x1, "gpio_out"), 203 - SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */ 233 + SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */ 234 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */ 204 235 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), 205 236 SUNXI_FUNCTION(0x0, "gpio_in"), 206 237 SUNXI_FUNCTION(0x1, "gpio_out"), 207 - SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */ 238 + SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */ 239 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */ 208 240 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), 209 241 SUNXI_FUNCTION(0x0, "gpio_in"), 210 242 SUNXI_FUNCTION(0x1, "gpio_out"), 211 243 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */ 212 - SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ 244 + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ 245 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */ 213 246 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), 214 247 SUNXI_FUNCTION(0x0, "gpio_in"), 215 248 SUNXI_FUNCTION(0x1, "gpio_out"), 216 249 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */ 217 250 SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 218 - SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */ 251 + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */ 252 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */ 219 253 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), 220 254 SUNXI_FUNCTION(0x0, "gpio_in"), 221 255 SUNXI_FUNCTION(0x1, "gpio_out"), 222 256 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */ 223 257 SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 224 - SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */ 258 + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */ 259 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */ 225 260 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), 226 261 SUNXI_FUNCTION(0x0, "gpio_in"), 227 262 SUNXI_FUNCTION(0x1, "gpio_out"), 228 - SUNXI_FUNCTION(0x3, "i2s0")), /* DI */ 263 + SUNXI_FUNCTION(0x3, "i2s0"), /* DI */ 264 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */ 229 265 /* Hole */ 230 266 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 231 267 SUNXI_FUNCTION(0x0, "gpio_in"), ··· 546 510 SUNXI_FUNCTION(0x0, "gpio_in"), 547 511 SUNXI_FUNCTION(0x1, "gpio_out"), 548 512 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ 549 - SUNXI_FUNCTION(0x3, "ts")), /* CLK */ 513 + SUNXI_FUNCTION(0x3, "ts"), /* CLK */ 514 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */ 550 515 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), 551 516 SUNXI_FUNCTION(0x0, "gpio_in"), 552 517 SUNXI_FUNCTION(0x1, "gpio_out"), 553 518 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ 554 - SUNXI_FUNCTION(0x3, "ts")), /* ERR */ 519 + SUNXI_FUNCTION(0x3, "ts"), /* ERR */ 520 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */ 555 521 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), 556 522 SUNXI_FUNCTION(0x0, "gpio_in"), 557 523 SUNXI_FUNCTION(0x1, "gpio_out"), 558 524 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ 559 - SUNXI_FUNCTION(0x3, "ts")), /* SYNC */ 525 + SUNXI_FUNCTION(0x3, "ts"), /* SYNC */ 526 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */ 560 527 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), 561 528 SUNXI_FUNCTION(0x0, "gpio_in"), 562 529 SUNXI_FUNCTION(0x1, "gpio_out"), 563 530 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ 564 - SUNXI_FUNCTION(0x3, "ts")), /* DVLD */ 531 + SUNXI_FUNCTION(0x3, "ts"), /* DVLD */ 532 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */ 565 533 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), 566 534 SUNXI_FUNCTION(0x0, "gpio_in"), 567 535 SUNXI_FUNCTION(0x1, "gpio_out"), 568 536 SUNXI_FUNCTION(0x2, "csi"), /* D0 */ 569 - SUNXI_FUNCTION(0x3, "uart5")), /* TX */ 537 + SUNXI_FUNCTION(0x3, "uart5"), /* TX */ 538 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */ 570 539 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), 571 540 SUNXI_FUNCTION(0x0, "gpio_in"), 572 541 SUNXI_FUNCTION(0x1, "gpio_out"), 573 542 SUNXI_FUNCTION(0x2, "csi"), /* D1 */ 574 - SUNXI_FUNCTION(0x3, "uart5")), /* RX */ 543 + SUNXI_FUNCTION(0x3, "uart5"), /* RX */ 544 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */ 575 545 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), 576 546 SUNXI_FUNCTION(0x0, "gpio_in"), 577 547 SUNXI_FUNCTION(0x1, "gpio_out"), 578 548 SUNXI_FUNCTION(0x2, "csi"), /* D2 */ 579 - SUNXI_FUNCTION(0x3, "uart5")), /* RTS */ 549 + SUNXI_FUNCTION(0x3, "uart5"), /* RTS */ 550 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */ 580 551 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), 581 552 SUNXI_FUNCTION(0x0, "gpio_in"), 582 553 SUNXI_FUNCTION(0x1, "gpio_out"), 583 554 SUNXI_FUNCTION(0x2, "csi"), /* D3 */ 584 - SUNXI_FUNCTION(0x3, "uart5")), /* CTS */ 555 + SUNXI_FUNCTION(0x3, "uart5"), /* CTS */ 556 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */ 585 557 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), 586 558 SUNXI_FUNCTION(0x0, "gpio_in"), 587 559 SUNXI_FUNCTION(0x1, "gpio_out"), 588 560 SUNXI_FUNCTION(0x2, "csi"), /* D4 */ 589 - SUNXI_FUNCTION(0x3, "ts")), /* D0 */ 561 + SUNXI_FUNCTION(0x3, "ts"), /* D0 */ 562 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */ 590 563 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), 591 564 SUNXI_FUNCTION(0x0, "gpio_in"), 592 565 SUNXI_FUNCTION(0x1, "gpio_out"), 593 566 SUNXI_FUNCTION(0x2, "csi"), /* D5 */ 594 - SUNXI_FUNCTION(0x3, "ts")), /* D1 */ 567 + SUNXI_FUNCTION(0x3, "ts"), /* D1 */ 568 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */ 595 569 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), 596 570 SUNXI_FUNCTION(0x0, "gpio_in"), 597 571 SUNXI_FUNCTION(0x1, "gpio_out"), 598 572 SUNXI_FUNCTION(0x2, "csi"), /* D6 */ 599 - SUNXI_FUNCTION(0x3, "ts")), /* D2 */ 573 + SUNXI_FUNCTION(0x3, "ts"), /* D2 */ 574 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */ 600 575 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), 601 576 SUNXI_FUNCTION(0x0, "gpio_in"), 602 577 SUNXI_FUNCTION(0x1, "gpio_out"), 603 578 SUNXI_FUNCTION(0x2, "csi"), /* D7 */ 604 - SUNXI_FUNCTION(0x3, "ts")), /* D3 */ 579 + SUNXI_FUNCTION(0x3, "ts"), /* D3 */ 580 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */ 605 581 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), 606 582 SUNXI_FUNCTION(0x0, "gpio_in"), 607 583 SUNXI_FUNCTION(0x1, "gpio_out"), 608 584 SUNXI_FUNCTION(0x2, "csi"), /* D8 */ 609 - SUNXI_FUNCTION(0x3, "ts")), /* D4 */ 585 + SUNXI_FUNCTION(0x3, "ts"), /* D4 */ 586 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */ 610 587 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), 611 588 SUNXI_FUNCTION(0x0, "gpio_in"), 612 589 SUNXI_FUNCTION(0x1, "gpio_out"), 613 590 SUNXI_FUNCTION(0x2, "csi"), /* D9 */ 614 - SUNXI_FUNCTION(0x3, "ts")), /* D5 */ 591 + SUNXI_FUNCTION(0x3, "ts"), /* D5 */ 592 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */ 615 593 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), 616 594 SUNXI_FUNCTION(0x0, "gpio_in"), 617 595 SUNXI_FUNCTION(0x1, "gpio_out"), 618 596 SUNXI_FUNCTION(0x2, "csi"), /* D10 */ 619 - SUNXI_FUNCTION(0x3, "ts")), /* D6 */ 597 + SUNXI_FUNCTION(0x3, "ts"), /* D6 */ 598 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */ 620 599 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), 621 600 SUNXI_FUNCTION(0x0, "gpio_in"), 622 601 SUNXI_FUNCTION(0x1, "gpio_out"), 623 602 SUNXI_FUNCTION(0x2, "csi"), /* D11 */ 624 - SUNXI_FUNCTION(0x3, "ts")), /* D7 */ 603 + SUNXI_FUNCTION(0x3, "ts"), /* D7 */ 604 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */ 625 605 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), 626 606 SUNXI_FUNCTION(0x0, "gpio_in"), 627 607 SUNXI_FUNCTION(0x1, "gpio_out"), 628 - SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */ 608 + SUNXI_FUNCTION(0x2, "csi"), /* MIPI CSI MCLK */ 609 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */ 629 610 /* Hole */ 630 611 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 631 612 SUNXI_FUNCTION(0x0, "gpio_in"), ··· 678 625 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 679 626 SUNXI_FUNCTION(0x0, "gpio_in"), 680 627 SUNXI_FUNCTION(0x1, "gpio_out"), 681 - SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */ 628 + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 629 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */ 682 630 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 683 631 SUNXI_FUNCTION(0x0, "gpio_in"), 684 632 SUNXI_FUNCTION(0x1, "gpio_out"), 685 - SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */ 633 + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 634 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */ 686 635 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 687 636 SUNXI_FUNCTION(0x0, "gpio_in"), 688 637 SUNXI_FUNCTION(0x1, "gpio_out"), 689 - SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */ 638 + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ 639 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */ 690 640 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 691 641 SUNXI_FUNCTION(0x0, "gpio_in"), 692 642 SUNXI_FUNCTION(0x1, "gpio_out"), 693 - SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */ 643 + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ 644 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */ 694 645 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), 695 646 SUNXI_FUNCTION(0x0, "gpio_in"), 696 647 SUNXI_FUNCTION(0x1, "gpio_out"), 697 - SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */ 648 + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ 649 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */ 698 650 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), 699 651 SUNXI_FUNCTION(0x0, "gpio_in"), 700 652 SUNXI_FUNCTION(0x1, "gpio_out"), 701 - SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */ 653 + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ 654 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */ 702 655 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), 703 656 SUNXI_FUNCTION(0x0, "gpio_in"), 704 657 SUNXI_FUNCTION(0x1, "gpio_out"), 705 - SUNXI_FUNCTION(0x2, "uart2")), /* TX */ 658 + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ 659 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */ 706 660 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), 707 661 SUNXI_FUNCTION(0x0, "gpio_in"), 708 662 SUNXI_FUNCTION(0x1, "gpio_out"), 709 - SUNXI_FUNCTION(0x2, "uart2")), /* RX */ 663 + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ 664 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */ 710 665 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), 711 666 SUNXI_FUNCTION(0x0, "gpio_in"), 712 667 SUNXI_FUNCTION(0x1, "gpio_out"), 713 - SUNXI_FUNCTION(0x2, "uart2")), /* RTS */ 668 + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ 669 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */ 714 670 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), 715 671 SUNXI_FUNCTION(0x0, "gpio_in"), 716 672 SUNXI_FUNCTION(0x1, "gpio_out"), 717 - SUNXI_FUNCTION(0x2, "uart2")), /* CTS */ 673 + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ 674 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */ 718 675 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), 719 676 SUNXI_FUNCTION(0x0, "gpio_in"), 720 677 SUNXI_FUNCTION(0x1, "gpio_out"), 721 678 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ 722 - SUNXI_FUNCTION(0x3, "usb")), /* DP3 */ 679 + SUNXI_FUNCTION(0x3, "usb"), /* DP3 */ 680 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */ 723 681 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), 724 682 SUNXI_FUNCTION(0x0, "gpio_in"), 725 683 SUNXI_FUNCTION(0x1, "gpio_out"), 726 684 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ 727 - SUNXI_FUNCTION(0x3, "usb")), /* DM3 */ 685 + SUNXI_FUNCTION(0x3, "usb"), /* DM3 */ 686 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */ 728 687 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), 729 688 SUNXI_FUNCTION(0x0, "gpio_in"), 730 689 SUNXI_FUNCTION(0x1, "gpio_out"), 731 690 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ 732 - SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */ 691 + SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */ 692 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */ 733 693 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), 734 694 SUNXI_FUNCTION(0x0, "gpio_in"), 735 695 SUNXI_FUNCTION(0x1, "gpio_out"), 736 696 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 737 - SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */ 697 + SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */ 698 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */ 738 699 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), 739 700 SUNXI_FUNCTION(0x0, "gpio_in"), 740 701 SUNXI_FUNCTION(0x1, "gpio_out"), 741 702 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 742 - SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */ 703 + SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */ 704 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */ 743 705 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15), 744 706 SUNXI_FUNCTION(0x0, "gpio_in"), 745 707 SUNXI_FUNCTION(0x1, "gpio_out"), 746 708 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 747 - SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */ 709 + SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */ 710 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */ 748 711 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16), 749 712 SUNXI_FUNCTION(0x0, "gpio_in"), 750 713 SUNXI_FUNCTION(0x1, "gpio_out"), 751 714 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 752 - SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */ 715 + SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */ 716 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */ 753 717 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17), 754 718 SUNXI_FUNCTION(0x0, "gpio_in"), 755 719 SUNXI_FUNCTION(0x1, "gpio_out"), 756 - SUNXI_FUNCTION(0x2, "uart4")), /* TX */ 720 + SUNXI_FUNCTION(0x2, "uart4"), /* TX */ 721 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */ 757 722 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18), 758 723 SUNXI_FUNCTION(0x0, "gpio_in"), 759 724 SUNXI_FUNCTION(0x1, "gpio_out"), 760 - SUNXI_FUNCTION(0x2, "uart4")), /* RX */ 725 + SUNXI_FUNCTION(0x2, "uart4"), /* RX */ 726 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */ 761 727 /* Hole */ 762 728 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), 763 729 SUNXI_FUNCTION(0x0, "gpio_in"),