tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: rockchip: add support for rk3568
RK3568 SoCs have 5 gpio controllers, each gpio has 32 pins. GPIO supports
set iomux, pull, drive strength and schmitt.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20210319081441.368358-1-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
authored by
Jianqun Xu
and committed by
Linus Walleij
c0dadc0e
589b9b8b
+290
-2
+290
-2
drivers/pinctrl/pinctrl-rockchip.c
+290
-2
drivers/pinctrl/pinctrl-rockchip.c
···
63
63
RK3308,
64
64
RK3368,
65
65
RK3399,
66
+
RK3568,
66
67
};
68
+
69
+
70
+
/**
71
+
* Generate a bitmask for setting a value (v) with a write mask bit in hiword
72
+
* register 31:16 area.
73
+
*/
74
+
#define WRITE_MASK_VAL(h, l, v) \
75
+
(GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
67
76
68
77
/*
69
78
* Encode variants of iomux registers into a type variable
···
300
291
.pull_type[2] = pull2, \
301
292
.pull_type[3] = pull3, \
302
293
}
294
+
295
+
#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
296
+
{ \
297
+
.bank_num = ID, \
298
+
.pin = PIN, \
299
+
.func = FUNC, \
300
+
.route_offset = REG, \
301
+
.route_val = VAL, \
302
+
.route_location = FLAG, \
303
+
}
304
+
305
+
#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
306
+
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
307
+
308
+
#define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
309
+
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
310
+
311
+
#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
312
+
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
303
313
304
314
/**
305
315
* struct rockchip_mux_recalced_data: represent a pin iomux data.
···
1424
1396
},
1425
1397
};
1426
1398
1399
+
static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
1400
+
RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
1401
+
RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
1402
+
RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
1403
+
RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
1404
+
RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
1405
+
RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
1406
+
RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
1407
+
RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
1408
+
RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
1409
+
RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
1410
+
RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
1411
+
RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
1412
+
RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
1413
+
RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
1414
+
RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
1415
+
RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
1416
+
RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
1417
+
RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
1418
+
RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
1419
+
RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
1420
+
RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
1421
+
RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
1422
+
RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
1423
+
RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
1424
+
RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
1425
+
RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
1426
+
RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
1427
+
RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
1428
+
RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
1429
+
RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
1430
+
RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
1431
+
RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
1432
+
RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
1433
+
RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
1434
+
RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
1435
+
RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
1436
+
RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
1437
+
RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
1438
+
RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
1439
+
RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
1440
+
RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
1441
+
RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
1442
+
RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
1443
+
RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
1444
+
RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
1445
+
RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
1446
+
RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
1447
+
RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
1448
+
RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
1449
+
RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
1450
+
RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
1451
+
RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
1452
+
RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
1453
+
RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
1454
+
RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
1455
+
RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
1456
+
RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
1457
+
RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
1458
+
RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
1459
+
RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
1460
+
RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
1461
+
RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
1462
+
RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
1463
+
RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
1464
+
RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
1465
+
RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
1466
+
RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
1467
+
RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
1468
+
RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
1469
+
RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
1470
+
RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1471
+
RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1472
+
RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1473
+
RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1474
+
RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1475
+
RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1476
+
RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1477
+
RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1478
+
RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1479
+
RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1480
+
RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1481
+
RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1482
+
RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1483
+
RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1484
+
RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1485
+
RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1486
+
RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1487
+
RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1488
+
RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1489
+
RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1490
+
RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1491
+
RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1492
+
RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1493
+
};
1494
+
1427
1495
static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1428
1496
int mux, u32 *loc, u32 *reg, u32 *value)
1429
1497
{
···
2228
2104
*bit = (pin_num % 8) * 2;
2229
2105
}
2230
2106
2107
+
#define RK3568_PULL_PMU_OFFSET 0x20
2108
+
#define RK3568_PULL_GRF_OFFSET 0x80
2109
+
#define RK3568_PULL_BITS_PER_PIN 2
2110
+
#define RK3568_PULL_PINS_PER_REG 8
2111
+
#define RK3568_PULL_BANK_STRIDE 0x10
2112
+
2113
+
static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2114
+
int pin_num, struct regmap **regmap,
2115
+
int *reg, u8 *bit)
2116
+
{
2117
+
struct rockchip_pinctrl *info = bank->drvdata;
2118
+
2119
+
if (bank->bank_num == 0) {
2120
+
*regmap = info->regmap_pmu;
2121
+
*reg = RK3568_PULL_PMU_OFFSET;
2122
+
*reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
2123
+
*reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
2124
+
2125
+
*bit = pin_num % RK3568_PULL_PINS_PER_REG;
2126
+
*bit *= RK3568_PULL_BITS_PER_PIN;
2127
+
} else {
2128
+
*regmap = info->regmap_base;
2129
+
*reg = RK3568_PULL_GRF_OFFSET;
2130
+
*reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
2131
+
*reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
2132
+
2133
+
*bit = (pin_num % RK3568_PULL_PINS_PER_REG);
2134
+
*bit *= RK3568_PULL_BITS_PER_PIN;
2135
+
}
2136
+
}
2137
+
2138
+
#define RK3568_DRV_PMU_OFFSET 0x70
2139
+
#define RK3568_DRV_GRF_OFFSET 0x200
2140
+
#define RK3568_DRV_BITS_PER_PIN 8
2141
+
#define RK3568_DRV_PINS_PER_REG 2
2142
+
#define RK3568_DRV_BANK_STRIDE 0x40
2143
+
2144
+
static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2145
+
int pin_num, struct regmap **regmap,
2146
+
int *reg, u8 *bit)
2147
+
{
2148
+
struct rockchip_pinctrl *info = bank->drvdata;
2149
+
2150
+
/* The first 32 pins of the first bank are located in PMU */
2151
+
if (bank->bank_num == 0) {
2152
+
*regmap = info->regmap_pmu;
2153
+
*reg = RK3568_DRV_PMU_OFFSET;
2154
+
*reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2155
+
2156
+
*bit = pin_num % RK3568_DRV_PINS_PER_REG;
2157
+
*bit *= RK3568_DRV_BITS_PER_PIN;
2158
+
} else {
2159
+
*regmap = info->regmap_base;
2160
+
*reg = RK3568_DRV_GRF_OFFSET;
2161
+
*reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
2162
+
*reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2163
+
2164
+
*bit = (pin_num % RK3568_DRV_PINS_PER_REG);
2165
+
*bit *= RK3568_DRV_BITS_PER_PIN;
2166
+
}
2167
+
}
2168
+
2231
2169
static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
2232
2170
{ 2, 4, 8, 12, -1, -1, -1, -1 },
2233
2171
{ 3, 6, 9, 12, -1, -1, -1, -1 },
···
2390
2204
bank->bank_num, pin_num, strength);
2391
2205
2392
2206
ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
2207
+
if (ctrl->type == RK3568) {
2208
+
rmask_bits = RK3568_DRV_BITS_PER_PIN;
2209
+
ret = (1 << (strength + 1)) - 1;
2210
+
goto config;
2211
+
}
2393
2212
2394
2213
ret = -EINVAL;
2395
2214
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
···
2464
2273
return -EINVAL;
2465
2274
}
2466
2275
2276
+
config:
2467
2277
/* enable the write to the equivalent lower bits */
2468
2278
data = ((1 << rmask_bits) - 1) << (bit + 16);
2469
2279
rmask = data | (data >> 16);
···
2567
2375
case RK3308:
2568
2376
case RK3368:
2569
2377
case RK3399:
2378
+
case RK3568:
2570
2379
pull_type = bank->pull_type[pin_num / 8];
2571
2380
ret = -EINVAL;
2572
2381
for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
···
2576
2383
ret = i;
2577
2384
break;
2578
2385
}
2386
+
}
2387
+
/*
2388
+
* In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6,
2389
+
* where that pull up value becomes 3.
2390
+
*/
2391
+
if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2392
+
if (ret == 1)
2393
+
ret = 3;
2579
2394
}
2580
2395
2581
2396
if (ret < 0) {
···
2629
2428
return 0;
2630
2429
}
2631
2430
2431
+
#define RK3568_SCHMITT_BITS_PER_PIN 2
2432
+
#define RK3568_SCHMITT_PINS_PER_REG 8
2433
+
#define RK3568_SCHMITT_BANK_STRIDE 0x10
2434
+
#define RK3568_SCHMITT_GRF_OFFSET 0xc0
2435
+
#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
2436
+
2437
+
static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2438
+
int pin_num,
2439
+
struct regmap **regmap,
2440
+
int *reg, u8 *bit)
2441
+
{
2442
+
struct rockchip_pinctrl *info = bank->drvdata;
2443
+
2444
+
if (bank->bank_num == 0) {
2445
+
*regmap = info->regmap_pmu;
2446
+
*reg = RK3568_SCHMITT_PMUGRF_OFFSET;
2447
+
} else {
2448
+
*regmap = info->regmap_base;
2449
+
*reg = RK3568_SCHMITT_GRF_OFFSET;
2450
+
*reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
2451
+
}
2452
+
2453
+
*reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
2454
+
*bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
2455
+
*bit *= RK3568_SCHMITT_BITS_PER_PIN;
2456
+
2457
+
return 0;
2458
+
}
2459
+
2632
2460
static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2633
2461
{
2634
2462
struct rockchip_pinctrl *info = bank->drvdata;
···
2676
2446
return ret;
2677
2447
2678
2448
data >>= bit;
2449
+
switch (ctrl->type) {
2450
+
case RK3568:
2451
+
return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
2452
+
default:
2453
+
break;
2454
+
}
2455
+
2679
2456
return data & 0x1;
2680
2457
}
2681
2458
···
2704
2467
return ret;
2705
2468
2706
2469
/* enable the write to the equivalent lower bits */
2707
-
data = BIT(bit + 16) | (enable << bit);
2708
-
rmask = BIT(bit + 16) | BIT(bit);
2470
+
switch (ctrl->type) {
2471
+
case RK3568:
2472
+
data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
2473
+
rmask = data | (data >> 16);
2474
+
data |= ((enable ? 0x2 : 0x1) << bit);
2475
+
break;
2476
+
default:
2477
+
data = BIT(bit + 16) | (enable << bit);
2478
+
rmask = BIT(bit + 16) | BIT(bit);
2479
+
break;
2480
+
}
2709
2481
2710
2482
return regmap_update_bits(regmap, reg, rmask, data);
2711
2483
}
···
2888
2642
case RK3308:
2889
2643
case RK3368:
2890
2644
case RK3399:
2645
+
case RK3568:
2891
2646
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2892
2647
}
2893
2648
···
4460
4213
.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
4461
4214
};
4462
4215
4216
+
static struct rockchip_pin_bank rk3568_pin_banks[] = {
4217
+
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4218
+
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4219
+
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4220
+
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
4221
+
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
4222
+
IOMUX_WIDTH_4BIT,
4223
+
IOMUX_WIDTH_4BIT,
4224
+
IOMUX_WIDTH_4BIT),
4225
+
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
4226
+
IOMUX_WIDTH_4BIT,
4227
+
IOMUX_WIDTH_4BIT,
4228
+
IOMUX_WIDTH_4BIT),
4229
+
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
4230
+
IOMUX_WIDTH_4BIT,
4231
+
IOMUX_WIDTH_4BIT,
4232
+
IOMUX_WIDTH_4BIT),
4233
+
PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4234
+
IOMUX_WIDTH_4BIT,
4235
+
IOMUX_WIDTH_4BIT,
4236
+
IOMUX_WIDTH_4BIT),
4237
+
};
4238
+
4239
+
static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
4240
+
.pin_banks = rk3568_pin_banks,
4241
+
.nr_banks = ARRAY_SIZE(rk3568_pin_banks),
4242
+
.label = "RK3568-GPIO",
4243
+
.type = RK3568,
4244
+
.grf_mux_offset = 0x0,
4245
+
.pmu_mux_offset = 0x0,
4246
+
.grf_drv_offset = 0x0200,
4247
+
.pmu_drv_offset = 0x0070,
4248
+
.iomux_routes = rk3568_mux_route_data,
4249
+
.niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
4250
+
.pull_calc_reg = rk3568_calc_pull_reg_and_bit,
4251
+
.drv_calc_reg = rk3568_calc_drv_reg_and_bit,
4252
+
.schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
4253
+
};
4254
+
4463
4255
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4464
4256
{ .compatible = "rockchip,px30-pinctrl",
4465
4257
.data = &px30_pin_ctrl },
···
4528
4242
.data = &rk3368_pin_ctrl },
4529
4243
{ .compatible = "rockchip,rk3399-pinctrl",
4530
4244
.data = &rk3399_pin_ctrl },
4245
+
{ .compatible = "rockchip,rk3568-pinctrl",
4246
+
.data = &rk3568_pin_ctrl },
4531
4247
{},
4532
4248
};
4533
4249