drm/i915: Rename object_set_domain to object_set_to_gpu_domain

Now that the CPU and GTT domain operations are isolated to their own
functions, the previously general-purpose set_domain function is now used
only to set GPU domains. It also has no failure cases, which is important as
this eliminates any possible interruption of the computation of new object
domains and subsequent emmission of the flushing instructions into the ring.

Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

authored by

Keith Packard and committed by
Dave Airlie
c0d90829 e47c68e9

+12 -27
+12 -27
drivers/gpu/drm/i915/i915_gem.c
··· 33 34 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 35 36 - static int 37 - i915_gem_object_set_domain(struct drm_gem_object *obj, 38 - uint32_t read_domains, 39 - uint32_t write_domain); 40 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); 41 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); 42 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); ··· 1477 * MI_FLUSH 1478 * drm_agp_chipset_flush 1479 */ 1480 - static int 1481 - i915_gem_object_set_domain(struct drm_gem_object *obj, 1482 - uint32_t read_domains, 1483 - uint32_t write_domain) 1484 { 1485 struct drm_device *dev = obj->dev; 1486 struct drm_i915_gem_object *obj_priv = obj->driver_private; ··· 1540 obj->read_domains, obj->write_domain, 1541 dev->invalidate_domains, dev->flush_domains); 1542 #endif 1543 - return 0; 1544 } 1545 1546 /** ··· 2042 for (i = 0; i < args->buffer_count; i++) { 2043 struct drm_gem_object *obj = object_list[i]; 2044 2045 - /* make sure all previous memory operations have passed */ 2046 - ret = i915_gem_object_set_domain(obj, 2047 - obj->pending_read_domains, 2048 - obj->pending_write_domain); 2049 - if (ret) { 2050 - /* As we've partially updated domains on our buffers, 2051 - * we have to emit the flush we've accumulated 2052 - * before exiting, or we'll have broken the 2053 - * active/flushing/inactive invariants. 2054 - * 2055 - * We'll potentially have some things marked as 2056 - * being in write domains that they actually aren't, 2057 - * but that should be merely a minor performance loss. 2058 - */ 2059 - flush_domains = i915_gem_dev_set_domain(dev); 2060 - (void)i915_add_request(dev, flush_domains); 2061 - goto err; 2062 - } 2063 } 2064 2065 i915_verify_inactive(dev, __FILE__, __LINE__);
··· 33 34 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 35 36 + static void 37 + i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, 38 + uint32_t read_domains, 39 + uint32_t write_domain); 40 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); 41 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); 42 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); ··· 1477 * MI_FLUSH 1478 * drm_agp_chipset_flush 1479 */ 1480 + static void 1481 + i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, 1482 + uint32_t read_domains, 1483 + uint32_t write_domain) 1484 { 1485 struct drm_device *dev = obj->dev; 1486 struct drm_i915_gem_object *obj_priv = obj->driver_private; ··· 1540 obj->read_domains, obj->write_domain, 1541 dev->invalidate_domains, dev->flush_domains); 1542 #endif 1543 } 1544 1545 /** ··· 2043 for (i = 0; i < args->buffer_count; i++) { 2044 struct drm_gem_object *obj = object_list[i]; 2045 2046 + /* Compute new gpu domains and update invalidate/flushing */ 2047 + i915_gem_object_set_to_gpu_domain(obj, 2048 + obj->pending_read_domains, 2049 + obj->pending_write_domain); 2050 } 2051 2052 i915_verify_inactive(dev, __FILE__, __LINE__);