tjh.dev / kernel
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drm/amd/display: Use physical addressing for DMCUB on both dcn20/21

[Why]
CW0 and CW1 need to use physical addressing mode for dcn20 and dcn21.

The current code for dcn20 is using virtual.

[How]
We already program the DMCUB like this on dcn21 so we should just use
the same sequence for both.

Copy the dcn21 sequences into the dmjub_dcn20.c file and rename them.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Nicholas Kazlauskas and committed by
Alex Deucher c09d1d34 01c229d9

+45 -126
+44 -17
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
··· 54 54 55 55 /* Shared functions. */ 56 56 57 + static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in, 58 + uint64_t fb_base, 59 + uint64_t fb_offset, 60 + union dmub_addr *addr_out) 61 + { 62 + addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; 63 + } 64 + 57 65 void dmub_dcn20_reset(struct dmub_srv *dmub) 58 66 { 59 67 REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1); ··· 79 71 const struct dmub_window *cw0, 80 72 const struct dmub_window *cw1) 81 73 { 82 - REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 83 - REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x4, 84 - DMCUB_MEM_WRITE_SPACE, 0x4); 74 + union dmub_addr offset; 75 + uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset; 85 76 86 - REG_WRITE(DMCUB_REGION3_CW0_OFFSET, cw0->offset.u.low_part); 87 - REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, cw0->offset.u.high_part); 77 + REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 78 + REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3, 79 + DMCUB_MEM_WRITE_SPACE, 0x3); 80 + 81 + dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); 82 + 83 + REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 84 + REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 88 85 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 89 86 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 90 87 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 91 88 DMCUB_REGION3_CW0_ENABLE, 1); 92 89 93 - REG_WRITE(DMCUB_REGION3_CW1_OFFSET, cw1->offset.u.low_part); 94 - REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, cw1->offset.u.high_part); 90 + dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); 91 + 92 + REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 93 + REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 95 94 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 96 95 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 97 96 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, ··· 115 100 const struct dmub_window *cw5, 116 101 const struct dmub_window *cw6) 117 102 { 118 - REG_WRITE(DMCUB_REGION3_CW2_OFFSET, cw2->offset.u.low_part); 119 - REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, cw2->offset.u.high_part); 103 + union dmub_addr offset; 104 + uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset; 105 + 106 + dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset, &offset); 107 + 108 + REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part); 109 + REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part); 120 110 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base); 121 111 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0, 122 112 DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top, 123 113 DMCUB_REGION3_CW2_ENABLE, 1); 124 114 125 - REG_WRITE(DMCUB_REGION3_CW3_OFFSET, cw3->offset.u.low_part); 126 - REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, cw3->offset.u.high_part); 115 + dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset); 116 + 117 + REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); 118 + REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); 127 119 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); 128 120 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, 129 121 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, 130 122 DMCUB_REGION3_CW3_ENABLE, 1); 131 123 132 124 /* TODO: Move this to CW4. */ 125 + dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset); 133 126 134 - REG_WRITE(DMCUB_REGION4_OFFSET, cw4->offset.u.low_part); 135 - REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, cw4->offset.u.high_part); 127 + REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part); 128 + REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part); 136 129 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS, 137 130 cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE, 138 131 1); 139 132 140 - REG_WRITE(DMCUB_REGION3_CW5_OFFSET, cw5->offset.u.low_part); 141 - REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, cw5->offset.u.high_part); 133 + dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset); 134 + 135 + REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); 136 + REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); 142 137 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); 143 138 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, 144 139 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, 145 140 DMCUB_REGION3_CW5_ENABLE, 1); 146 141 147 - REG_WRITE(DMCUB_REGION3_CW6_OFFSET, cw6->offset.u.low_part); 148 - REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, cw6->offset.u.high_part); 142 + dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset); 143 + 144 + REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); 145 + REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); 149 146 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); 150 147 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, 151 148 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
+1 -96
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
··· 51 51 #undef DMUB_SF 52 52 }; 53 53 54 - static inline void dmub_dcn21_translate_addr(const union dmub_addr *addr_in, 55 - uint64_t fb_base, 56 - uint64_t fb_offset, 57 - union dmub_addr *addr_out) 58 - { 59 - addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; 60 - } 61 - 62 - void dmub_dcn21_backdoor_load(struct dmub_srv *dmub, 63 - const struct dmub_window *cw0, 64 - const struct dmub_window *cw1) 65 - { 66 - union dmub_addr offset; 67 - uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset; 68 - 69 - REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 70 - REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3, 71 - DMCUB_MEM_WRITE_SPACE, 0x3); 72 - 73 - dmub_dcn21_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); 74 - 75 - REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 76 - REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 77 - REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 78 - REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 79 - DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 80 - DMCUB_REGION3_CW0_ENABLE, 1); 81 - 82 - dmub_dcn21_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); 83 - 84 - REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 85 - REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 86 - REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 87 - REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 88 - DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 89 - DMCUB_REGION3_CW1_ENABLE, 1); 90 - 91 - REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 92 - 0x20); 93 - } 94 - 95 - void dmub_dcn21_setup_windows(struct dmub_srv *dmub, 96 - const struct dmub_window *cw2, 97 - const struct dmub_window *cw3, 98 - const struct dmub_window *cw4, 99 - const struct dmub_window *cw5, 100 - const struct dmub_window *cw6) 101 - { 102 - union dmub_addr offset; 103 - uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset; 104 - 105 - dmub_dcn21_translate_addr(&cw2->offset, fb_base, fb_offset, &offset); 106 - 107 - REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part); 108 - REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part); 109 - REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base); 110 - REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0, 111 - DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top, 112 - DMCUB_REGION3_CW2_ENABLE, 1); 113 - 114 - dmub_dcn21_translate_addr(&cw3->offset, fb_base, fb_offset, &offset); 115 - 116 - REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); 117 - REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); 118 - REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); 119 - REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, 120 - DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, 121 - DMCUB_REGION3_CW3_ENABLE, 1); 122 - 123 - /* TODO: Move this to CW4. */ 124 - dmub_dcn21_translate_addr(&cw4->offset, fb_base, fb_offset, &offset); 125 - 126 - REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part); 127 - REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part); 128 - REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS, 129 - cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE, 130 - 1); 131 - 132 - dmub_dcn21_translate_addr(&cw5->offset, fb_base, fb_offset, &offset); 133 - 134 - REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); 135 - REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); 136 - REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); 137 - REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, 138 - DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, 139 - DMCUB_REGION3_CW5_ENABLE, 1); 140 - 141 - dmub_dcn21_translate_addr(&cw6->offset, fb_base, fb_offset, &offset); 142 - 143 - REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); 144 - REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); 145 - REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); 146 - REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, 147 - DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, 148 - DMCUB_REGION3_CW6_ENABLE, 1); 149 - } 54 + /* Shared functions. */ 150 55 151 56 bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub) 152 57 {
-11
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
··· 34 34 35 35 /* Hardware functions. */ 36 36 37 - void dmub_dcn21_backdoor_load(struct dmub_srv *dmub, 38 - const struct dmub_window *cw0, 39 - const struct dmub_window *cw1); 40 - 41 - void dmub_dcn21_setup_windows(struct dmub_srv *dmub, 42 - const struct dmub_window *cw2, 43 - const struct dmub_window *cw3, 44 - const struct dmub_window *cw4, 45 - const struct dmub_window *cw5, 46 - const struct dmub_window *cw6); 47 - 48 37 bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub); 49 38 50 39 bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub);
-2
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
··· 84 84 if (asic == DMUB_ASIC_DCN21) { 85 85 dmub->regs = &dmub_srv_dcn21_regs; 86 86 87 - funcs->backdoor_load = dmub_dcn21_backdoor_load; 88 - funcs->setup_windows = dmub_dcn21_setup_windows; 89 87 funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done; 90 88 funcs->is_phy_init = dmub_dcn21_is_phy_init; 91 89 }