ARM: dts: aspeed: bletchley: Enable wdtrst1

Enable WDTRST1 external signal to send a reset pulse to peripherals while
BMC reset.

Signed-off-by: Potin Lai <[e-mail]>
Reviewed-by: Patrick Williams <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]
Signed-off-by: Joel Stanley <[e-mail]>

arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts

···
 		bias-disable;
 	};
 };
+
+&wdt1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdtrst1_default>;
+	aspeed,reset-type = "soc";
+	aspeed,external-signal;
+	aspeed,ext-push-pull;
+	aspeed,ext-active-high;
+	aspeed,ext-pulse-duration = <256>;
+};