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kernel
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linux
phy: qcom: qmp: move common bits definitions to common header
Move bit definitions for the common headers to the common phy-qcom-qmp.h
header.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-5-a463d0b57836@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Vinod Koul
c01e03f9
ef643d55
+26
-137
-21
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
-21
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
···
41
41
#include "phy-qcom-qmp-dp-phy-v5.h"
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#include "phy-qcom-qmp-dp-phy-v6.h"
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-
/* QPHY_SW_RESET bit */
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-
#define SW_RESET BIT(0)
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-
/* QPHY_POWER_DOWN_CONTROL */
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-
#define SW_PWRDN BIT(0)
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-
/* QPHY_START_CONTROL bits */
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-
#define SERDES_START BIT(0)
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-
#define PCS_START BIT(1)
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-
/* QPHY_PCS_STATUS bit */
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-
#define PHYSTATUS BIT(6)
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-
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/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
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/* DP PHY soft reset */
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#define SW_DPPHY_RESET BIT(0)
···
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/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
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#define USB3_MODE BIT(0) /* enables USB3 mode */
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#define DP_MODE BIT(1) /* enables DP mode */
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-
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/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
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#define ARCVR_DTCT_EN BIT(0)
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#define ALFPS_DTCT_EN BIT(1)
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-
#define ARCVR_DTCT_EVENT_SEL BIT(4)
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-
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/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
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-
#define IRQ_CLEAR BIT(0)
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-
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-
/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
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-
#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
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/* QPHY_V3_DP_COM_TYPEC_CTRL register bits */
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#define SW_PORTSELECT_VAL BIT(0)
+1
-9
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+1
-9
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
···
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#include "phy-qcom-qmp.h"
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-
/* QPHY_SW_RESET bit */
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-
#define SW_RESET BIT(0)
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-
/* QPHY_POWER_DOWN_CONTROL */
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-
#define SW_PWRDN BIT(0)
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-
#define REFCLK_DRV_DSBL BIT(1)
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/* QPHY_START_CONTROL bits */
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-
#define SERDES_START BIT(0)
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-
#define PCS_START BIT(1)
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#define PLL_READY_GATE_EN BIT(3)
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-
/* QPHY_PCS_STATUS bit */
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-
#define PHYSTATUS BIT(6)
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+
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/* QPHY_COM_PCS_READY_STATUS bit */
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#define PCS_READY BIT(0)
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-12
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
-12
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
···
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#include "phy-qcom-qmp-pcs-pcie-v6_20.h"
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#include "phy-qcom-qmp-pcie-qhp.h"
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-
/* QPHY_SW_RESET bit */
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-
#define SW_RESET BIT(0)
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-
/* QPHY_POWER_DOWN_CONTROL */
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-
#define SW_PWRDN BIT(0)
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-
#define REFCLK_DRV_DSBL BIT(1)
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-
/* QPHY_START_CONTROL bits */
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-
#define SERDES_START BIT(0)
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#define PCS_START BIT(1)
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-
/* QPHY_PCS_STATUS bit */
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-
#define PHYSTATUS BIT(6)
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-
#define PHYSTATUS_4_20 BIT(7)
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-
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#define PHY_INIT_COMPLETE_TIMEOUT 10000
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/* set of registers with offsets different per-PHY */
-7
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
-7
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
···
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#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
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-
/* QPHY_SW_RESET bit */
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-
#define SW_RESET BIT(0)
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-
/* QPHY_POWER_DOWN_CONTROL */
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-
#define SW_PWRDN BIT(0)
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-
/* QPHY_START_CONTROL bits */
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-
#define SERDES_START BIT(0)
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-
#define PCS_START BIT(1)
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/* QPHY_PCS_READY_STATUS bit */
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#define PCS_READY BIT(0)
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-21
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
-21
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
···
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#include "phy-qcom-qmp-dp-com-v3.h"
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-
/* QPHY_SW_RESET bit */
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-
#define SW_RESET BIT(0)
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-
/* QPHY_POWER_DOWN_CONTROL */
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-
#define SW_PWRDN BIT(0)
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-
/* QPHY_START_CONTROL bits */
35
-
#define SERDES_START BIT(0)
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-
#define PCS_START BIT(1)
37
-
/* QPHY_PCS_STATUS bit */
38
-
#define PHYSTATUS BIT(6)
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-
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/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
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/* DP PHY soft reset */
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#define SW_DPPHY_RESET BIT(0)
···
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/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
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#define USB3_MODE BIT(0) /* enables USB3 mode */
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#define DP_MODE BIT(1) /* enables DP mode */
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-
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-
/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
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-
#define ARCVR_DTCT_EN BIT(0)
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-
#define ALFPS_DTCT_EN BIT(1)
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-
#define ARCVR_DTCT_EVENT_SEL BIT(4)
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-
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-
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
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-
#define IRQ_CLEAR BIT(0)
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-
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-
/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
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-
#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
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#define PHY_INIT_COMPLETE_TIMEOUT 10000
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-35
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-35
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
···
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#include "phy-qcom-qmp-pcs-usb-v6.h"
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#include "phy-qcom-qmp-pcs-usb-v7.h"
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31
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-
/* QPHY_SW_RESET bit */
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-
#define SW_RESET BIT(0)
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-
/* QPHY_POWER_DOWN_CONTROL */
35
-
#define SW_PWRDN BIT(0)
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-
/* QPHY_START_CONTROL bits */
37
-
#define SERDES_START BIT(0)
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-
#define PCS_START BIT(1)
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-
/* QPHY_PCS_STATUS bit */
40
-
#define PHYSTATUS BIT(6)
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-
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-
/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
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-
/* DP PHY soft reset */
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-
#define SW_DPPHY_RESET BIT(0)
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-
/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
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-
#define SW_DPPHY_RESET_MUX BIT(1)
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-
/* USB3 PHY soft reset */
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#define SW_USB3PHY_RESET BIT(2)
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-
/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
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-
#define SW_USB3PHY_RESET_MUX BIT(3)
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-
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/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
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-
#define USB3_MODE BIT(0) /* enables USB3 mode */
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-
#define DP_MODE BIT(1) /* enables DP mode */
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-
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/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
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-
#define ARCVR_DTCT_EN BIT(0)
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-
#define ALFPS_DTCT_EN BIT(1)
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-
#define ARCVR_DTCT_EVENT_SEL BIT(4)
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-
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-
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
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-
#define IRQ_CLEAR BIT(0)
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-
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/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
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#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
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-
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#define PHY_INIT_COMPLETE_TIMEOUT 10000
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/* set of registers with offsets different per-PHY */
-32
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
-32
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
···
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#include "phy-qcom-qmp.h"
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#include "phy-qcom-qmp-pcs-misc-v3.h"
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-
/* QPHY_SW_RESET bit */
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-
#define SW_RESET BIT(0)
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-
/* QPHY_POWER_DOWN_CONTROL */
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-
#define SW_PWRDN BIT(0)
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-
/* QPHY_START_CONTROL bits */
36
-
#define SERDES_START BIT(0)
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-
#define PCS_START BIT(1)
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-
/* QPHY_PCS_STATUS bit */
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-
#define PHYSTATUS BIT(6)
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-
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/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
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-
/* DP PHY soft reset */
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-
#define SW_DPPHY_RESET BIT(0)
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-
/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
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-
#define SW_DPPHY_RESET_MUX BIT(1)
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-
/* USB3 PHY soft reset */
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-
#define SW_USB3PHY_RESET BIT(2)
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-
/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
49
-
#define SW_USB3PHY_RESET_MUX BIT(3)
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-
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/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
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-
#define USB3_MODE BIT(0) /* enables USB3 mode */
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-
#define DP_MODE BIT(1) /* enables DP mode */
54
-
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/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
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-
#define ARCVR_DTCT_EN BIT(0)
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#define ALFPS_DTCT_EN BIT(1)
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-
#define ARCVR_DTCT_EVENT_SEL BIT(4)
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-
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/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
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#define IRQ_CLEAR BIT(0)
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-
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31
#define PHY_INIT_COMPLETE_TIMEOUT 10000
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/* set of registers with offsets different per-PHY */
+25
drivers/phy/qualcomm/phy-qcom-qmp.h
+25
drivers/phy/qualcomm/phy-qcom-qmp.h
···
50
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#include "phy-qcom-qmp-pcs-v7.h"
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+
/* QPHY_SW_RESET bit */
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+
#define SW_RESET BIT(0)
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+
/* QPHY_POWER_DOWN_CONTROL */
56
+
#define SW_PWRDN BIT(0)
57
+
#define REFCLK_DRV_DSBL BIT(1) /* PCIe */
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+
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+
/* QPHY_START_CONTROL bits */
60
+
#define SERDES_START BIT(0)
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+
#define PCS_START BIT(1)
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+
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+
/* QPHY_PCS_STATUS bit */
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+
#define PHYSTATUS BIT(6)
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+
#define PHYSTATUS_4_20 BIT(7)
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+
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+
/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
68
+
#define ARCVR_DTCT_EN BIT(0)
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+
#define ALFPS_DTCT_EN BIT(1)
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+
#define ARCVR_DTCT_EVENT_SEL BIT(4)
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+
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+
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
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+
#define IRQ_CLEAR BIT(0)
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+
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+
/* QPHY_PCS_MISC_CLAMP_ENABLE register bits */
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+
#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
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+
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#endif