commit c01ac4b9440aa85374536075b1d61af961c3e567 · tjh.dev/kernel

+2

drivers/tty/n_gsm.c

··· 3157 3157 mutex_unlock(&gsm->mutex); 3158 3158 /* Now wipe the queues */ 3159 3159 tty_ldisc_flush(gsm->tty); 3160 + 3161 + guard(spinlock_irqsave)(&gsm->tx_lock); 3160 3162 list_for_each_entry_safe(txq, ntxq, &gsm->tx_ctrl_list, list) 3161 3163 kfree(txq); 3162 3164 INIT_LIST_HEAD(&gsm->tx_ctrl_list);

+15

drivers/tty/serial/imx.c

··· 762 762 763 763 imx_uart_writel(sport, USR1_RTSD, USR1); 764 764 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 765 + /* 766 + * Update sport->old_status here, so any follow-up calls to 767 + * imx_uart_mctrl_check() will be able to recognize that RTS 768 + * state changed since last imx_uart_mctrl_check() call. 769 + * 770 + * In case RTS has been detected as asserted here and later on 771 + * deasserted by the time imx_uart_mctrl_check() was called, 772 + * imx_uart_mctrl_check() can detect the RTS state change and 773 + * trigger uart_handle_cts_change() to unblock the port for 774 + * further TX transfers. 775 + */ 776 + if (usr1 & USR1_RTSS) 777 + sport->old_status |= TIOCM_CTS; 778 + else 779 + sport->old_status &= ~TIOCM_CTS; 765 780 uart_handle_cts_change(&sport->port, usr1); 766 781 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 767 782

+48 -55

drivers/tty/serial/qcom_geni_serial.c

··· 147 147 148 148 static void __qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport); 149 149 static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport); 150 + static int qcom_geni_serial_port_setup(struct uart_port *uport); 150 151 151 152 static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport) 152 153 { ··· 396 395 writel(c, uport->membase + SE_GENI_TX_FIFOn); 397 396 qcom_geni_serial_poll_tx_done(uport); 398 397 } 398 + 399 + static int qcom_geni_serial_poll_init(struct uart_port *uport) 400 + { 401 + struct qcom_geni_serial_port *port = to_dev_port(uport); 402 + int ret; 403 + 404 + if (!port->setup) { 405 + ret = qcom_geni_serial_port_setup(uport); 406 + if (ret) 407 + return ret; 408 + } 409 + 410 + if (!qcom_geni_serial_secondary_active(uport)) 411 + geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 412 + 413 + return 0; 414 + } 399 415 #endif 400 416 401 417 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE ··· 580 562 } 581 563 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 582 564 583 - static void handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) 565 + static void handle_rx_uart(struct uart_port *uport, u32 bytes) 584 566 { 585 567 struct qcom_geni_serial_port *port = to_dev_port(uport); 586 568 struct tty_port *tport = &uport->state->port; ··· 588 570 589 571 ret = tty_insert_flip_string(tport, port->rx_buf, bytes); 590 572 if (ret != bytes) { 591 - dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", 592 - __func__, ret, bytes); 593 - WARN_ON_ONCE(1); 573 + dev_err_ratelimited(uport->dev, "failed to push data (%d < %u)\n", 574 + ret, bytes); 594 575 } 595 576 uport->icount.rx += ret; 596 577 tty_flip_buffer_push(tport); ··· 804 787 static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport) 805 788 { 806 789 struct qcom_geni_serial_port *port = to_dev_port(uport); 790 + bool done; 807 791 808 792 if (!qcom_geni_serial_secondary_active(uport)) 809 793 return; 810 794 811 795 geni_se_cancel_s_cmd(&port->se); 812 - qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 813 - S_CMD_CANCEL_EN, true); 814 - 815 - if (qcom_geni_serial_secondary_active(uport)) 796 + done = qcom_geni_serial_poll_bit(uport, SE_DMA_RX_IRQ_STAT, 797 + RX_EOT, true); 798 + if (done) { 799 + writel(RX_EOT | RX_DMA_DONE, 800 + uport->membase + SE_DMA_RX_IRQ_CLR); 801 + } else { 816 802 qcom_geni_serial_abort_rx(uport); 803 + 804 + writel(1, uport->membase + SE_DMA_RX_FSM_RST); 805 + qcom_geni_serial_poll_bit(uport, SE_DMA_RX_IRQ_STAT, 806 + RX_RESET_DONE, true); 807 + writel(RX_RESET_DONE | RX_DMA_DONE, 808 + uport->membase + SE_DMA_RX_IRQ_CLR); 809 + } 817 810 818 811 if (port->rx_dma_addr) { 819 812 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, ··· 873 846 } 874 847 875 848 if (!drop) 876 - handle_rx_uart(uport, rx_in, drop); 849 + handle_rx_uart(uport, rx_in); 877 850 878 851 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 879 852 DMA_RX_BUF_SIZE, ··· 1123 1096 { 1124 1097 disable_irq(uport->irq); 1125 1098 1099 + uart_port_lock_irq(uport); 1126 1100 qcom_geni_serial_stop_tx(uport); 1127 1101 qcom_geni_serial_stop_rx(uport); 1128 1102 1129 1103 qcom_geni_serial_cancel_tx_cmd(uport); 1104 + uart_port_unlock_irq(uport); 1130 1105 } 1131 1106 1132 1107 static void qcom_geni_serial_flush_buffer(struct uart_port *uport) ··· 1181 1152 false, true, true); 1182 1153 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 1183 1154 geni_se_select_mode(&port->se, port->dev_data->mode); 1184 - qcom_geni_serial_start_rx(uport); 1185 1155 port->setup = true; 1186 1156 1187 1157 return 0; ··· 1196 1168 if (ret) 1197 1169 return ret; 1198 1170 } 1171 + 1172 + uart_port_lock_irq(uport); 1173 + qcom_geni_serial_start_rx(uport); 1174 + uart_port_unlock_irq(uport); 1175 + 1199 1176 enable_irq(uport->irq); 1200 1177 1201 1178 return 0; ··· 1286 1253 unsigned int avg_bw_core; 1287 1254 unsigned long timeout; 1288 1255 1289 - qcom_geni_serial_stop_rx(uport); 1290 1256 /* baud rate */ 1291 1257 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 1292 1258 ··· 1301 1269 dev_err(port->se.dev, 1302 1270 "Couldn't find suitable clock rate for %u\n", 1303 1271 baud * sampling_rate); 1304 - goto out_restart_rx; 1272 + return; 1305 1273 } 1306 1274 1307 1275 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n", ··· 1392 1360 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1393 1361 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1394 1362 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1395 - out_restart_rx: 1396 - qcom_geni_serial_start_rx(uport); 1397 1363 } 1398 1364 1399 1365 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE ··· 1612 1582 #ifdef CONFIG_CONSOLE_POLL 1613 1583 .poll_get_char = qcom_geni_serial_get_char, 1614 1584 .poll_put_char = qcom_geni_serial_poll_put_char, 1615 - .poll_init = qcom_geni_serial_port_setup, 1585 + .poll_init = qcom_geni_serial_poll_init, 1616 1586 #endif 1617 1587 .pm = qcom_geni_serial_pm, 1618 1588 }; ··· 1779 1749 uart_remove_one_port(drv, &port->uport); 1780 1750 } 1781 1751 1782 - static int qcom_geni_serial_sys_suspend(struct device *dev) 1752 + static int qcom_geni_serial_suspend(struct device *dev) 1783 1753 { 1784 1754 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1785 1755 struct uart_port *uport = &port->uport; ··· 1796 1766 return uart_suspend_port(private_data->drv, uport); 1797 1767 } 1798 1768 1799 - static int qcom_geni_serial_sys_resume(struct device *dev) 1769 + static int qcom_geni_serial_resume(struct device *dev) 1800 1770 { 1801 1771 int ret; 1802 1772 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); ··· 1807 1777 if (uart_console(uport)) { 1808 1778 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 1809 1779 geni_icc_set_bw(&port->se); 1810 - } 1811 - return ret; 1812 - } 1813 - 1814 - static int qcom_geni_serial_sys_hib_resume(struct device *dev) 1815 - { 1816 - int ret = 0; 1817 - struct uart_port *uport; 1818 - struct qcom_geni_private_data *private_data; 1819 - struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1820 - 1821 - uport = &port->uport; 1822 - private_data = uport->private_data; 1823 - 1824 - if (uart_console(uport)) { 1825 - geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 1826 - geni_icc_set_bw(&port->se); 1827 - ret = uart_resume_port(private_data->drv, uport); 1828 - /* 1829 - * For hibernation usecase clients for 1830 - * console UART won't call port setup during restore, 1831 - * hence call port setup for console uart. 1832 - */ 1833 - qcom_geni_serial_port_setup(uport); 1834 - } else { 1835 - /* 1836 - * Peripheral register settings are lost during hibernation. 1837 - * Update setup flag such that port setup happens again 1838 - * during next session. Clients of HS-UART will close and 1839 - * open the port during hibernation. 1840 - */ 1841 - port->setup = false; 1842 1780 } 1843 1781 return ret; 1844 1782 } ··· 1822 1824 }; 1823 1825 1824 1826 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1825 - .suspend = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1826 - .resume = pm_sleep_ptr(qcom_geni_serial_sys_resume), 1827 - .freeze = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1828 - .poweroff = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1829 - .restore = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), 1830 - .thaw = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), 1827 + SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_suspend, qcom_geni_serial_resume) 1831 1828 }; 1832 1829 1833 1830 static const struct of_device_id qcom_geni_serial_match_table[] = {

+1 -1

drivers/tty/vt/vt.c

··· 4726 4726 return -EINVAL; 4727 4727 4728 4728 if (op->data) { 4729 - font.data = kvmalloc(max_font_size, GFP_KERNEL); 4729 + font.data = kvzalloc(max_font_size, GFP_KERNEL); 4730 4730 if (!font.data) 4731 4731 return -ENOMEM; 4732 4732 } else

+1 -1

include/linux/soc/qcom/geni-se.h

··· 258 258 #define RX_DMA_PARITY_ERR BIT(5) 259 259 #define RX_DMA_BREAK GENMASK(8, 7) 260 260 #define RX_GENI_GP_IRQ GENMASK(10, 5) 261 - #define RX_GENI_CANCEL_IRQ BIT(11) 262 261 #define RX_GENI_GP_IRQ_EXT GENMASK(13, 12) 262 + #define RX_GENI_CANCEL_IRQ BIT(14) 263 263 264 264 /* SE_HW_PARAM_0 fields */ 265 265 #define TX_FIFO_WIDTH_MSK GENMASK(29, 24)