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ARM: hardware: fix endian-ness in <hardware/coresight.h>
The <hardware/coresight.h> needs to take into account the endian-ness
of the processor when reading and writing data, so change to using
the readl/writel relaxed variants from the raw ones.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
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arch/arm/include/asm/hardware/coresight.h
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arch/arm/include/asm/hardware/coresight.h
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#define TRACER_TIMEOUT 10000
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#define etm_writel(t, v, x) \
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(__raw_writel((v), (t)->etm_regs + (x)))
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#define etm_readl(t, x) (__raw_readl((t)->etm_regs + (x)))
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(writel_relaxed((v), (t)->etm_regs + (x)))
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#define etm_readl(t, x) (readl_relaxed((t)->etm_regs + (x)))
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/* CoreSight Management Registers */
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#define CSMR_LOCKACCESS 0xfb0
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#define ETBFF_TRIGFL BIT(10)
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#define etb_writel(t, v, x) \
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(__raw_writel((v), (t)->etb_regs + (x)))
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#define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x)))
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(writel_relaxed((v), (t)->etb_regs + (x)))
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#define etb_readl(t, x) (readl_relaxed((t)->etb_regs + (x)))
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#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)
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#define etm_unlock(t) \