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clk: shmobile: document DIV6 clock parent bindings

Describes how to specify the parents for clocks with EXSRC bits.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Ulrich Hecht and committed by
Geert Uytterhoeven
bfadcadf c6d67fb0

+12 -6
+12 -6
Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
··· 7 7 Required Properties: 8 8 9 9 - compatible: Must be one of the following 10 + - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks 11 + - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks 10 12 - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks 11 13 - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks 14 + - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks 12 15 - "renesas,cpg-div6-clock" for generic DIV6 clocks 13 16 - reg: Base address and length of the memory resource used by the DIV6 clock 14 - - clocks: Reference to the parent clock 17 + - clocks: Reference to the parent clock(s); either one, four, or eight 18 + clocks must be specified. For clocks with multiple parents, invalid 19 + settings must be specified as "<0>". 15 20 - #clock-cells: Must be 0 16 21 - clock-output-names: The name of the clock as a free-form string 17 22 ··· 24 19 Example 25 20 ------- 26 21 27 - sd2_clk: sd2_clk@e6150078 { 28 - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; 29 - reg = <0 0xe6150078 0 4>; 30 - clocks = <&pll1_div2_clk>; 22 + sdhi2_clk: sdhi2_clk@e615007c { 23 + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 24 + reg = <0 0xe615007c 0 4>; 25 + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 26 + <0>, <&extal2_clk>; 31 27 #clock-cells = <0>; 32 - clock-output-names = "sd2"; 28 + clock-output-names = "sdhi2ck"; 33 29 };