Merge branch 'for-5.0' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-5.1

+18 -18

drivers/spi/spi-dw.c

··· 53 53 if (!buf) 54 54 return 0; 55 55 56 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 56 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 57 57 "%s registers:\n", dev_name(&dws->master->dev)); 58 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 58 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 59 59 "=================================\n"); 60 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 60 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 61 61 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); 62 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 62 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 63 63 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); 64 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 64 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 65 65 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); 66 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 66 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 67 67 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER)); 68 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 68 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 69 69 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); 70 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 70 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 71 71 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); 72 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 72 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 73 73 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); 74 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 74 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 75 75 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); 76 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 76 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 77 77 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR)); 78 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 78 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 79 79 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR)); 80 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 80 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 81 81 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR)); 82 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 82 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 83 83 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR)); 84 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 84 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 85 85 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR)); 86 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 86 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 87 87 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR)); 88 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 88 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 89 89 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR)); 90 - len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 90 + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, 91 91 "=================================\n"); 92 92 93 93 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);

+1 -1

drivers/spi/spi-fsl-dspi.c

··· 67 67 #define SPI_SR 0x2c 68 68 #define SPI_SR_EOQF 0x10000000 69 69 #define SPI_SR_TCFQF 0x80000000 70 - #define SPI_SR_CLEAR 0xdaad0000 70 + #define SPI_SR_CLEAR 0x9aaf0000 71 71 72 72 #define SPI_RSER_TFFFE BIT(25) 73 73 #define SPI_RSER_TFFFD BIT(24)

+48 -44

drivers/spi/spi-fsl-lpspi.c

··· 48 48 #define CR_RTF BIT(8) 49 49 #define CR_RST BIT(1) 50 50 #define CR_MEN BIT(0) 51 + #define SR_MBF BIT(24) 51 52 #define SR_TCF BIT(10) 53 + #define SR_FCF BIT(9) 52 54 #define SR_RDF BIT(1) 53 55 #define SR_TDF BIT(0) 54 56 #define IER_TCIE BIT(10) 57 + #define IER_FCIE BIT(9) 55 58 #define IER_RDIE BIT(1) 56 59 #define IER_TDIE BIT(0) 57 60 #define CFGR1_PCSCFG BIT(27) ··· 62 59 #define CFGR1_PCSPOL BIT(8) 63 60 #define CFGR1_NOSTALL BIT(3) 64 61 #define CFGR1_MASTER BIT(0) 62 + #define FSR_RXCOUNT (BIT(16)|BIT(17)|BIT(18)) 65 63 #define RSR_RXEMPTY BIT(1) 66 64 #define TCR_CPOL BIT(31) 67 65 #define TCR_CPHA BIT(30) ··· 165 161 return 0; 166 162 } 167 163 168 - static int fsl_lpspi_txfifo_empty(struct fsl_lpspi_data *fsl_lpspi) 169 - { 170 - u32 txcnt; 171 - unsigned long orig_jiffies = jiffies; 172 - 173 - do { 174 - txcnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff; 175 - 176 - if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 177 - dev_dbg(fsl_lpspi->dev, "txfifo empty timeout\n"); 178 - return -ETIMEDOUT; 179 - } 180 - cond_resched(); 181 - 182 - } while (txcnt); 183 - 184 - return 0; 185 - } 186 - 187 164 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi) 188 165 { 189 166 u8 txfifo_cnt; 167 + u32 temp; 190 168 191 169 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff; 192 170 ··· 179 193 txfifo_cnt++; 180 194 } 181 195 182 - if (!fsl_lpspi->remain && (txfifo_cnt < fsl_lpspi->txfifosize)) 183 - writel(0, fsl_lpspi->base + IMX7ULP_TDR); 184 - else 196 + if (txfifo_cnt < fsl_lpspi->txfifosize) { 197 + if (!fsl_lpspi->is_slave) { 198 + temp = readl(fsl_lpspi->base + IMX7ULP_TCR); 199 + temp &= ~TCR_CONTC; 200 + writel(temp, fsl_lpspi->base + IMX7ULP_TCR); 201 + } 202 + 203 + fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE); 204 + } else 185 205 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE); 186 206 } 187 207 ··· 267 275 { 268 276 u32 temp; 269 277 int ret; 270 - 271 - temp = CR_RST; 272 - writel(temp, fsl_lpspi->base + IMX7ULP_CR); 273 - writel(0, fsl_lpspi->base + IMX7ULP_CR); 274 278 275 279 if (!fsl_lpspi->is_slave) { 276 280 ret = fsl_lpspi_set_bitrate(fsl_lpspi); ··· 358 370 return 0; 359 371 } 360 372 373 + static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi) 374 + { 375 + u32 temp; 376 + 377 + /* Disable all interrupt */ 378 + fsl_lpspi_intctrl(fsl_lpspi, 0); 379 + 380 + /* W1C for all flags in SR */ 381 + temp = 0x3F << 8; 382 + writel(temp, fsl_lpspi->base + IMX7ULP_SR); 383 + 384 + /* Clear FIFO and disable module */ 385 + temp = CR_RRF | CR_RTF; 386 + writel(temp, fsl_lpspi->base + IMX7ULP_CR); 387 + 388 + return 0; 389 + } 390 + 361 391 static int fsl_lpspi_transfer_one(struct spi_controller *controller, 362 392 struct spi_device *spi, 363 393 struct spi_transfer *t) ··· 397 391 if (ret) 398 392 return ret; 399 393 400 - ret = fsl_lpspi_txfifo_empty(fsl_lpspi); 401 - if (ret) 402 - return ret; 403 - 404 - fsl_lpspi_read_rx_fifo(fsl_lpspi); 394 + fsl_lpspi_reset(fsl_lpspi); 405 395 406 396 return 0; 407 397 } ··· 410 408 struct spi_device *spi = msg->spi; 411 409 struct spi_transfer *xfer; 412 410 bool is_first_xfer = true; 413 - u32 temp; 414 411 int ret = 0; 415 412 416 413 msg->status = 0; ··· 429 428 } 430 429 431 430 complete: 432 - if (!fsl_lpspi->is_slave) { 433 - /* de-assert SS, then finalize current message */ 434 - temp = readl(fsl_lpspi->base + IMX7ULP_TCR); 435 - temp &= ~TCR_CONTC; 436 - writel(temp, fsl_lpspi->base + IMX7ULP_TCR); 437 - } 438 - 439 431 msg->status = ret; 440 432 spi_finalize_current_message(controller); 441 433 ··· 437 443 438 444 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id) 439 445 { 446 + u32 temp_SR, temp_IER; 440 447 struct fsl_lpspi_data *fsl_lpspi = dev_id; 441 - u32 temp; 442 448 449 + temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER); 443 450 fsl_lpspi_intctrl(fsl_lpspi, 0); 444 - temp = readl(fsl_lpspi->base + IMX7ULP_SR); 451 + temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR); 445 452 446 453 fsl_lpspi_read_rx_fifo(fsl_lpspi); 447 454 448 - if (temp & SR_TDF) { 455 + if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) { 449 456 fsl_lpspi_write_tx_fifo(fsl_lpspi); 457 + return IRQ_HANDLED; 458 + } 450 459 451 - if (!fsl_lpspi->remain) 460 + if (temp_SR & SR_MBF || 461 + readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_RXCOUNT) { 462 + writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); 463 + fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE); 464 + return IRQ_HANDLED; 465 + } 466 + 467 + if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) { 468 + writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); 452 469 complete(&fsl_lpspi->xfer_done); 453 - 454 470 return IRQ_HANDLED; 455 471 } 456 472

+2 -1

drivers/spi/spi-mem.c

··· 537 537 /** 538 538 * spi_mem_dirmap_destroy() - Destroy a direct mapping descriptor 539 539 * @desc: the direct mapping descriptor to destroy 540 - * @info: direct mapping information 541 540 * 542 541 * This function destroys a direct mapping descriptor previously created by 543 542 * spi_mem_dirmap_create(). ··· 547 548 548 549 if (!desc->nodirmap && ctlr->mem_ops && ctlr->mem_ops->dirmap_destroy) 549 550 ctlr->mem_ops->dirmap_destroy(desc); 551 + 552 + kfree(desc); 550 553 } 551 554 EXPORT_SYMBOL_GPL(spi_mem_dirmap_destroy); 552 555

+2 -1

drivers/spi/spi-npcm-pspi.c

··· 465 465 466 466 static int npcm_pspi_remove(struct platform_device *pdev) 467 467 { 468 - struct npcm_pspi *priv = platform_get_drvdata(pdev); 468 + struct spi_master *master = platform_get_drvdata(pdev); 469 + struct npcm_pspi *priv = spi_master_get_devdata(master); 469 470 470 471 npcm_pspi_reset_hw(priv); 471 472 clk_disable_unprepare(priv->clk);

+2 -2

drivers/spi/spi-omap2-mcspi.c

··· 623 623 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; 624 624 cfg.src_addr_width = width; 625 625 cfg.dst_addr_width = width; 626 - cfg.src_maxburst = es; 627 - cfg.dst_maxburst = es; 626 + cfg.src_maxburst = 1; 627 + cfg.dst_maxburst = 1; 628 628 629 629 rx = xfer->rx_buf; 630 630 tx = xfer->tx_buf;

+1

drivers/spi/spi-pxa2xx.c

··· 1696 1696 platform_info->enable_dma = false; 1697 1697 } else { 1698 1698 controller->can_dma = pxa2xx_spi_can_dma; 1699 + controller->max_dma_len = MAX_DMA_LEN; 1699 1700 } 1700 1701 } 1701 1702

+6 -4

drivers/spi/spi-sprd.c

··· 403 403 { 404 404 struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller); 405 405 u32 trans_len = ss->trans_len, len; 406 - int ret, write_size = 0; 406 + int ret, write_size = 0, read_size = 0; 407 407 408 408 while (trans_len) { 409 409 len = trans_len > SPRD_SPI_FIFO_SIZE ? SPRD_SPI_FIFO_SIZE : ··· 439 439 goto complete; 440 440 441 441 if (ss->trans_mode & SPRD_SPI_RX_MODE) 442 - ss->read_bufs(ss, len); 442 + read_size += ss->read_bufs(ss, len); 443 443 444 444 trans_len -= len; 445 445 } 446 446 447 - ret = write_size; 448 - 447 + if (ss->trans_mode & SPRD_SPI_TX_MODE) 448 + ret = write_size; 449 + else 450 + ret = read_size; 449 451 complete: 450 452 sprd_spi_enter_idle(ss); 451 453

+3 -3

drivers/spi/spi-ti-qspi.c

··· 490 490 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG); 491 491 if (qspi->ctrl_base) { 492 492 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, 493 - MEM_CS_EN(spi->chip_select), 494 - MEM_CS_MASK); 493 + MEM_CS_MASK, 494 + MEM_CS_EN(spi->chip_select)); 495 495 } 496 496 qspi->mmap_enabled = true; 497 497 } ··· 503 503 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG); 504 504 if (qspi->ctrl_base) 505 505 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, 506 - 0, MEM_CS_MASK); 506 + MEM_CS_MASK, 0); 507 507 qspi->mmap_enabled = false; 508 508 } 509 509

+6

drivers/spi/spi-topcliff-pch.c

··· 1008 1008 1009 1009 /* RX */ 1010 1010 dma->sg_rx_p = kcalloc(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC); 1011 + if (!dma->sg_rx_p) 1012 + return; 1013 + 1011 1014 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */ 1012 1015 /* offset, length setting */ 1013 1016 sg = dma->sg_rx_p; ··· 1071 1068 } 1072 1069 1073 1070 dma->sg_tx_p = kcalloc(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC); 1071 + if (!dma->sg_tx_p) 1072 + return; 1073 + 1074 1074 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */ 1075 1075 /* offset, length setting */ 1076 1076 sg = dma->sg_tx_p;