ARM: dts: omap5: add SHA crypto accelerator node

Add the single available SHA crypto accelerator device for OMAP5 SoC.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

authored by Tero Kristo and committed by Tony Lindgren bf755817 4b9882ae

+28
+28
arch/arm/boot/dts/omap5.dtsi
··· 305 305 }; 306 306 }; 307 307 308 + sham_target: target-module@4b100000 { 309 + compatible = "ti,sysc-omap3-sham", "ti,sysc"; 310 + reg = <0x4b100100 0x4>, 311 + <0x4b100110 0x4>, 312 + <0x4b100114 0x4>; 313 + reg-names = "rev", "sysc", "syss"; 314 + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 315 + SYSC_OMAP2_AUTOIDLE)>; 316 + ti,sysc-sidle = <SYSC_IDLE_FORCE>, 317 + <SYSC_IDLE_NO>, 318 + <SYSC_IDLE_SMART>; 319 + ti,syss-mask = <1>; 320 + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 321 + clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>; 322 + clock-names = "fck"; 323 + #address-cells = <1>; 324 + #size-cells = <1>; 325 + ranges = <0x0 0x4b100000 0x1000>; 326 + 327 + sham: sham@0 { 328 + compatible = "ti,omap4-sham"; 329 + reg = <0 0x300>; 330 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 331 + dmas = <&sdma 119>; 332 + dma-names = "rx"; 333 + }; 334 + }; 335 + 308 336 bandgap: bandgap@4a0021e0 { 309 337 reg = <0x4a0021e0 0xc 310 338 0x4a00232c 0xc