tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: zynq: clkc: Remove various instances of an unused variable 'clk'
Fixes the following W=1 kernel build warning(s):
drivers/clk/zynq/clkc.c: In function ‘zynq_clk_register_fclk’:
drivers/clk/zynq/clkc.c:106:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable]
drivers/clk/zynq/clkc.c: In function ‘zynq_clk_register_periph_clk’:
drivers/clk/zynq/clkc.c:179:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable]
drivers/clk/zynq/clkc.c: In function ‘zynq_clk_setup’:
drivers/clk/zynq/clkc.c:220:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable]
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-21-lee.jones@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Lee Jones
and committed by
Stephen Boyd
bf2244ba
0c1d46d3
+35
-38
+35
-38
drivers/clk/zynq/clkc.c
+35
-38
drivers/clk/zynq/clkc.c
···
103
103
const char *clk_name, void __iomem *fclk_ctrl_reg,
104
104
const char **parents, int enable)
105
105
{
106
-
struct clk *clk;
107
106
u32 enable_reg;
108
107
char *mux_name;
109
108
char *div0_name;
···
130
131
if (!div1_name)
131
132
goto err_div1_name;
132
133
133
-
clk = clk_register_mux(NULL, mux_name, parents, 4,
134
+
clk_register_mux(NULL, mux_name, parents, 4,
134
135
CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
135
136
fclk_lock);
136
137
137
-
clk = clk_register_divider(NULL, div0_name, mux_name,
138
+
clk_register_divider(NULL, div0_name, mux_name,
138
139
0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
139
140
CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
140
141
141
-
clk = clk_register_divider(NULL, div1_name, div0_name,
142
+
clk_register_divider(NULL, div1_name, div0_name,
142
143
CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
143
144
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
144
145
fclk_lock);
···
175
176
const char *clk_name1, void __iomem *clk_ctrl,
176
177
const char **parents, unsigned int two_gates)
177
178
{
178
-
struct clk *clk;
179
179
char *mux_name;
180
180
char *div_name;
181
181
spinlock_t *lock;
···
187
189
mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
188
190
div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
189
191
190
-
clk = clk_register_mux(NULL, mux_name, parents, 4,
192
+
clk_register_mux(NULL, mux_name, parents, 4,
191
193
CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
192
194
193
-
clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
195
+
clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
194
196
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
195
197
196
198
clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
···
215
217
int i;
216
218
u32 tmp;
217
219
int ret;
218
-
struct clk *clk;
219
220
char *clk_name;
220
221
unsigned int fclk_enable = 0;
221
222
const char *clk_output_name[clk_max];
···
254
257
ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp);
255
258
256
259
/* PLLs */
257
-
clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
260
+
clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
258
261
SLCR_PLL_STATUS, 0, &armpll_lock);
259
262
clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
260
263
armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
261
264
SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
262
265
263
-
clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
266
+
clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
264
267
SLCR_PLL_STATUS, 1, &ddrpll_lock);
265
268
clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
266
269
ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
267
270
SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
268
271
269
-
clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
272
+
clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
270
273
SLCR_PLL_STATUS, 2, &iopll_lock);
271
274
clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
272
275
iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
···
274
277
275
278
/* CPU clocks */
276
279
tmp = readl(SLCR_621_TRUE) & 1;
277
-
clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
280
+
clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
278
281
CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
279
282
&armclk_lock);
280
-
clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
283
+
clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
281
284
SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
282
285
CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
283
286
···
285
288
"cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
286
289
SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
287
290
288
-
clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
291
+
clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
289
292
1, 2);
290
293
clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
291
294
"cpu_3or2x_div", CLK_IGNORE_UNUSED,
292
295
SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
293
296
294
-
clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
297
+
clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
295
298
2 + tmp);
296
299
clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
297
300
"cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
298
301
26, 0, &armclk_lock);
299
302
clk_prepare_enable(clks[cpu_2x]);
300
303
301
-
clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
304
+
clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
302
305
4 + 2 * tmp);
303
306
clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
304
307
"cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
···
321
324
&swdtclk_lock);
322
325
323
326
/* DDR clocks */
324
-
clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
327
+
clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
325
328
SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
326
329
CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
327
330
clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
328
331
"ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
329
332
clk_prepare_enable(clks[ddr2x]);
330
-
clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
333
+
clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
331
334
SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
332
335
CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
333
336
clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
334
337
"ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
335
338
clk_prepare_enable(clks[ddr3x]);
336
339
337
-
clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
340
+
clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
338
341
SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
339
342
CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
340
-
clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
343
+
clk_register_divider(NULL, "dci_div1", "dci_div0",
341
344
CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
342
345
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
343
346
&dciclk_lock);
···
382
385
gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
383
386
idx);
384
387
}
385
-
clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
388
+
clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
386
389
CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
387
390
&gem0clk_lock);
388
-
clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
391
+
clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
389
392
SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
390
393
CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
391
-
clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
394
+
clk_register_divider(NULL, "gem0_div1", "gem0_div0",
392
395
CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
393
396
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
394
397
&gem0clk_lock);
395
-
clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
398
+
clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
396
399
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
397
400
SLCR_GEM0_CLK_CTRL, 6, 1, 0,
398
401
&gem0clk_lock);
···
407
410
gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
408
411
idx);
409
412
}
410
-
clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
413
+
clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
411
414
CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
412
415
&gem1clk_lock);
413
-
clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
416
+
clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
414
417
SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
415
418
CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
416
-
clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
419
+
clk_register_divider(NULL, "gem1_div1", "gem1_div0",
417
420
CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
418
421
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
419
422
&gem1clk_lock);
420
-
clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
423
+
clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
421
424
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
422
425
SLCR_GEM1_CLK_CTRL, 6, 1, 0,
423
426
&gem1clk_lock);
···
439
442
can_mio_mux_parents[i] = dummy_nm;
440
443
}
441
444
kfree(clk_name);
442
-
clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
445
+
clk_register_mux(NULL, "can_mux", periph_parents, 4,
443
446
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
444
447
&canclk_lock);
445
-
clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
448
+
clk_register_divider(NULL, "can_div0", "can_mux", 0,
446
449
SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
447
450
CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
448
-
clk = clk_register_divider(NULL, "can_div1", "can_div0",
451
+
clk_register_divider(NULL, "can_div1", "can_div0",
449
452
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
450
453
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
451
454
&canclk_lock);
452
-
clk = clk_register_gate(NULL, "can0_gate", "can_div1",
455
+
clk_register_gate(NULL, "can0_gate", "can_div1",
453
456
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
454
457
&canclk_lock);
455
-
clk = clk_register_gate(NULL, "can1_gate", "can_div1",
458
+
clk_register_gate(NULL, "can1_gate", "can_div1",
456
459
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
457
460
&canclk_lock);
458
-
clk = clk_register_mux(NULL, "can0_mio_mux",
461
+
clk_register_mux(NULL, "can0_mio_mux",
459
462
can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
460
463
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
461
464
&canmioclk_lock);
462
-
clk = clk_register_mux(NULL, "can1_mio_mux",
465
+
clk_register_mux(NULL, "can1_mio_mux",
463
466
can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
464
467
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
465
468
0, &canmioclk_lock);
···
479
482
dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
480
483
idx);
481
484
}
482
-
clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
485
+
clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
483
486
CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
484
487
&dbgclk_lock);
485
-
clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
488
+
clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
486
489
SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
487
490
CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
488
-
clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
491
+
clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
489
492
CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
490
493
&dbgclk_lock);
491
494
clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],