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kernel
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linux
clk: mstar: MStar/SigmaStar MPLL driver
This adds a basic driver for the MPLL block found in MStar/SigmaStar
ARMv7 SoCs.
Currently this driver is only good for calculating the rates of it's
outputs and the actual configuration must be done before the kernel
boots. Usually this is done even before u-boot starts.
This driver targets the MPLL block found in the MSC313/MSC313E but
there is no documentation this chip so the register descriptions for
the another MStar chip the MST786 were used as they seem to match.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20210211052206.2955988-5-daniel@0x0f.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Daniel Palmer
and committed by
Stephen Boyd
bef7a78d
0b9266d2
+169
+1
MAINTAINERS
+1
MAINTAINERS
···
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F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml
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F: arch/arm/boot/dts/mstar-*
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F: arch/arm/mach-mstar/
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F: drivers/clk/mstar/
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F: drivers/gpio/gpio-msc313.c
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F: include/dt-bindings/clock/mstar-*
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F: include/dt-bindings/gpio/msc313-gpio.h
+1
drivers/clk/Kconfig
+1
drivers/clk/Kconfig
···
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source "drivers/clk/keystone/Kconfig"
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source "drivers/clk/mediatek/Kconfig"
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source "drivers/clk/meson/Kconfig"
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source "drivers/clk/mstar/Kconfig"
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source "drivers/clk/mvebu/Kconfig"
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source "drivers/clk/qcom/Kconfig"
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source "drivers/clk/renesas/Kconfig"
+1
drivers/clk/Makefile
+1
drivers/clk/Makefile
+5
drivers/clk/mstar/Kconfig
+5
drivers/clk/mstar/Kconfig
+6
drivers/clk/mstar/Makefile
+6
drivers/clk/mstar/Makefile
+155
drivers/clk/mstar/clk-msc313-mpll.c
+155
drivers/clk/mstar/clk-msc313-mpll.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* MStar MSC313 MPLL driver
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*
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* Copyright (C) 2020 Daniel Palmer <daniel@thingy.jp>
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*/
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#define REG_CONFIG1 0x8
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#define REG_CONFIG2 0xc
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static const struct regmap_config msc313_mpll_regmap_config = {
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.reg_bits = 16,
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.val_bits = 16,
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.reg_stride = 4,
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};
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static const struct reg_field config1_loop_div_first = REG_FIELD(REG_CONFIG1, 8, 9);
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static const struct reg_field config1_input_div_first = REG_FIELD(REG_CONFIG1, 4, 5);
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static const struct reg_field config2_output_div_first = REG_FIELD(REG_CONFIG2, 12, 13);
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static const struct reg_field config2_loop_div_second = REG_FIELD(REG_CONFIG2, 0, 7);
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static const unsigned int output_dividers[] = {
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2, 3, 4, 5, 6, 7, 10
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};
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#define NUMOUTPUTS (ARRAY_SIZE(output_dividers) + 1)
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struct msc313_mpll {
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struct clk_hw clk_hw;
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struct regmap_field *input_div;
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struct regmap_field *loop_div_first;
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struct regmap_field *loop_div_second;
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struct regmap_field *output_div;
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struct clk_hw_onecell_data *clk_data;
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};
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#define to_mpll(_hw) container_of(_hw, struct msc313_mpll, clk_hw)
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static unsigned long msc313_mpll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct msc313_mpll *mpll = to_mpll(hw);
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unsigned int input_div, output_div, loop_first, loop_second;
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unsigned long output_rate;
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regmap_field_read(mpll->input_div, &input_div);
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regmap_field_read(mpll->output_div, &output_div);
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regmap_field_read(mpll->loop_div_first, &loop_first);
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regmap_field_read(mpll->loop_div_second, &loop_second);
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output_rate = parent_rate / (1 << input_div);
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output_rate *= (1 << loop_first) * max(loop_second, 1U);
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output_rate /= max(output_div, 1U);
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return output_rate;
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}
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static const struct clk_ops msc313_mpll_ops = {
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.recalc_rate = msc313_mpll_recalc_rate,
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};
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static const struct clk_parent_data mpll_parent = {
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.index = 0,
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};
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static int msc313_mpll_probe(struct platform_device *pdev)
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{
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void __iomem *base;
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struct msc313_mpll *mpll;
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struct clk_init_data clk_init = { };
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struct device *dev = &pdev->dev;
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struct regmap *regmap;
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char *outputname;
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struct clk_hw *divhw;
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int ret, i;
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mpll = devm_kzalloc(dev, sizeof(*mpll), GFP_KERNEL);
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if (!mpll)
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return -ENOMEM;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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regmap = devm_regmap_init_mmio(dev, base, &msc313_mpll_regmap_config);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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mpll->input_div = devm_regmap_field_alloc(dev, regmap, config1_input_div_first);
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if (IS_ERR(mpll->input_div))
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return PTR_ERR(mpll->input_div);
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mpll->output_div = devm_regmap_field_alloc(dev, regmap, config2_output_div_first);
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if (IS_ERR(mpll->output_div))
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return PTR_ERR(mpll->output_div);
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mpll->loop_div_first = devm_regmap_field_alloc(dev, regmap, config1_loop_div_first);
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if (IS_ERR(mpll->loop_div_first))
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return PTR_ERR(mpll->loop_div_first);
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mpll->loop_div_second = devm_regmap_field_alloc(dev, regmap, config2_loop_div_second);
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if (IS_ERR(mpll->loop_div_second))
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return PTR_ERR(mpll->loop_div_second);
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mpll->clk_data = devm_kzalloc(dev, struct_size(mpll->clk_data, hws,
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ARRAY_SIZE(output_dividers)), GFP_KERNEL);
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if (!mpll->clk_data)
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return -ENOMEM;
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clk_init.name = dev_name(dev);
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clk_init.ops = &msc313_mpll_ops;
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clk_init.parent_data = &mpll_parent;
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clk_init.num_parents = 1;
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mpll->clk_hw.init = &clk_init;
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ret = devm_clk_hw_register(dev, &mpll->clk_hw);
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if (ret)
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return ret;
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mpll->clk_data->num = NUMOUTPUTS;
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mpll->clk_data->hws[0] = &mpll->clk_hw;
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for (i = 0; i < ARRAY_SIZE(output_dividers); i++) {
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outputname = devm_kasprintf(dev, GFP_KERNEL, "%s_div_%d",
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clk_init.name, output_dividers[i]);
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if (!outputname)
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return -ENOMEM;
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divhw = devm_clk_hw_register_fixed_factor(dev, outputname,
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clk_init.name, 0, 1, output_dividers[i]);
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if (IS_ERR(divhw))
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return PTR_ERR(divhw);
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mpll->clk_data->hws[i + 1] = divhw;
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}
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platform_set_drvdata(pdev, mpll);
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return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
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mpll->clk_data);
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}
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static const struct of_device_id msc313_mpll_of_match[] = {
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{ .compatible = "mstar,msc313-mpll", },
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{}
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};
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static struct platform_driver msc313_mpll_driver = {
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.driver = {
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.name = "mstar-msc313-mpll",
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.of_match_table = msc313_mpll_of_match,
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},
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.probe = msc313_mpll_probe,
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};
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builtin_platform_driver(msc313_mpll_driver);