tjh.dev / kernel
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serial: sc16is7xx: reformat comments to improve readability

Fold some multi-line comments into a single line, taking advantage of the
new 100 line length limit to improve readability and to have uniform style
across driver.

Add missing 's' to SC16IS7XX_MCR_TCRTLR_BIT registers comments.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Link: https://patch.msgid.link/20251027142957.1032073-14-hugo@hugovil.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Hugo Villeneuve and committed by
Greg Kroah-Hartman bee8828a b90871cb

+39 -82
+39 -82
drivers/tty/serial/sc16is7xx.c
··· 50 50 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 51 51 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 52 52 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 53 - #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 54 - * - only on 75x/76x 55 - */ 56 - #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 57 - * - only on 75x/76x 58 - */ 59 - #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 60 - * - only on 75x/76x 61 - */ 62 - #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 63 - * - only on 75x/76x 64 - */ 53 + #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction - only on 75x/76x */ 54 + #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State - only on 75x/76x */ 55 + #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable - only on 75x/76x */ 56 + #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control - only on 75x/76x */ 65 57 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 66 58 67 59 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ ··· 73 81 74 82 /* IER register bits */ 75 83 #define SC16IS7XX_IER_RDI_BIT BIT(0) /* Enable RX data interrupt */ 76 - #define SC16IS7XX_IER_THRI_BIT BIT(1) /* Enable TX holding register 77 - * interrupt */ 78 - #define SC16IS7XX_IER_RLSI_BIT BIT(2) /* Enable RX line status 79 - * interrupt */ 80 - #define SC16IS7XX_IER_MSI_BIT BIT(3) /* Enable Modem status 81 - * interrupt */ 84 + #define SC16IS7XX_IER_THRI_BIT BIT(1) /* Enable TX holding register interrupt */ 85 + #define SC16IS7XX_IER_RLSI_BIT BIT(2) /* Enable RX line status interrupt */ 86 + #define SC16IS7XX_IER_MSI_BIT BIT(3) /* Enable Modem status interrupt */ 82 87 83 88 /* IER register bits - write only if (EFR[4] == 1) */ 84 89 #define SC16IS7XX_IER_SLEEP_BIT BIT(4) /* Enable Sleep mode */ ··· 108 119 * - only on 75x/76x 109 120 */ 110 121 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 111 - #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 112 - * from active (LOW) 113 - * to inactive (HIGH) 122 + #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state from active 123 + * (LOW) to inactive (HIGH) 114 124 */ 115 125 /* LCR register bits */ 116 126 #define SC16IS7XX_LCR_LENGTH0_BIT BIT(0) /* Word length bit 0 */ ··· 125 137 * 126 138 * STOP length bit table: 127 139 * 0 -> 1 stop bit 128 - * 1 -> 1-1.5 stop bits if 129 - * word length is 5, 140 + * 1 -> 1-1.5 stop bits if word length is 5, 130 141 * 2 stop bits otherwise 131 142 */ 132 143 #define SC16IS7XX_LCR_PARITY_BIT BIT(3) /* Parity bit enable */ ··· 137 150 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 138 151 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 139 152 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 140 - #define SC16IS7XX_LCR_REG_SET_SPECIAL SC16IS7XX_LCR_DLAB_BIT /* Special 141 - * reg set 142 - */ 143 - #define SC16IS7XX_LCR_REG_SET_ENHANCED 0xBF /* Enhanced 144 - * reg set 145 - */ 153 + #define SC16IS7XX_LCR_REG_SET_SPECIAL SC16IS7XX_LCR_DLAB_BIT /* Special reg set */ 154 + #define SC16IS7XX_LCR_REG_SET_ENHANCED 0xBF /* Enhanced reg set */ 146 155 147 156 /* MCR register bits */ 148 - #define SC16IS7XX_MCR_DTR_BIT BIT(0) /* DTR complement 149 - * - only on 75x/76x 150 - */ 157 + #define SC16IS7XX_MCR_DTR_BIT BIT(0) /* DTR complement - only on 75x/76x */ 151 158 #define SC16IS7XX_MCR_RTS_BIT BIT(1) /* RTS complement */ 152 - #define SC16IS7XX_MCR_TCRTLR_BIT BIT(2) /* TCR/TLR register enable */ 159 + #define SC16IS7XX_MCR_TCRTLR_BIT BIT(2) /* TCR/TLR registers enable */ 153 160 #define SC16IS7XX_MCR_LOOP_BIT BIT(4) /* Enable loopback test mode */ 154 161 #define SC16IS7XX_MCR_XONANY_BIT BIT(5) /* Enable Xon Any 155 - * - write enabled 156 - * if (EFR[4] == 1) 162 + * - write enabled if (EFR[4] == 1) 157 163 */ 158 164 #define SC16IS7XX_MCR_IRDA_BIT BIT(6) /* Enable IrDA mode 159 - * - write enabled 160 - * if (EFR[4] == 1) 165 + * - write enabled if (EFR[4] == 1) 161 166 */ 162 167 #define SC16IS7XX_MCR_CLKSEL_BIT BIT(7) /* Divide clock by 4 163 - * - write enabled 164 - * if (EFR[4] == 1) 168 + * - write enabled if (EFR[4] == 1) 165 169 */ 166 170 167 171 /* LSR register bits */ ··· 173 195 174 196 /* MSR register bits */ 175 197 #define SC16IS7XX_MSR_DCTS_BIT BIT(0) /* Delta CTS Clear To Send */ 176 - #define SC16IS7XX_MSR_DDSR_BIT BIT(1) /* Delta DSR Data Set Ready 177 - * or (IO4) 198 + #define SC16IS7XX_MSR_DDSR_BIT BIT(1) /* Delta DSR Data Set Ready or (IO4) 178 199 * - only on 75x/76x 179 200 */ 180 - #define SC16IS7XX_MSR_DRI_BIT BIT(2) /* Delta RI Ring Indicator 181 - * or (IO7) 201 + #define SC16IS7XX_MSR_DRI_BIT BIT(2) /* Delta RI Ring Indicator or (IO7) 182 202 * - only on 75x/76x 183 203 */ 184 - #define SC16IS7XX_MSR_DCD_BIT BIT(3) /* Delta CD Carrier Detect 185 - * or (IO6) 204 + #define SC16IS7XX_MSR_DCD_BIT BIT(3) /* Delta CD Carrier Detect or (IO6) 186 205 * - only on 75x/76x 187 206 */ 188 207 #define SC16IS7XX_MSR_CTS_BIT BIT(4) /* CTS */ 189 - #define SC16IS7XX_MSR_DSR_BIT BIT(5) /* DSR (IO4) 190 - * - only on 75x/76x 191 - */ 192 - #define SC16IS7XX_MSR_RI_BIT BIT(6) /* RI (IO7) 193 - * - only on 75x/76x 194 - */ 195 - #define SC16IS7XX_MSR_CD_BIT BIT(7) /* CD (IO6) 196 - * - only on 75x/76x 197 - */ 208 + #define SC16IS7XX_MSR_DSR_BIT BIT(5) /* DSR (IO4) - only on 75x/76x */ 209 + #define SC16IS7XX_MSR_RI_BIT BIT(6) /* RI (IO7) - only on 75x/76x */ 210 + #define SC16IS7XX_MSR_CD_BIT BIT(7) /* CD (IO6) - only on 75x/76x */ 198 211 199 212 /* 200 213 * TCR register bits ··· 224 255 #define SC16IS7XX_IOCONTROL_SRESET_BIT BIT(3) /* Software Reset */ 225 256 226 257 /* EFCR register bits */ 227 - #define SC16IS7XX_EFCR_9BIT_MODE_BIT BIT(0) /* Enable 9-bit or Multidrop 228 - * mode (RS485) */ 258 + #define SC16IS7XX_EFCR_9BIT_MODE_BIT BIT(0) /* Enable 9-bit or Multidrop mode (RS485) */ 229 259 #define SC16IS7XX_EFCR_RXDISABLE_BIT BIT(1) /* Disable receiver */ 230 260 #define SC16IS7XX_EFCR_TXDISABLE_BIT BIT(2) /* Disable transmitter */ 231 261 #define SC16IS7XX_EFCR_AUTO_RS485_BIT BIT(4) /* Auto RS485 RTS direction */ 232 262 #define SC16IS7XX_EFCR_RTS_INVERT_BIT BIT(5) /* RTS output inversion */ 233 263 #define SC16IS7XX_EFCR_IRDA_MODE_BIT BIT(7) /* IrDA mode 234 - * 0 = rate upto 115.2 kbit/s 235 - * - Only 75x/76x 236 - * 1 = rate upto 1.152 Mbit/s 237 - * - Only 76x 264 + * 0 = rate up to 115.2 kbit/s - Only 75x/76x 265 + * 1 = rate up to 1.152 Mbit/s - Only 76x 238 266 */ 239 267 240 268 /* EFR register bits */ 241 269 #define SC16IS7XX_EFR_AUTORTS_BIT BIT(6) /* Auto RTS flow ctrl enable */ 242 270 #define SC16IS7XX_EFR_AUTOCTS_BIT BIT(7) /* Auto CTS flow ctrl enable */ 243 271 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT BIT(5) /* Enable Xoff2 detection */ 244 - #define SC16IS7XX_EFR_ENABLE_BIT BIT(4) /* Enable enhanced functions 245 - * and writing to IER[7:4], 246 - * FCR[5:4], MCR[7:5] 272 + #define SC16IS7XX_EFR_ENABLE_BIT BIT(4) /* Enable enhanced functions and writing to 273 + * IER[7:4], FCR[5:4], MCR[7:5] 247 274 */ 248 275 #define SC16IS7XX_EFR_SWFLOW3_BIT BIT(3) 249 276 #define SC16IS7XX_EFR_SWFLOW2_BIT BIT(2) 250 277 /* 251 278 * SWFLOW bits 3 & 2 table: 252 - * 00 -> no transmitter flow 253 - * control 254 - * 01 -> transmitter generates 255 - * XON2 and XOFF2 256 - * 10 -> transmitter generates 257 - * XON1 and XOFF1 258 - * 11 -> transmitter generates 259 - * XON1, XON2, XOFF1 and 260 - * XOFF2 279 + * 00 -> no transmitter flow control 280 + * 01 -> transmitter generates XON2 and XOFF2 281 + * 10 -> transmitter generates XON1 and XOFF1 282 + * 11 -> transmitter generates XON1, XON2, 283 + * XOFF1 and XOFF2 261 284 */ 262 285 #define SC16IS7XX_EFR_SWFLOW1_BIT BIT(1) 263 286 #define SC16IS7XX_EFR_SWFLOW0_BIT BIT(0) 264 287 /* 265 288 * SWFLOW bits 1 & 0 table: 266 - * 00 -> no received flow 267 - * control 268 - * 01 -> receiver compares 269 - * XON2 and XOFF2 270 - * 10 -> receiver compares 271 - * XON1 and XOFF1 272 - * 11 -> receiver compares 273 - * XON1, XON2, XOFF1 and 274 - * XOFF2 289 + * 00 -> no received flow control 290 + * 01 -> receiver compares XON2 and XOFF2 291 + * 10 -> receiver compares XON1 and XOFF1 292 + * 11 -> receiver compares XON1, XON2, 293 + * XOFF1 and XOFF2 275 294 */ 276 295 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ 277 296 SC16IS7XX_EFR_AUTOCTS_BIT | \ ··· 1109 1152 1110 1153 sc16is7xx_power(port, 1); 1111 1154 1112 - /* Reset FIFOs*/ 1155 + /* Reset FIFOs */ 1113 1156 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 1114 1157 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 1115 1158 udelay(5);