tjh.dev / kernel
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sh: hd64461: Fix up I/O base register offsets.

hd64461 is mapped in a fixed location, so the I/O base itself is fairly
meaningless as a configuration item. Additionally, this makes it
impossible to share hd64461 code alongside generic drivers (in the case
of sh_dac_audio), so simply make it commonly defined and permit the
mach_is_foo() logic to work out the proper semantics.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Paul Mundt bec36eca 9304d0cc

+74 -77
-5
arch/sh/cchips/Kconfig
··· 34 34 35 35 Do not change this unless you know what you are doing. 36 36 37 - config HD64461_IOBASE 38 - hex "HD64461 start address" 39 - depends on HD64461 40 - default "0xb0000000" 41 - 42 37 config HD64461_ENABLER 43 38 bool "HD64461 PCMCIA enabler" 44 39 depends on HD64461
+74 -72
arch/sh/include/asm/hd64461.h
··· 13 13 #define HD64461_PCC_WINDOW 0x01000000 14 14 15 15 /* Area 6 - Slot 0 - memory and/or IO card */ 16 - #define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000) 16 + #define HD64461_IOBASE 0xb0000000 17 + #define HD64461_IO_OFFSET(x) (HD64461_IOBASE + (x)) 18 + #define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000) 17 19 #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */ 18 20 #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */ 19 21 #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */ 20 22 21 23 /* Area 5 - Slot 1 - memory card only */ 22 - #define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000) 24 + #define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000) 23 25 #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */ 24 26 #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */ 25 27 ··· 43 41 #define HD64461_STBCR_SURTST 0x0001 44 42 45 43 /* System Configuration Register */ 46 - #define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02) 44 + #define HD64461_SYSCR HD64461_IO_OFFSET(0x02) 47 45 48 46 /* CPU Data Bus Control Register */ 49 - #define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04) 47 + #define HD64461_SCPUCR HD64461_IO_OFFSET(0x04) 50 48 51 49 /* Base Address Register */ 52 - #define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000) 50 + #define HD64461_LCDCBAR HD64461_IO_OFFSET(0x1000) 53 51 54 52 /* Line increment address */ 55 - #define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002) 53 + #define HD64461_LCDCLOR HD64461_IO_OFFSET(0x1002) 56 54 57 55 /* Controls LCD controller */ 58 - #define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004) 56 + #define HD64461_LCDCCR HD64461_IO_OFFSET(0x1004) 59 57 60 58 /* LCCDR control bits */ 61 59 #define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */ ··· 66 64 #define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */ 67 65 68 66 /* Controls LCD (1) */ 69 - #define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010) 67 + #define HD64461_LDR1 HD64461_IO_OFFSET(0x1010) 70 68 #define HD64461_LDR1_DON 0x01 /* Display On */ 71 69 #define HD64461_LDR1_DINV 0x80 /* Display Invert */ 72 70 73 71 /* Controls LCD (2) */ 74 - #define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012) 75 - #define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */ 76 - #define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */ 77 - #define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */ 78 - #define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */ 79 - #define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */ 72 + #define HD64461_LDR2 HD64461_IO_OFFSET(0x1012) 73 + #define HD64461_LDHNCR HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */ 74 + #define HD64461_LDHNSR HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */ 75 + #define HD64461_LDVNTR HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */ 76 + #define HD64461_LDVNDR HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */ 77 + #define HD64461_LDVSPR HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */ 80 78 81 79 /* Controls LCD (3) */ 82 - #define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e) 80 + #define HD64461_LDR3 HD64461_IO_OFFSET(0x101e) 83 81 84 82 /* Palette Registers */ 85 - #define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Address Register */ 86 - #define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */ 87 - #define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Address Register */ 88 - #define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */ 83 + #define HD64461_CPTWAR HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */ 84 + #define HD64461_CPTWDR HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */ 85 + #define HD64461_CPTRAR HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */ 86 + #define HD64461_CPTRDR HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */ 89 87 90 - #define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */ 91 - #define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */ 92 - #define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */ 88 + #define HD64461_GRDOR HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */ 89 + #define HD64461_GRSCR HD64461_IO_OFFSET(0x1042) /* Solid Color Register */ 90 + #define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */ 93 91 94 92 #define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */ 95 93 #define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */ ··· 99 97 #define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ 100 98 101 99 /* Line Drawing Registers */ 102 - #define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Address Register (H) */ 103 - #define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Address Register (L) */ 104 - #define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */ 105 - #define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */ 106 - #define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */ 107 - #define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */ 108 - #define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */ 100 + #define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */ 101 + #define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */ 102 + #define HD64461_LNAXLR HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */ 103 + #define HD64461_LNDGR HD64461_IO_OFFSET(0x104c) /* Diagonal Register */ 104 + #define HD64461_LNAXR HD64461_IO_OFFSET(0x104e) /* Axial Register */ 105 + #define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */ 106 + #define HD64461_LNMDR HD64461_IO_OFFSET(0x1052) /* Line Mode Register */ 109 107 110 108 /* BitBLT Registers */ 111 - #define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Address Register (H) */ 112 - #define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Address Register (L) */ 113 - #define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Address Register (H) */ 114 - #define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Address Register (L) */ 115 - #define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */ 116 - #define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */ 117 - #define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Address Register (H) */ 118 - #define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Address Register (L) */ 119 - #define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Address Register (H) */ 120 - #define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Address Register (L) */ 121 - #define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */ 122 - #define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */ 109 + #define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */ 110 + #define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */ 111 + #define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */ 112 + #define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */ 113 + #define HD64461_BBTDWR HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */ 114 + #define HD64461_BBTDHR HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */ 115 + #define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */ 116 + #define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */ 117 + #define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */ 118 + #define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */ 119 + #define HD64461_BBTROPR HD64461_IO_OFFSET(0x1068) /* ROP Register */ 120 + #define HD64461_BBTMDR HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */ 123 121 124 122 /* PC Card Controller Registers */ 125 123 /* Maps to Physical Area 6 */ 126 - #define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */ 127 - #define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */ 128 - #define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */ 129 - #define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */ 130 - #define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */ 124 + #define HD64461_PCC0ISR HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */ 125 + #define HD64461_PCC0GCR HD64461_IO_OFFSET(0x2002) /* socket 0 general control */ 126 + #define HD64461_PCC0CSCR HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */ 127 + #define HD64461_PCC0CSCIER HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */ 128 + #define HD64461_PCC0SCR HD64461_IO_OFFSET(0x2008) /* socket 0 software control */ 131 129 /* Maps to Physical Area 5 */ 132 - #define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */ 133 - #define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */ 134 - #define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */ 135 - #define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */ 136 - #define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */ 130 + #define HD64461_PCC1ISR HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */ 131 + #define HD64461_PCC1GCR HD64461_IO_OFFSET(0x2012) /* socket 1 general control */ 132 + #define HD64461_PCC1CSCR HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */ 133 + #define HD64461_PCC1CSCIER HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */ 134 + #define HD64461_PCC1SCR HD64461_IO_OFFSET(0x2018) /* socket 1 software control */ 137 135 138 136 /* PCC Interface Status Register */ 139 137 #define HD64461_PCCISR_READY 0x80 /* card ready */ ··· 191 189 #define HD64461_PCCSCR_SWP 0x01 /* write protect */ 192 190 193 191 /* PCC0 Output Pins Control Register */ 194 - #define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a) 192 + #define HD64461_P0OCR HD64461_IO_OFFSET(0x202a) 195 193 196 194 /* PCC1 Output Pins Control Register */ 197 - #define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c) 195 + #define HD64461_P1OCR HD64461_IO_OFFSET(0x202c) 198 196 199 197 /* PC Card General Control Register */ 200 - #define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e) 198 + #define HD64461_PGCR HD64461_IO_OFFSET(0x202e) 201 199 202 200 /* Port Control Registers */ 203 - #define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */ 204 - #define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */ 205 - #define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */ 206 - #define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */ 201 + #define HD64461_GPACR HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */ 202 + #define HD64461_GPBCR HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */ 203 + #define HD64461_GPCCR HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */ 204 + #define HD64461_GPDCR HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */ 207 205 208 206 /* Port Control Data Registers */ 209 - #define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */ 210 - #define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */ 211 - #define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */ 212 - #define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */ 207 + #define HD64461_GPADR HD64461_IO_OFFSET(0x4010) /* A */ 208 + #define HD64461_GPBDR HD64461_IO_OFFSET(0x4012) /* B */ 209 + #define HD64461_GPCDR HD64461_IO_OFFSET(0x4014) /* C */ 210 + #define HD64461_GPDDR HD64461_IO_OFFSET(0x4016) /* D */ 213 211 214 212 /* Interrupt Control Registers */ 215 - #define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */ 216 - #define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */ 217 - #define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */ 218 - #define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */ 213 + #define HD64461_GPAICR HD64461_IO_OFFSET(0x4020) /* A */ 214 + #define HD64461_GPBICR HD64461_IO_OFFSET(0x4022) /* B */ 215 + #define HD64461_GPCICR HD64461_IO_OFFSET(0x4024) /* C */ 216 + #define HD64461_GPDICR HD64461_IO_OFFSET(0x4026) /* D */ 219 217 220 218 /* Interrupt Status Registers */ 221 - #define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */ 222 - #define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */ 223 - #define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */ 224 - #define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */ 219 + #define HD64461_GPAISR HD64461_IO_OFFSET(0x4040) /* A */ 220 + #define HD64461_GPBISR HD64461_IO_OFFSET(0x4042) /* B */ 221 + #define HD64461_GPCISR HD64461_IO_OFFSET(0x4044) /* C */ 222 + #define HD64461_GPDISR HD64461_IO_OFFSET(0x4046) /* D */ 225 223 226 224 /* Interrupt Request Register & Interrupt Mask Register */ 227 - #define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000) 228 - #define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002) 225 + #define HD64461_NIRR HD64461_IO_OFFSET(0x5000) 226 + #define HD64461_NIMR HD64461_IO_OFFSET(0x5002) 229 227 230 228 #define HD64461_IRQBASE OFFCHIP_IRQ_BASE 231 229 #define OFFCHIP_IRQ_BASE 64