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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
sh: NR_IRQS consolidation.
Each board sets the total number of IRQs that it's interested in via
the machvec. Previously we cared about the off vs on-chip IRQ range,
but any code relying on that is long dead. Set NR_IRQS to something
sensible given the vector range, and allow boards to cap it if they
really care.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
authored by
Paul Mundt
and committed by
Paul Mundt
be782df5
fa691511
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-88
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arch/sh/kernel/irq.c
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-2
arch/sh/kernel/irq.c
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#include <linux/seq_file.h>
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#include <linux/irq.h>
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#include <asm/processor.h>
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#include <asm/machvec.h>
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#include <asm/uaccess.h>
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#include <asm/thread_info.h>
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#include <asm/cpu/mmu_context.h>
···
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seq_putc(p, '\n');
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}
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if (i < NR_IRQS) {
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if (i < sh_mv.mv_nr_irqs) {
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spin_lock_irqsave(&irq_desc[i].lock, flags);
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action = irq_desc[i].action;
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if (!action)
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seq_putc(p, '\n');
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unlock:
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spin_unlock_irqrestore(&irq_desc[i].lock, flags);
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} else if (i == NR_IRQS)
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} else if (i == sh_mv.mv_nr_irqs)
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seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count));
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return 0;
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include/asm-sh/irq.h
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include/asm-sh/irq.h
···
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#define __ASM_SH_IRQ_H
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#include <asm/machvec.h>
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#include <asm/ptrace.h> /* for pt_regs */
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/* NR_IRQS is made from three components:
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* 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
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* 2. PINT_NR_IRQS - number of PINT interrupts
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* 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
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/*
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* A sane default based on a reasonable vector table size, platforms are
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* advised to cap this at the hard limit that they're interested in
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* through the machvec.
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*/
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-
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/* 1. ONCHIP_NR_IRQS */
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#if defined(CONFIG_CPU_SUBTYPE_SH7604)
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# define ONCHIP_NR_IRQS 24 // Actually 21
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#elif defined(CONFIG_CPU_SUBTYPE_SH7707)
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# define ONCHIP_NR_IRQS 64
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# define PINT_NR_IRQS 16
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#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
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# define ONCHIP_NR_IRQS 32
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#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7705)
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# define ONCHIP_NR_IRQS 64 // Actually 61
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# define PINT_NR_IRQS 16
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
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# define ONCHIP_NR_IRQS 104
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#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
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# define ONCHIP_NR_IRQS 48 // Actually 44
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#elif defined(CONFIG_CPU_SUBTYPE_SH7751)
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# define ONCHIP_NR_IRQS 72
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#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
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# define ONCHIP_NR_IRQS 112 /* XXX */
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#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
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# define ONCHIP_NR_IRQS 72
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#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
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# define ONCHIP_NR_IRQS 144
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#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
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defined(CONFIG_CPU_SUBTYPE_SH73180) || \
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defined(CONFIG_CPU_SUBTYPE_SH7343) || \
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defined(CONFIG_CPU_SUBTYPE_SH7722)
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# define ONCHIP_NR_IRQS 109
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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# define ONCHIP_NR_IRQS 111
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#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
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# define ONCHIP_NR_IRQS 256
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#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
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# define ONCHIP_NR_IRQS 128
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#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
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# define ONCHIP_NR_IRQS 144
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#endif
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/* 2. PINT_NR_IRQS */
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#ifdef CONFIG_SH_UNKNOWN
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# define PINT_NR_IRQS 16
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#else
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# ifndef PINT_NR_IRQS
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# define PINT_NR_IRQS 0
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# endif
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#endif
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#if PINT_NR_IRQS > 0
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# define PINT_IRQ_BASE ONCHIP_NR_IRQS
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#endif
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/* 3. OFFCHIP_NR_IRQS */
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#if defined(CONFIG_HD64461)
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# define OFFCHIP_NR_IRQS 18
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#elif defined(CONFIG_HD64465)
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# define OFFCHIP_NR_IRQS 16
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#elif defined (CONFIG_SH_DREAMCAST)
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# define OFFCHIP_NR_IRQS 96
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#elif defined (CONFIG_SH_TITAN)
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# define OFFCHIP_NR_IRQS 4
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#elif defined(CONFIG_SH_R7780RP)
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# define OFFCHIP_NR_IRQS 16
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#elif defined(CONFIG_SH_7343_SOLUTION_ENGINE)
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# define OFFCHIP_NR_IRQS 12
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#elif defined(CONFIG_SH_7722_SOLUTION_ENGINE)
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# define OFFCHIP_NR_IRQS 14
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#elif defined(CONFIG_SH_UNKNOWN)
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# define OFFCHIP_NR_IRQS 16 /* Must also be last */
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#else
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# define OFFCHIP_NR_IRQS 0
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#endif
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#if OFFCHIP_NR_IRQS > 0
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# define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
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#endif
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/* NR_IRQS. 1+2+3 */
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#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
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#define NR_IRQS 256
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/*
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* Convert back and forth between INTEVT and IRQ values.