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kernel os linux

dt-bindings: thermal: mediatek: Fix thermal zone definitions for MT8188

Fix thermal zone names for consistency with the other SoCs:
- GPU0 must be used as the first GPU item.
- SOCx deal with audio DSP, video, and infra subsystems.

The naming must be fixed "atomically" so compilation does not break.
As a result, the change is made in the dt-bindings and in the LVTS
driver within a single commit, despite the checkpatch warning.

The definitions can be safely modified here because they are used only
in the LVTS driver, which is modified accordingly, and have not yet
been included in a released kernel.

Fixes: 78c88534e5e1 ("dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for MT8188")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Link: https://lore.kernel.org/r/20240603-mtk-thermal-mt818x-dtsi-v7-2-8c8e3c7a3643@baylibre.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

authored by

Julien Panis and committed by
Daniel Lezcano
be3e224e 6b04928e

+10 -10
+5 -5
drivers/thermal/mediatek/lvts_thermal.c
··· 1488 1488 }, 1489 1489 { 1490 1490 .lvts_sensor = { 1491 - { .dt_id = MT8188_AP_GPU1, 1491 + { .dt_id = MT8188_AP_GPU0, 1492 1492 .cal_offsets = { 43, 44, 45 } }, 1493 - { .dt_id = MT8188_AP_GPU2, 1493 + { .dt_id = MT8188_AP_GPU1, 1494 1494 .cal_offsets = { 46, 47, 48 } }, 1495 - { .dt_id = MT8188_AP_SOC1, 1495 + { .dt_id = MT8188_AP_ADSP, 1496 1496 .cal_offsets = { 49, 50, 51 } }, 1497 1497 }, 1498 1498 VALID_SENSOR_MAP(1, 1, 1, 0), ··· 1500 1500 }, 1501 1501 { 1502 1502 .lvts_sensor = { 1503 - { .dt_id = MT8188_AP_SOC2, 1503 + { .dt_id = MT8188_AP_VDO, 1504 1504 .cal_offsets = { 52, 53, 54 } }, 1505 - { .dt_id = MT8188_AP_SOC3, 1505 + { .dt_id = MT8188_AP_INFRA, 1506 1506 .cal_offsets = { 55, 56, 57 } }, 1507 1507 }, 1508 1508 VALID_SENSOR_MAP(1, 1, 0, 0),
+5 -5
include/dt-bindings/thermal/mediatek,lvts-thermal.h
··· 34 34 #define MT8188_MCU_BIG_CPU1 5 35 35 36 36 #define MT8188_AP_APU 0 37 - #define MT8188_AP_GPU1 1 38 - #define MT8188_AP_GPU2 2 39 - #define MT8188_AP_SOC1 3 40 - #define MT8188_AP_SOC2 4 41 - #define MT8188_AP_SOC3 5 37 + #define MT8188_AP_GPU0 1 38 + #define MT8188_AP_GPU1 2 39 + #define MT8188_AP_ADSP 3 40 + #define MT8188_AP_VDO 4 41 + #define MT8188_AP_INFRA 5 42 42 #define MT8188_AP_CAM1 6 43 43 #define MT8188_AP_CAM2 7 44 44