Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'fpga-for-6.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga into char-misc-next

Xu writes:

FPGA Manager changes for 6.5-rc1

DFL:

- Krzysztof's change constifies pointers to hwmon_channel_info

Xilinx:

- Alfonso's change ensures proper reprograming (xCAP) interface switch

All patches have been reviewed on the mailing list, and have been in the
last linux-next releases (as part of our for-next branch).

Signed-off-by: Xu Yilun <yilun.xu@intel.com>

* tag 'fpga-for-6.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga:
fpga: zynq-fpga: Ensure proper xCAP interface switch
fpga: dfl-fme: constify pointers to hwmon_channel_info

+6 -6
+2 -2
drivers/fpga/dfl-fme-main.c
··· 265 265 .read = thermal_hwmon_read, 266 266 }; 267 267 268 - static const struct hwmon_channel_info *thermal_hwmon_info[] = { 268 + static const struct hwmon_channel_info * const thermal_hwmon_info[] = { 269 269 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_EMERGENCY | 270 270 HWMON_T_MAX | HWMON_T_MAX_ALARM | 271 271 HWMON_T_CRIT | HWMON_T_CRIT_ALARM), ··· 465 465 .write = power_hwmon_write, 466 466 }; 467 467 468 - static const struct hwmon_channel_info *power_hwmon_info[] = { 468 + static const struct hwmon_channel_info * const power_hwmon_info[] = { 469 469 HWMON_CHANNEL_INFO(power, HWMON_P_INPUT | 470 470 HWMON_P_MAX | HWMON_P_MAX_ALARM | 471 471 HWMON_P_CRIT | HWMON_P_CRIT_ALARM),
+4 -4
drivers/fpga/zynq-fpga.c
··· 493 493 if (err) 494 494 return err; 495 495 496 - /* Release 'PR' control back to the ICAP */ 497 - zynq_fpga_write(priv, CTRL_OFFSET, 498 - zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); 499 - 500 496 err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, 501 497 intr_status & IXR_PCFG_DONE_MASK, 502 498 INIT_POLL_DELAY, 503 499 INIT_POLL_TIMEOUT); 500 + 501 + /* Release 'PR' control back to the ICAP */ 502 + zynq_fpga_write(priv, CTRL_OFFSET, 503 + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); 504 504 505 505 clk_disable(priv->clk); 506 506