drm/amd/display: Add missing registers · tjh.dev/kernel@be23968

+20

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h

··· 5695 5695 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 5696 5696 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 5697 5697 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 5698 + #define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a 5699 + #define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 5700 + #define mmDSCC0_DSCC_TEST_DEBUG_DATA0 0x303b 5701 + #define mmDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 5702 + #define mmDSCC0_DSCC_TEST_DEBUG_DATA1 0x303c 5703 + #define mmDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 5704 + #define mmDSCC0_DSCC_TEST_DEBUG_DATA2 0x303d 5705 + #define mmDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 5706 + #define mmDSCC0_DSCC_TEST_DEBUG_DATA3 0x303e 5707 + #define mmDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 5698 5708 5699 5709 5700 5710 // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec ··· 5835 5825 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 5836 5826 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 5837 5827 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 5828 + #define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 5829 + #define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 5830 + #define mmDSCC1_DSCC_TEST_DEBUG_DATA0 0x3097 5831 + #define mmDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 5832 + #define mmDSCC1_DSCC_TEST_DEBUG_DATA1 0x3098 5833 + #define mmDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 5834 + #define mmDSCC1_DSCC_TEST_DEBUG_DATA2 0x3099 5835 + #define mmDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 5836 + #define mmDSCC1_DSCC_TEST_DEBUG_DATA3 0x309a 5837 + #define mmDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 5838 5838 5839 5839 5840 5840 // addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec

+11

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h

··· 22265 22265 #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L 22266 22266 //DSC_TOP0_DSC_DEBUG_CONTROL 22267 22267 #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 22268 + #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 22268 22269 #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L 22270 + #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L 22269 22271 22270 22272 22271 22273 // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec ··· 22640 22638 //DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 22641 22639 #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 22642 22640 #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL 22641 + //DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 22642 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 22643 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 22644 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 22645 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 22646 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL 22647 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L 22648 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L 22649 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L 22643 22650 22644 22651 22645 22652 // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec

+4

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h

··· 424 424 #define regDTBCLK_DTO2_MODULO_BASE_IDX 2 425 425 #define regDTBCLK_DTO3_MODULO 0x0022 426 426 #define regDTBCLK_DTO3_MODULO_BASE_IDX 2 427 + #define regHDMICHARCLK0_CLOCK_CNTL 0x004a 428 + #define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2 427 429 #define regPHYASYMCLK_CLOCK_CNTL 0x0052 428 430 #define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 429 431 #define regPHYBSYMCLK_CLOCK_CNTL 0x0053 ··· 436 434 #define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 437 435 #define regPHYESYMCLK_CLOCK_CNTL 0x0056 438 436 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 437 + #define regHDMISTREAMCLK_CNTL 0x0059 438 + #define regHDMISTREAMCLK_CNTL_BASE_IDX 2 439 439 #define regDCCG_GATE_DISABLE_CNTL3 0x005a 440 440 #define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 441 441 #define regHDMISTREAMCLK0_DTO_PARAM 0x005b

+19

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h

··· 1372 1372 //DTBCLK_DTO3_MODULO 1373 1373 #define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO__SHIFT 0x0 1374 1374 #define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO_MASK 0xFFFFFFFFL 1375 + //HDMICHARCLK0_CLOCK_CNTL 1376 + #define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT 0x0 1377 + #define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT 0x4 1378 + #define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK 0x00000001L 1379 + #define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK 0x00000070L 1375 1380 //PHYASYMCLK_CLOCK_CNTL 1376 1381 #define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT 0x0 1377 1382 #define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT 0x4 ··· 1402 1397 #define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL__SHIFT 0x4 1403 1398 #define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN_MASK 0x00000001L 1404 1399 #define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL_MASK 0x00000030L 1400 + //HDMISTREAMCLK_CNTL 1401 + #define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL__SHIFT 0x0 1402 + #define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN__SHIFT 0x3 1403 + #define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS__SHIFT 0x4 1404 + #define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL_MASK 0x00000007L 1405 + #define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN_MASK 0x00000008L 1406 + #define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS_MASK 0x00000010L 1405 1407 //DCCG_GATE_DISABLE_CNTL3 1406 1408 #define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT 0x0 1407 1409 #define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT 0x1 ··· 46990 46978 #define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L 46991 46979 #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L 46992 46980 #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L 46981 + 46982 + 46983 + //DSC_TOP0_DSC_DEBUG_CONTROL 46984 + #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 46985 + #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 46986 + #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L 46987 + #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L 46993 46988 //DSC_TOP0_DSC_DEBUG_CONTROL 46994 46989 #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 46995 46990 #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4

+60

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h

··· 1719 1719 #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 1720 1720 #define regFMON_CTRL 0x0541 1721 1721 #define regFMON_CTRL_BASE_IDX 2 1722 + #define regDCHUBBUB_TEST_DEBUG_INDEX 0x0542 1723 + #define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 1724 + #define regDCHUBBUB_TEST_DEBUG_DATA 0x0543 1725 + #define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 1722 1726 1723 1727 1724 1728 // addressBlock: dcn_dc_dchubbubl_hubbub_sdpif_dispdec ··· 3578 3574 #define regCM0_CM_DEALPHA_BASE_IDX 2 3579 3575 #define regCM0_CM_COEF_FORMAT 0x0d8c 3580 3576 #define regCM0_CM_COEF_FORMAT_BASE_IDX 2 3577 + #define regCM0_CM_TEST_DEBUG_INDEX 0x0d8d 3578 + #define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 3579 + #define regCM0_CM_TEST_DEBUG_DATA 0x0d8e 3580 + #define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 3581 3581 3582 3582 3583 3583 // addressBlock: dcn_dc_dpp0_dispdec_dpp_top_dispdec ··· 3968 3960 #define regCM1_CM_DEALPHA_BASE_IDX 2 3969 3961 #define regCM1_CM_COEF_FORMAT 0x0ef7 3970 3962 #define regCM1_CM_COEF_FORMAT_BASE_IDX 2 3963 + #define regCM1_CM_TEST_DEBUG_INDEX 0x0ef8 3964 + #define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 3965 + #define regCM1_CM_TEST_DEBUG_DATA 0x0ef9 3966 + #define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 3971 3967 3972 3968 3973 3969 // addressBlock: dcn_dc_dpp1_dispdec_dpp_top_dispdec ··· 4358 4346 #define regCM2_CM_DEALPHA_BASE_IDX 2 4359 4347 #define regCM2_CM_COEF_FORMAT 0x1062 4360 4348 #define regCM2_CM_COEF_FORMAT_BASE_IDX 2 4349 + #define regCM2_CM_TEST_DEBUG_INDEX 0x1063 4350 + #define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4351 + #define regCM2_CM_TEST_DEBUG_DATA 0x1064 4352 + #define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 4361 4353 4362 4354 4363 4355 // addressBlock: dcn_dc_dpp2_dispdec_dpp_top_dispdec ··· 4748 4732 #define regCM3_CM_DEALPHA_BASE_IDX 2 4749 4733 #define regCM3_CM_COEF_FORMAT 0x11cd 4750 4734 #define regCM3_CM_COEF_FORMAT_BASE_IDX 2 4735 + #define regCM3_CM_TEST_DEBUG_INDEX 0x11ce 4736 + #define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4737 + #define regCM3_CM_TEST_DEBUG_DATA 0x11cf 4738 + #define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 4751 4739 4752 4740 4753 4741 // addressBlock: dcn_dc_dpp3_dispdec_dpp_top_dispdec ··· 11800 11780 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11801 11781 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 11802 11782 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11783 + #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a 11784 + #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 11785 + #define regDSCC0_DSCC_TEST_DEBUG_DATA0 0x303b 11786 + #define regDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 11787 + #define regDSCC0_DSCC_TEST_DEBUG_DATA1 0x303c 11788 + #define regDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 11789 + #define regDSCC0_DSCC_TEST_DEBUG_DATA2 0x303d 11790 + #define regDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 11791 + #define regDSCC0_DSCC_TEST_DEBUG_DATA3 0x303e 11792 + #define regDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 11803 11793 11804 11794 11805 11795 // addressBlock: dcn_dc_dsc0_dispdec_dsccif_dispdec ··· 11918 11888 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11919 11889 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 11920 11890 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11891 + #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 11892 + #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 11893 + #define regDSCC1_DSCC_TEST_DEBUG_DATA0 0x3097 11894 + #define regDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 11895 + #define regDSCC1_DSCC_TEST_DEBUG_DATA1 0x3098 11896 + #define regDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 11897 + #define regDSCC1_DSCC_TEST_DEBUG_DATA2 0x3099 11898 + #define regDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 11899 + #define regDSCC1_DSCC_TEST_DEBUG_DATA3 0x309a 11900 + #define regDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 11921 11901 11922 11902 11923 11903 // addressBlock: dcn_dc_dsc1_dispdec_dsccif_dispdec ··· 12036 11996 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12037 11997 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed 12038 11998 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11999 + #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2 12000 + #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12001 + #define regDSCC2_DSCC_TEST_DEBUG_DATA0 0x30f3 12002 + #define regDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 12003 + #define regDSCC2_DSCC_TEST_DEBUG_DATA1 0x30f4 12004 + #define regDSCC2_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 12005 + #define regDSCC2_DSCC_TEST_DEBUG_DATA2 0x30f5 12006 + #define regDSCC2_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 12007 + #define regDSCC2_DSCC_TEST_DEBUG_DATA3 0x30f6 12008 + #define regDSCC2_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 12039 12009 12040 12010 12041 12011 // addressBlock: dcn_dc_dsc2_dispdec_dsccif_dispdec ··· 12154 12104 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12155 12105 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149 12156 12106 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12107 + #define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x314e 12108 + #define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12109 + #define regDSCC3_DSCC_TEST_DEBUG_DATA0 0x314f 12110 + #define regDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 12111 + #define regDSCC3_DSCC_TEST_DEBUG_DATA1 0x3150 12112 + #define regDSCC3_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 12113 + #define regDSCC3_DSCC_TEST_DEBUG_DATA2 0x3151 12114 + #define regDSCC3_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 12115 + #define regDSCC3_DSCC_TEST_DEBUG_DATA3 0x3152 12116 + #define regDSCC3_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 12157 12117 12158 12118 12159 12119 // addressBlock: dcn_dc_dsc3_dispdec_dsccif_dispdec

+22

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h

··· 42272 42272 //DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 42273 42273 #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 42274 42274 #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL 42275 + //DSCC0_DSCC_TEST_DEBUG_INDEX2 42276 + #define DSCC0_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2__SHIFT 0x0 42277 + #define DSCC0_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2_MASK 0x000000FFL 42278 + //DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 42279 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 42280 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 42281 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 42282 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 42283 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL 42284 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L 42285 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L 42286 + #define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L 42275 42287 42276 42288 42277 42289 // addressBlock: dcn_dc_dsc0_dispdec_dsccif_dispdec ··· 42315 42303 #define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L 42316 42304 #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L 42317 42305 #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L 42306 + //DSC_TOP0_DSC_DEBUG_CONTROL 42307 + #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 42308 + #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 42309 + #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L 42310 + #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L 42311 + 42312 + 42313 + //DSC_TOP0_DSC_DEBUG_CONTROL 42314 + #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 42315 + #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 42318 42316 //DSC_TOP0_DSC_DEBUG_CONTROL 42319 42317 #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 42320 42318 #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L

+3 -1

drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_3_sh_mask.h

··· 70 70 //DPCSTX0_DPCSTX_PLL_UPDATE_DATA 71 71 #define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT 0x0 72 72 #define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK 0xFFFFFFFFL 73 - 73 + //DPCSTX0_DPCSTX_DEBUG_CONFIG 74 + #define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT 0xe 75 + #define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK 0x00004000L 74 76 75 77 // addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec 76 78 //RDPCSTX0_RDPCSTX_CNTL

+10

drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h

··· 155 155 #define regRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2 156 156 #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c 157 157 #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 158 + #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0x293d 159 + #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 158 160 #define regRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940 159 161 #define regRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2 160 162 #define regRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941 ··· 241 239 #define regRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2 242 240 #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14 243 241 #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 242 + #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0x2a15 243 + #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 244 244 #define regRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18 245 245 #define regRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2 246 246 #define regRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19 ··· 327 323 #define regRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX 2 328 324 #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2aec 329 325 #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 326 + #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0x2aed 327 + #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 330 328 #define regRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0 331 329 #define regRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2 332 330 #define regRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1 ··· 413 407 #define regRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX 2 414 408 #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2bc4 415 409 #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 410 + #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0x2bc5 411 + #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 416 412 #define regRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8 417 413 #define regRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2 418 414 #define regRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9 ··· 499 491 #define regRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX 2 500 492 #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2c9c 501 493 #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 494 + #define regRDPCSTX4_RDPCSTX_DEBUG_CONFIG 0x2c9d 495 + #define regRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 502 496 #define regRDPCSTX4_RDPCSTX_PHY_CNTL0 0x2ca0 503 497 #define regRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX 2 504 498 #define regRDPCSTX4_RDPCSTX_PHY_CNTL1 0x2ca1