dt-bindings: timer: meson6_timer: document the clock inputs

The Meson Timer IP has two clock inputs:
- pclk which is used as "system clock" timebase of Timer E
- xtal which is used for the 1us, 10us, 100us and 1ms timebases of Timer
A, B, C, D and E

The IP block has four internal dividers (XTAL is running at 24MHz):
- "xtal div 24" for 1us resolution
- "xtal div 240" for 10us resolution
- "xtal div 2400" for 100us resolution
- "xtal div 24000" for 1ms resolution

Suggested-by: Jianxin Pan <[e-mail]>
Signed-off-by: Martin Blumenstingl <[e-mail]>
Signed-off-by: Kevin Hilman <[e-mail]>

Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt

···
 - compatible : should be "amlogic,meson6-timer"
 - reg : Specifies base physical address and size of the registers.
 - interrupts : The four interrupts, one for each timer event
+- clocks : phandles to the pclk (system clock) and XTAL clocks
+- clock-names : must contain "pclk" and "xtal"
 
 Example:
 
···
 		     <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
 		     <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
 		     <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
+	clocks = <&xtal>, <&clk81>;
+	clock-names = "xtal", "pclk";
 };