tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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ARM: dts: bcm2837: Add the missing L1/L2 cache information

This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2837 on newer kernel versions.

Signed-off-by: Richard Schleich <rs@noreya.tech>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
[florian: Align and remove comments matching property values]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

authored by

Richard Schleich and committed by
Florian Fainelli bdf8762d 441d531e

+49
+49
arch/arm/boot/dts/bcm2837.dtsi
··· 40 40 #size-cells = <0>; 41 41 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 42 42 43 + /* Source for d/i-cache-line-size and d/i-cache-sets 44 + * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system 45 + * /about-the-l1-memory-system?lang=en 46 + * 47 + * Source for d/i-cache-size 48 + * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks 49 + */ 43 50 cpu0: cpu@0 { 44 51 device_type = "cpu"; 45 52 compatible = "arm,cortex-a53"; 46 53 reg = <0>; 47 54 enable-method = "spin-table"; 48 55 cpu-release-addr = <0x0 0x000000d8>; 56 + d-cache-size = <0x8000>; 57 + d-cache-line-size = <64>; 58 + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 59 + i-cache-size = <0x8000>; 60 + i-cache-line-size = <64>; 61 + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 62 + next-level-cache = <&l2>; 49 63 }; 50 64 51 65 cpu1: cpu@1 { ··· 68 54 reg = <1>; 69 55 enable-method = "spin-table"; 70 56 cpu-release-addr = <0x0 0x000000e0>; 57 + d-cache-size = <0x8000>; 58 + d-cache-line-size = <64>; 59 + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 60 + i-cache-size = <0x8000>; 61 + i-cache-line-size = <64>; 62 + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 63 + next-level-cache = <&l2>; 71 64 }; 72 65 73 66 cpu2: cpu@2 { ··· 83 62 reg = <2>; 84 63 enable-method = "spin-table"; 85 64 cpu-release-addr = <0x0 0x000000e8>; 65 + d-cache-size = <0x8000>; 66 + d-cache-line-size = <64>; 67 + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 68 + i-cache-size = <0x8000>; 69 + i-cache-line-size = <64>; 70 + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 71 + next-level-cache = <&l2>; 86 72 }; 87 73 88 74 cpu3: cpu@3 { ··· 98 70 reg = <3>; 99 71 enable-method = "spin-table"; 100 72 cpu-release-addr = <0x0 0x000000f0>; 73 + d-cache-size = <0x8000>; 74 + d-cache-line-size = <64>; 75 + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 76 + i-cache-size = <0x8000>; 77 + i-cache-line-size = <64>; 78 + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 79 + next-level-cache = <&l2>; 80 + }; 81 + 82 + /* Source for cache-line-size + cache-sets 83 + * https://developer.arm.com/documentation/ddi0500 84 + * /e/level-2-memory-system/about-the-l2-memory-system?lang=en 85 + * Source for cache-size 86 + * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf 87 + */ 88 + l2: l2-cache0 { 89 + compatible = "cache"; 90 + cache-size = <0x80000>; 91 + cache-line-size = <64>; 92 + cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set 93 + cache-level = <2>; 101 94 }; 102 95 }; 103 96 };