tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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gpio: Added support to Zynq Ultrascale+ MPSoC

Added support to Zynq Ultrascale+ MPSoC on the existing zynq
gpio driver.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Anurag Kumar Vulisha and committed by
Linus Walleij bdf7a4ae d342571e

+127 -68
+1 -1
Documentation/devicetree/bindings/gpio/gpio-zynq.txt
··· 6 6 - First cell is the GPIO line number 7 7 - Second cell is used to specify optional 8 8 parameters (unused) 9 - - compatible : Should be "xlnx,zynq-gpio-1.0" 9 + - compatible : Should be "xlnx,zynq-gpio-1.0" or "xlnx,zynqmp-gpio-1.0" 10 10 - clocks : Clock specifier (see clock bindings for details) 11 11 - gpio-controller : Marks the device node as a GPIO controller. 12 12 - interrupts : Interrupt specifier (see interrupt bindings for
+1 -1
drivers/gpio/Kconfig
··· 540 540 541 541 config GPIO_ZYNQ 542 542 tristate "Xilinx Zynq GPIO support" 543 - depends on ARCH_ZYNQ 543 + depends on ARCH_ZYNQ || ARCH_ZYNQMP 544 544 select GPIOLIB_IRQCHIP 545 545 help 546 546 Say yes here to support Xilinx Zynq GPIO controller.
+125 -66
drivers/gpio/gpio-zynq.c
··· 18 18 #include <linux/module.h> 19 19 #include <linux/platform_device.h> 20 20 #include <linux/pm_runtime.h> 21 + #include <linux/of.h> 21 22 22 23 #define DRIVER_NAME "zynq-gpio" 23 24 24 25 /* Maximum banks */ 25 26 #define ZYNQ_GPIO_MAX_BANK 4 27 + #define ZYNQMP_GPIO_MAX_BANK 6 26 28 27 29 #define ZYNQ_GPIO_BANK0_NGPIO 32 28 30 #define ZYNQ_GPIO_BANK1_NGPIO 22 29 31 #define ZYNQ_GPIO_BANK2_NGPIO 32 30 32 #define ZYNQ_GPIO_BANK3_NGPIO 32 31 33 32 - #define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \ 33 - ZYNQ_GPIO_BANK1_NGPIO + \ 34 - ZYNQ_GPIO_BANK2_NGPIO + \ 35 - ZYNQ_GPIO_BANK3_NGPIO) 34 + #define ZYNQMP_GPIO_BANK0_NGPIO 26 35 + #define ZYNQMP_GPIO_BANK1_NGPIO 26 36 + #define ZYNQMP_GPIO_BANK2_NGPIO 26 37 + #define ZYNQMP_GPIO_BANK3_NGPIO 32 38 + #define ZYNQMP_GPIO_BANK4_NGPIO 32 39 + #define ZYNQMP_GPIO_BANK5_NGPIO 32 36 40 37 - #define ZYNQ_GPIO_BANK0_PIN_MIN 0 38 - #define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \ 39 - ZYNQ_GPIO_BANK0_NGPIO - 1) 40 - #define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1) 41 - #define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \ 42 - ZYNQ_GPIO_BANK1_NGPIO - 1) 43 - #define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1) 44 - #define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \ 45 - ZYNQ_GPIO_BANK2_NGPIO - 1) 46 - #define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1) 47 - #define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \ 48 - ZYNQ_GPIO_BANK3_NGPIO - 1) 41 + #define ZYNQ_GPIO_NR_GPIOS 118 42 + #define ZYNQMP_GPIO_NR_GPIOS 174 43 + 44 + #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 45 + #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \ 46 + ZYNQ##str##_GPIO_BANK0_NGPIO - 1) 47 + #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) 48 + #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \ 49 + ZYNQ##str##_GPIO_BANK1_NGPIO - 1) 50 + #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) 51 + #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \ 52 + ZYNQ##str##_GPIO_BANK2_NGPIO - 1) 53 + #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) 54 + #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \ 55 + ZYNQ##str##_GPIO_BANK3_NGPIO - 1) 56 + #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) 57 + #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \ 58 + ZYNQ##str##_GPIO_BANK4_NGPIO - 1) 59 + #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) 60 + #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ 61 + ZYNQ##str##_GPIO_BANK5_NGPIO - 1) 49 62 50 63 51 64 /* Register offsets for the GPIO device */ ··· 102 89 * @base_addr: base address of the GPIO device 103 90 * @clk: clock resource for this controller 104 91 * @irq: interrupt for the GPIO device 92 + * @p_data: pointer to platform data 105 93 */ 106 94 struct zynq_gpio { 107 95 struct gpio_chip chip; 108 96 void __iomem *base_addr; 109 97 struct clk *clk; 110 98 int irq; 99 + const struct zynq_platform_data *p_data; 100 + }; 101 + 102 + /** 103 + * struct zynq_platform_data - zynq gpio platform data structure 104 + * @label: string to store in gpio->label 105 + * @ngpio: max number of gpio pins 106 + * @max_bank: maximum number of gpio banks 107 + * @bank_min: this array represents bank's min pin 108 + * @bank_max: this array represents bank's max pin 109 + */ 110 + struct zynq_platform_data { 111 + const char *label; 112 + u16 ngpio; 113 + int max_bank; 114 + int bank_min[ZYNQMP_GPIO_MAX_BANK]; 115 + int bank_max[ZYNQMP_GPIO_MAX_BANK]; 111 116 }; 112 117 113 118 static struct irq_chip zynq_gpio_level_irqchip; ··· 143 112 */ 144 113 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, 145 114 unsigned int *bank_num, 146 - unsigned int *bank_pin_num) 115 + unsigned int *bank_pin_num, 116 + struct zynq_gpio *gpio) 147 117 { 148 - switch (pin_num) { 149 - case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX: 150 - *bank_num = 0; 151 - *bank_pin_num = pin_num; 152 - break; 153 - case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX: 154 - *bank_num = 1; 155 - *bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN; 156 - break; 157 - case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX: 158 - *bank_num = 2; 159 - *bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN; 160 - break; 161 - case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX: 162 - *bank_num = 3; 163 - *bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN; 164 - break; 165 - default: 166 - WARN(true, "invalid GPIO pin number: %u", pin_num); 167 - *bank_num = 0; 168 - *bank_pin_num = 0; 169 - break; 170 - } 171 - } 118 + int bank; 172 119 173 - static const unsigned int zynq_gpio_bank_offset[] = { 174 - ZYNQ_GPIO_BANK0_PIN_MIN, 175 - ZYNQ_GPIO_BANK1_PIN_MIN, 176 - ZYNQ_GPIO_BANK2_PIN_MIN, 177 - ZYNQ_GPIO_BANK3_PIN_MIN, 178 - }; 120 + for (bank = 0; bank < gpio->p_data->max_bank; bank++) { 121 + if ((pin_num >= gpio->p_data->bank_min[bank]) && 122 + (pin_num <= gpio->p_data->bank_max[bank])) { 123 + *bank_num = bank; 124 + *bank_pin_num = pin_num - 125 + gpio->p_data->bank_min[bank]; 126 + return; 127 + } 128 + } 129 + 130 + /* default */ 131 + WARN(true, "invalid GPIO pin number: %u", pin_num); 132 + *bank_num = 0; 133 + *bank_pin_num = 0; 134 + } 179 135 180 136 /** 181 137 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device ··· 179 161 unsigned int bank_num, bank_pin_num; 180 162 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); 181 163 182 - zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); 164 + zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 183 165 184 166 data = readl_relaxed(gpio->base_addr + 185 167 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); ··· 203 185 unsigned int reg_offset, bank_num, bank_pin_num; 204 186 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); 205 187 206 - zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); 188 + zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 207 189 208 190 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { 209 191 /* only 16 data bits in bit maskable reg */ ··· 240 222 unsigned int bank_num, bank_pin_num; 241 223 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); 242 224 243 - zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); 225 + zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 244 226 245 227 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */ 246 228 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) ··· 273 255 unsigned int bank_num, bank_pin_num; 274 256 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); 275 257 276 - zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); 258 + zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 277 259 278 260 /* set the GPIO pin as output */ 279 261 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); ··· 304 286 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data); 305 287 306 288 device_pin_num = irq_data->hwirq; 307 - zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); 289 + zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 308 290 writel_relaxed(BIT(bank_pin_num), 309 291 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); 310 292 } ··· 324 306 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data); 325 307 326 308 device_pin_num = irq_data->hwirq; 327 - zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); 309 + zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 328 310 writel_relaxed(BIT(bank_pin_num), 329 311 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); 330 312 } ··· 343 325 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data); 344 326 345 327 device_pin_num = irq_data->hwirq; 346 - zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); 328 + zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 347 329 writel_relaxed(BIT(bank_pin_num), 348 330 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); 349 331 } ··· 393 375 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data); 394 376 395 377 device_pin_num = irq_data->hwirq; 396 - zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); 378 + zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 397 379 398 380 int_type = readl_relaxed(gpio->base_addr + 399 381 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); ··· 488 470 unsigned int bank_num, 489 471 unsigned long pending) 490 472 { 491 - unsigned int bank_offset = zynq_gpio_bank_offset[bank_num]; 473 + unsigned int bank_offset = gpio->p_data->bank_min[bank_num]; 492 474 struct irq_domain *irqdomain = gpio->chip.irqdomain; 493 475 int offset; 494 476 ··· 523 505 524 506 chained_irq_enter(irqchip, desc); 525 507 526 - for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++) { 508 + for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { 527 509 int_sts = readl_relaxed(gpio->base_addr + 528 510 ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); 529 511 int_enb = readl_relaxed(gpio->base_addr + ··· 600 582 zynq_gpio_runtime_resume, NULL) 601 583 }; 602 584 585 + static const struct zynq_platform_data zynqmp_gpio_def = { 586 + .label = "zynqmp_gpio", 587 + .ngpio = ZYNQMP_GPIO_NR_GPIOS, 588 + .max_bank = ZYNQMP_GPIO_MAX_BANK, 589 + .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), 590 + .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), 591 + .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), 592 + .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), 593 + .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), 594 + .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), 595 + .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), 596 + .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), 597 + .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), 598 + .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), 599 + .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), 600 + .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), 601 + }; 602 + 603 + static const struct zynq_platform_data zynq_gpio_def = { 604 + .label = "zynq_gpio", 605 + .ngpio = ZYNQ_GPIO_NR_GPIOS, 606 + .max_bank = ZYNQ_GPIO_MAX_BANK, 607 + .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), 608 + .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), 609 + .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), 610 + .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), 611 + .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), 612 + .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), 613 + .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), 614 + .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), 615 + }; 616 + 617 + static const struct of_device_id zynq_gpio_of_match[] = { 618 + { .compatible = "xlnx,zynq-gpio-1.0", .data = (void *)&zynq_gpio_def }, 619 + { .compatible = "xlnx,zynqmp-gpio-1.0", 620 + .data = (void *)&zynqmp_gpio_def }, 621 + { /* end of table */ } 622 + }; 623 + MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); 624 + 603 625 /** 604 626 * zynq_gpio_probe - Initialization method for a zynq_gpio device 605 627 * @pdev: platform device instance ··· 657 599 struct zynq_gpio *gpio; 658 600 struct gpio_chip *chip; 659 601 struct resource *res; 602 + const struct of_device_id *match; 660 603 661 604 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 662 605 if (!gpio) 663 606 return -ENOMEM; 664 607 608 + match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node); 609 + if (!match) { 610 + dev_err(&pdev->dev, "of_match_node() failed\n"); 611 + return -EINVAL; 612 + } 613 + gpio->p_data = match->data; 665 614 platform_set_drvdata(pdev, gpio); 666 615 667 616 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ··· 684 619 685 620 /* configure the gpio chip */ 686 621 chip = &gpio->chip; 687 - chip->label = "zynq_gpio"; 622 + chip->label = gpio->p_data->label; 688 623 chip->owner = THIS_MODULE; 689 624 chip->dev = &pdev->dev; 690 625 chip->get = zynq_gpio_get_value; ··· 694 629 chip->direction_input = zynq_gpio_dir_in; 695 630 chip->direction_output = zynq_gpio_dir_out; 696 631 chip->base = -1; 697 - chip->ngpio = ZYNQ_GPIO_NR_GPIOS; 632 + chip->ngpio = gpio->p_data->ngpio; 698 633 699 634 /* Enable GPIO clock */ 700 635 gpio->clk = devm_clk_get(&pdev->dev, NULL); ··· 716 651 } 717 652 718 653 /* disable interrupts for all banks */ 719 - for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++) 654 + for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) 720 655 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + 721 656 ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); 722 657 ··· 759 694 device_set_wakeup_capable(&pdev->dev, 0); 760 695 return 0; 761 696 } 762 - 763 - static struct of_device_id zynq_gpio_of_match[] = { 764 - { .compatible = "xlnx,zynq-gpio-1.0", }, 765 - { /* end of table */ } 766 - }; 767 - MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); 768 697 769 698 static struct platform_driver zynq_gpio_driver = { 770 699 .driver = {