···1717 "core" - Main peripheral bus clock1818 "clkin0" - Parent clock of internal mux1919 "clkin1" - Other parent clock of internal mux2020- The driver has an interal mux clock which switches between clkin0 and clkin1 depending on the2020+ The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the2121 clock rate requested by the MMC core.22222323Example:
···3838- bus-width: Number of data lines.3939 See: Documentation/devicetree/bindings/mmc/mmc.txt.40404141-- max-frequency: Can be 200MHz, 100Mz or 50MHz (default) and used for4141+- max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for4242 configuring the CCONFIG3 in the mmcss.4343 See: Documentation/devicetree/bindings/mmc/mmc.txt.4444
+1-1
Documentation/devicetree/bindings/mmc/sdhci.txt
···5566Optional properties:77- sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit88- property corresponds to the bits in the sdhci capabilty register. If the bit88+ property corresponds to the bits in the sdhci capability register. If the bit99 is on in the mask then the bit is incorrect in the register and should be1010 turned off, before applying sdhci-caps.1111- sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
···1616 each child-node representing a supported slot. There should be atleast one1717 child node representing a card slot. The name of the child node representing1818 the slot is recommended to be slot@n where n is the unique number of the slot1919- connnected to the controller. The following are optional properties which1919+ connected to the controller. The following are optional properties which2020 can be included in the slot child node.21212222 * reg: specifies the physical slot number. The valid values of this