tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
x86, cpu: Support the features flags in new CPUID leaf 7
Intel has defined CPUID leaf 7 as the next set of feature flags (see
the AVX specification, version 007). Add support for this new feature
flags word.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
LKML-Reference: <tip-*@vger.kernel.org>
+21
-4
+9
-4
arch/x86/include/asm/cpufeature.h
+9
-4
arch/x86/include/asm/cpufeature.h
···
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#include <asm/required-features.h>
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-
#define NCAPINTS 9 /* N 32-bit words worth of info */
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+
#define NCAPINTS 10 /* N 32-bit words worth of info */
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/*
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* Note: If the comment begins with a quoted string, that string is used
···
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/*
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* Auxiliary flags: Linux defined - For features scattered in various
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-
* CPUID levels like 0x6, 0xA etc
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* CPUID levels like 0x6, 0xA etc, word 7
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*/
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#define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */
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#define X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */
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#define X86_FEATURE_CPB (7*32+ 2) /* AMD Core Performance Boost */
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#define X86_FEATURE_EPB (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
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-
/* Virtualization flags: Linux defined */
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */
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#define X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */
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#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
···
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#define X86_FEATURE_LBRV (8*32+6) /* AMD LBR Virtualization support */
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#define X86_FEATURE_SVML (8*32+7) /* "svm_lock" AMD SVM locking MSR */
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#define X86_FEATURE_NRIPS (8*32+8) /* "nrip_save" AMD SVM next_rip save */
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
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#define X86_FEATURE_FSGSBASE (9*32+0) /* {RD/WR}{FS/GS}BASE instructions*/
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#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
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···
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(((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \
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(((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \
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(((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \
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(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \
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(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \
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(((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \
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(((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) ) \
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? 1 : \
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test_cpu_cap(c, bit))
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+2
arch/x86/include/asm/required-features.h
+2
arch/x86/include/asm/required-features.h
+10
arch/x86/kernel/cpu/common.c
+10
arch/x86/kernel/cpu/common.c
···
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c->x86_capability[4] = excap;
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}
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+
/* Additional Intel-defined flags: level 0x00000007 */
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if (c->cpuid_level >= 0x00000007) {
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u32 eax, ebx, ecx, edx;
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cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
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if (eax > 0)
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c->x86_capability[9] = ebx;
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}
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/* AMD-defined flags: level 0x80000001 */
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xlvl = cpuid_eax(0x80000000);
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c->extended_cpuid_level = xlvl;