tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: rockchip: set the clock ids for RK3228 HDMI

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

authored by

Yakir Yang and committed by
Heiko Stuebner bdc7deec 0a9d4ac0

+4 -4
+4 -4
drivers/clk/rockchip/clk-rk3228.c
··· 285 285 RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS, 286 286 RK2928_CLKGATE_CON(3), 5, GFLAGS), 287 287 288 - GATE(0, "sclk_hdmi_hdcp", "xin24m", 0, 288 + GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, 289 289 RK2928_CLKGATE_CON(3), 7, GFLAGS), 290 290 291 291 COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0, ··· 364 364 RK2928_CLKGATE_CON(3), 1, GFLAGS), 365 365 MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0, 366 366 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS), 367 - DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0, 367 + DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0, 368 368 RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), 369 369 DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, 370 370 RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), ··· 519 519 GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS), 520 520 GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS), 521 521 GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS), 522 - GATE(0, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS), 522 + GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS), 523 523 GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS), 524 524 GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS), 525 525 ··· 592 592 593 593 GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS), 594 594 GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS), 595 - GATE(0, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS), 595 + GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS), 596 596 GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS), 597 597 GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS), 598 598