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phy: rockchip: phy-rockchip-inno-csidphy: add support for rk3588 variant

The Rockchip RK3588 MIPI CSI-2 DPHY can be supported using the existing
phy-rockchip-inno-csidphy driver, the notable differences being
- the control bits in the GRF
- the additional reset line
Add support for this variant.

Signed-off-by: Michael Riesch <michael.riesch@collabora.com>
Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-6-a4f340a7f0cf@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Michael Riesch and committed by
Vinod Koul
bdb97897 26043515

+28
+28
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
··· 30 30 #define RK3568_GRF_VI_CON0 0x0340 31 31 #define RK3568_GRF_VI_CON1 0x0344 32 32 33 + #define RK3588_CSIDPHY_GRF_CON0 0x0000 34 + 33 35 /* PHY */ 34 36 #define CSIDPHY_CTRL_LANE_ENABLE 0x00 35 37 #define CSIDPHY_CTRL_LANE_ENABLE_CK BIT(6) ··· 119 117 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3568_GRF_VI_CON0, 1, 8), 120 118 }; 121 119 120 + static const struct dphy_reg rk3588_grf_dphy_regs[] = { 121 + [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 0), 122 + [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 4), 123 + [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3588_CSIDPHY_GRF_CON0, 1, 8), 124 + }; 125 + 122 126 struct hsfreq_range { 123 127 u32 range_h; 124 128 u8 cfg_bit; ··· 189 181 190 182 static const char *const rk3368_reset_names[] = { 191 183 "apb" 184 + }; 185 + 186 + static const char *const rk3588_reset_names[] = { 187 + "apb", 188 + "phy" 192 189 }; 193 190 194 191 static void rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy *priv, ··· 403 390 .resets_num = ARRAY_SIZE(rk3368_reset_names), 404 391 }; 405 392 393 + static const struct dphy_drv_data rk3588_mipidphy_drv_data = { 394 + .pwrctl_offset = -1, 395 + .ths_settle_offset = RK3568_CSIDPHY_CLK_WR_THS_SETTLE, 396 + .calib_offset = RK3568_CSIDPHY_CLK_CALIB_EN, 397 + .hsfreq_ranges = rk1808_mipidphy_hsfreq_ranges, 398 + .num_hsfreq_ranges = ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), 399 + .grf_regs = rk3588_grf_dphy_regs, 400 + .resets = rk3588_reset_names, 401 + .resets_num = ARRAY_SIZE(rk3588_reset_names), 402 + }; 403 + 406 404 static const struct of_device_id rockchip_inno_csidphy_match_id[] = { 407 405 { 408 406 .compatible = "rockchip,px30-csi-dphy", ··· 434 410 { 435 411 .compatible = "rockchip,rk3568-csi-dphy", 436 412 .data = &rk3568_mipidphy_drv_data, 413 + }, 414 + { 415 + .compatible = "rockchip,rk3588-csi-dphy", 416 + .data = &rk3588_mipidphy_drv_data, 437 417 }, 438 418 {} 439 419 };