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[SCSI] mvumi: Add support for Marvell SAS/SATA RAID-on-Chip(ROC) 88RC9580

[jejb: fix up for spelling correction patch]
Signed-off-by: Shun Fu <fushun@marvell.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>

authored by

Shun Fu and committed by
James Bottomley bd756dde 08bc166d

+1070 -262
+916 -177
drivers/scsi/mvumi.c
··· 35 35 #include <linux/io.h> 36 36 #include <scsi/scsi.h> 37 37 #include <scsi/scsi_cmnd.h> 38 + #include <scsi/scsi_device.h> 38 39 #include <scsi/scsi_host.h> 39 40 #include <scsi/scsi_transport.h> 40 41 #include <scsi/scsi_eh.h> 41 42 #include <linux/uaccess.h> 43 + #include <linux/kthread.h> 42 44 43 45 #include "mvumi.h" 44 46 ··· 50 48 51 49 static DEFINE_PCI_DEVICE_TABLE(mvumi_pci_table) = { 52 50 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_2, PCI_DEVICE_ID_MARVELL_MV9143) }, 51 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_2, PCI_DEVICE_ID_MARVELL_MV9580) }, 53 52 { 0 } 54 53 }; 55 54 ··· 121 118 static struct mvumi_res *mvumi_alloc_mem_resource(struct mvumi_hba *mhba, 122 119 enum resource_type type, unsigned int size) 123 120 { 124 - struct mvumi_res *res = kzalloc(sizeof(*res), GFP_KERNEL); 121 + struct mvumi_res *res = kzalloc(sizeof(*res), GFP_ATOMIC); 125 122 126 123 if (!res) { 127 124 dev_err(&mhba->pdev->dev, ··· 131 128 132 129 switch (type) { 133 130 case RESOURCE_CACHED_MEMORY: 134 - res->virt_addr = kzalloc(size, GFP_KERNEL); 131 + res->virt_addr = kzalloc(size, GFP_ATOMIC); 135 132 if (!res->virt_addr) { 136 133 dev_err(&mhba->pdev->dev, 137 134 "unable to allocate memory,size = %d.\n", size); ··· 225 222 m_sg->baseaddr_l = cpu_to_le32(lower_32_bits(busaddr)); 226 223 m_sg->baseaddr_h = cpu_to_le32(upper_32_bits(busaddr)); 227 224 m_sg->flags = 0; 228 - m_sg->size = cpu_to_le32(sg_dma_len(&sg[i])); 225 + sgd_setsz(mhba, m_sg, cpu_to_le32(sg_dma_len(&sg[i]))); 229 226 if ((i + 1) == *sg_count) 230 - m_sg->flags |= SGD_EOT; 227 + m_sg->flags |= 1U << mhba->eot_flag; 231 228 232 - m_sg++; 229 + sgd_inc(mhba, m_sg); 233 230 } 234 231 } else { 235 232 scmd->SCp.dma_handle = scsi_bufflen(scmd) ? ··· 240 237 busaddr = scmd->SCp.dma_handle; 241 238 m_sg->baseaddr_l = cpu_to_le32(lower_32_bits(busaddr)); 242 239 m_sg->baseaddr_h = cpu_to_le32(upper_32_bits(busaddr)); 243 - m_sg->flags = SGD_EOT; 244 - m_sg->size = cpu_to_le32(scsi_bufflen(scmd)); 240 + m_sg->flags = 1U << mhba->eot_flag; 241 + sgd_setsz(mhba, m_sg, cpu_to_le32(scsi_bufflen(scmd))); 245 242 *sg_count = 1; 246 243 } 247 244 ··· 270 267 271 268 m_sg->baseaddr_l = cpu_to_le32(lower_32_bits(phy_addr)); 272 269 m_sg->baseaddr_h = cpu_to_le32(upper_32_bits(phy_addr)); 273 - m_sg->flags = SGD_EOT; 274 - m_sg->size = cpu_to_le32(size); 270 + m_sg->flags = 1U << mhba->eot_flag; 271 + sgd_setsz(mhba, m_sg, cpu_to_le32(size)); 275 272 276 273 return 0; 277 274 } ··· 288 285 } 289 286 INIT_LIST_HEAD(&cmd->queue_pointer); 290 287 291 - cmd->frame = kzalloc(mhba->ib_max_size, GFP_KERNEL); 288 + cmd->frame = pci_alloc_consistent(mhba->pdev, 289 + mhba->ib_max_size, &cmd->frame_phys); 292 290 if (!cmd->frame) { 293 291 dev_err(&mhba->pdev->dev, "failed to allocate memory for FW" 294 292 " frame,size = %d.\n", mhba->ib_max_size); ··· 301 297 if (mvumi_internal_cmd_sgl(mhba, cmd, buf_size)) { 302 298 dev_err(&mhba->pdev->dev, "failed to allocate memory" 303 299 " for internal frame\n"); 304 - kfree(cmd->frame); 300 + pci_free_consistent(mhba->pdev, mhba->ib_max_size, 301 + cmd->frame, cmd->frame_phys); 305 302 kfree(cmd); 306 303 return NULL; 307 304 } ··· 322 317 if (cmd && cmd->frame) { 323 318 if (cmd->frame->sg_counts) { 324 319 m_sg = (struct mvumi_sgl *) &cmd->frame->payload[0]; 325 - size = m_sg->size; 320 + sgd_getsz(mhba, m_sg, size); 326 321 327 322 phy_addr = (dma_addr_t) m_sg->baseaddr_l | 328 323 (dma_addr_t) ((m_sg->baseaddr_h << 16) << 16); ··· 330 325 pci_free_consistent(mhba->pdev, size, cmd->data_buf, 331 326 phy_addr); 332 327 } 333 - kfree(cmd->frame); 328 + pci_free_consistent(mhba->pdev, mhba->ib_max_size, 329 + cmd->frame, cmd->frame_phys); 334 330 kfree(cmd); 335 331 } 336 332 } ··· 380 374 cmd = list_first_entry(&mhba->cmd_pool, struct mvumi_cmd, 381 375 queue_pointer); 382 376 list_del(&cmd->queue_pointer); 383 - kfree(cmd->frame); 377 + if (!(mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC)) 378 + kfree(cmd->frame); 384 379 kfree(cmd); 385 380 } 386 381 } ··· 403 396 404 397 INIT_LIST_HEAD(&cmd->queue_pointer); 405 398 list_add_tail(&cmd->queue_pointer, &mhba->cmd_pool); 406 - cmd->frame = kzalloc(mhba->ib_max_size, GFP_KERNEL); 399 + if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC) { 400 + cmd->frame = mhba->ib_frame + i * mhba->ib_max_size; 401 + cmd->frame_phys = mhba->ib_frame_phys 402 + + i * mhba->ib_max_size; 403 + } else 404 + cmd->frame = kzalloc(mhba->ib_max_size, GFP_KERNEL); 407 405 if (!cmd->frame) 408 406 goto err_exit; 409 407 } ··· 421 409 cmd = list_first_entry(&mhba->cmd_pool, struct mvumi_cmd, 422 410 queue_pointer); 423 411 list_del(&cmd->queue_pointer); 424 - kfree(cmd->frame); 412 + if (!(mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC)) 413 + kfree(cmd->frame); 425 414 kfree(cmd); 426 415 } 427 416 return -ENOMEM; 428 417 } 429 418 430 - static int mvumi_get_ib_list_entry(struct mvumi_hba *mhba, void **ib_entry) 419 + static unsigned int mvumi_check_ib_list_9143(struct mvumi_hba *mhba) 431 420 { 432 - unsigned int ib_rp_reg, cur_ib_entry; 421 + unsigned int ib_rp_reg; 422 + struct mvumi_hw_regs *regs = mhba->regs; 433 423 424 + ib_rp_reg = ioread32(mhba->regs->inb_read_pointer); 425 + 426 + if (unlikely(((ib_rp_reg & regs->cl_slot_num_mask) == 427 + (mhba->ib_cur_slot & regs->cl_slot_num_mask)) && 428 + ((ib_rp_reg & regs->cl_pointer_toggle) 429 + != (mhba->ib_cur_slot & regs->cl_pointer_toggle)))) { 430 + dev_warn(&mhba->pdev->dev, "no free slot to use.\n"); 431 + return 0; 432 + } 434 433 if (atomic_read(&mhba->fw_outstanding) >= mhba->max_io) { 435 434 dev_warn(&mhba->pdev->dev, "firmware io overflow.\n"); 436 - return -1; 435 + return 0; 436 + } else { 437 + return mhba->max_io - atomic_read(&mhba->fw_outstanding); 437 438 } 438 - ib_rp_reg = ioread32(mhba->mmio + CLA_INB_READ_POINTER); 439 + } 439 440 440 - if (unlikely(((ib_rp_reg & CL_SLOT_NUM_MASK) == 441 - (mhba->ib_cur_slot & CL_SLOT_NUM_MASK)) && 442 - ((ib_rp_reg & CL_POINTER_TOGGLE) != 443 - (mhba->ib_cur_slot & CL_POINTER_TOGGLE)))) { 444 - dev_warn(&mhba->pdev->dev, "no free slot to use.\n"); 445 - return -1; 446 - } 441 + static unsigned int mvumi_check_ib_list_9580(struct mvumi_hba *mhba) 442 + { 443 + unsigned int count; 444 + if (atomic_read(&mhba->fw_outstanding) >= (mhba->max_io - 1)) 445 + return 0; 446 + count = ioread32(mhba->ib_shadow); 447 + if (count == 0xffff) 448 + return 0; 449 + return count; 450 + } 447 451 448 - cur_ib_entry = mhba->ib_cur_slot & CL_SLOT_NUM_MASK; 452 + static void mvumi_get_ib_list_entry(struct mvumi_hba *mhba, void **ib_entry) 453 + { 454 + unsigned int cur_ib_entry; 455 + 456 + cur_ib_entry = mhba->ib_cur_slot & mhba->regs->cl_slot_num_mask; 449 457 cur_ib_entry++; 450 458 if (cur_ib_entry >= mhba->list_num_io) { 451 459 cur_ib_entry -= mhba->list_num_io; 452 - mhba->ib_cur_slot ^= CL_POINTER_TOGGLE; 460 + mhba->ib_cur_slot ^= mhba->regs->cl_pointer_toggle; 453 461 } 454 - mhba->ib_cur_slot &= ~CL_SLOT_NUM_MASK; 455 - mhba->ib_cur_slot |= (cur_ib_entry & CL_SLOT_NUM_MASK); 456 - *ib_entry = mhba->ib_list + cur_ib_entry * mhba->ib_max_size; 462 + mhba->ib_cur_slot &= ~mhba->regs->cl_slot_num_mask; 463 + mhba->ib_cur_slot |= (cur_ib_entry & mhba->regs->cl_slot_num_mask); 464 + if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC) { 465 + *ib_entry = mhba->ib_list + cur_ib_entry * 466 + sizeof(struct mvumi_dyn_list_entry); 467 + } else { 468 + *ib_entry = mhba->ib_list + cur_ib_entry * mhba->ib_max_size; 469 + } 457 470 atomic_inc(&mhba->fw_outstanding); 458 - 459 - return 0; 460 471 } 461 472 462 473 static void mvumi_send_ib_list_entry(struct mvumi_hba *mhba) 463 474 { 464 - iowrite32(0xfff, mhba->ib_shadow); 465 - iowrite32(mhba->ib_cur_slot, mhba->mmio + CLA_INB_WRITE_POINTER); 475 + iowrite32(0xffff, mhba->ib_shadow); 476 + iowrite32(mhba->ib_cur_slot, mhba->regs->inb_write_pointer); 466 477 } 467 478 468 479 static char mvumi_check_ob_frame(struct mvumi_hba *mhba, ··· 515 480 return 0; 516 481 } 517 482 483 + static int mvumi_check_ob_list_9143(struct mvumi_hba *mhba, 484 + unsigned int *cur_obf, unsigned int *assign_obf_end) 485 + { 486 + unsigned int ob_write, ob_write_shadow; 487 + struct mvumi_hw_regs *regs = mhba->regs; 488 + 489 + do { 490 + ob_write = ioread32(regs->outb_copy_pointer); 491 + ob_write_shadow = ioread32(mhba->ob_shadow); 492 + } while ((ob_write & regs->cl_slot_num_mask) != ob_write_shadow); 493 + 494 + *cur_obf = mhba->ob_cur_slot & mhba->regs->cl_slot_num_mask; 495 + *assign_obf_end = ob_write & mhba->regs->cl_slot_num_mask; 496 + 497 + if ((ob_write & regs->cl_pointer_toggle) != 498 + (mhba->ob_cur_slot & regs->cl_pointer_toggle)) { 499 + *assign_obf_end += mhba->list_num_io; 500 + } 501 + return 0; 502 + } 503 + 504 + static int mvumi_check_ob_list_9580(struct mvumi_hba *mhba, 505 + unsigned int *cur_obf, unsigned int *assign_obf_end) 506 + { 507 + unsigned int ob_write; 508 + struct mvumi_hw_regs *regs = mhba->regs; 509 + 510 + ob_write = ioread32(regs->outb_read_pointer); 511 + ob_write = ioread32(regs->outb_copy_pointer); 512 + *cur_obf = mhba->ob_cur_slot & mhba->regs->cl_slot_num_mask; 513 + *assign_obf_end = ob_write & mhba->regs->cl_slot_num_mask; 514 + if (*assign_obf_end < *cur_obf) 515 + *assign_obf_end += mhba->list_num_io; 516 + else if (*assign_obf_end == *cur_obf) 517 + return -1; 518 + return 0; 519 + } 520 + 518 521 static void mvumi_receive_ob_list_entry(struct mvumi_hba *mhba) 519 522 { 520 - unsigned int ob_write_reg, ob_write_shadow_reg; 521 523 unsigned int cur_obf, assign_obf_end, i; 522 524 struct mvumi_ob_data *ob_data; 523 525 struct mvumi_rsp_frame *p_outb_frame; 526 + struct mvumi_hw_regs *regs = mhba->regs; 524 527 525 - do { 526 - ob_write_reg = ioread32(mhba->mmio + CLA_OUTB_COPY_POINTER); 527 - ob_write_shadow_reg = ioread32(mhba->ob_shadow); 528 - } while ((ob_write_reg & CL_SLOT_NUM_MASK) != ob_write_shadow_reg); 529 - 530 - cur_obf = mhba->ob_cur_slot & CL_SLOT_NUM_MASK; 531 - assign_obf_end = ob_write_reg & CL_SLOT_NUM_MASK; 532 - 533 - if ((ob_write_reg & CL_POINTER_TOGGLE) != 534 - (mhba->ob_cur_slot & CL_POINTER_TOGGLE)) { 535 - assign_obf_end += mhba->list_num_io; 536 - } 528 + if (mhba->instancet->check_ob_list(mhba, &cur_obf, &assign_obf_end)) 529 + return; 537 530 538 531 for (i = (assign_obf_end - cur_obf); i != 0; i--) { 539 532 cur_obf++; 540 533 if (cur_obf >= mhba->list_num_io) { 541 534 cur_obf -= mhba->list_num_io; 542 - mhba->ob_cur_slot ^= CL_POINTER_TOGGLE; 535 + mhba->ob_cur_slot ^= regs->cl_pointer_toggle; 543 536 } 544 537 545 538 p_outb_frame = mhba->ob_list + cur_obf * mhba->ob_max_size; ··· 591 528 ob_data = NULL; 592 529 if (cur_obf == 0) { 593 530 cur_obf = mhba->list_num_io - 1; 594 - mhba->ob_cur_slot ^= CL_POINTER_TOGGLE; 531 + mhba->ob_cur_slot ^= regs->cl_pointer_toggle; 595 532 } else 596 533 cur_obf -= 1; 597 534 break; ··· 602 539 603 540 list_add_tail(&ob_data->list, &mhba->free_ob_list); 604 541 } 605 - mhba->ob_cur_slot &= ~CL_SLOT_NUM_MASK; 606 - mhba->ob_cur_slot |= (cur_obf & CL_SLOT_NUM_MASK); 607 - iowrite32(mhba->ob_cur_slot, mhba->mmio + CLA_OUTB_READ_POINTER); 542 + mhba->ob_cur_slot &= ~regs->cl_slot_num_mask; 543 + mhba->ob_cur_slot |= (cur_obf & regs->cl_slot_num_mask); 544 + iowrite32(mhba->ob_cur_slot, regs->outb_read_pointer); 608 545 } 609 546 610 - static void mvumi_reset(void *regs) 547 + static void mvumi_reset(struct mvumi_hba *mhba) 611 548 { 612 - iowrite32(0, regs + CPU_ENPOINTA_MASK_REG); 613 - if (ioread32(regs + CPU_ARM_TO_PCIEA_MSG1) != HANDSHAKE_DONESTATE) 549 + struct mvumi_hw_regs *regs = mhba->regs; 550 + 551 + iowrite32(0, regs->enpointa_mask_reg); 552 + if (ioread32(regs->arm_to_pciea_msg1) != HANDSHAKE_DONESTATE) 614 553 return; 615 554 616 - iowrite32(DRBL_SOFT_RESET, regs + CPU_PCIEA_TO_ARM_DRBL_REG); 555 + iowrite32(DRBL_SOFT_RESET, regs->pciea_to_arm_drbl_reg); 617 556 } 618 557 619 558 static unsigned char mvumi_start(struct mvumi_hba *mhba); ··· 623 558 static int mvumi_wait_for_outstanding(struct mvumi_hba *mhba) 624 559 { 625 560 mhba->fw_state = FW_STATE_ABORT; 626 - mvumi_reset(mhba->mmio); 561 + mvumi_reset(mhba); 627 562 628 563 if (mvumi_start(mhba)) 629 564 return FAILED; 630 565 else 631 566 return SUCCESS; 567 + } 568 + 569 + static int mvumi_wait_for_fw(struct mvumi_hba *mhba) 570 + { 571 + struct mvumi_hw_regs *regs = mhba->regs; 572 + u32 tmp; 573 + unsigned long before; 574 + before = jiffies; 575 + 576 + iowrite32(0, regs->enpointa_mask_reg); 577 + tmp = ioread32(regs->arm_to_pciea_msg1); 578 + while (tmp != HANDSHAKE_READYSTATE) { 579 + iowrite32(DRBL_MU_RESET, regs->pciea_to_arm_drbl_reg); 580 + if (time_after(jiffies, before + FW_MAX_DELAY * HZ)) { 581 + dev_err(&mhba->pdev->dev, 582 + "FW reset failed [0x%x].\n", tmp); 583 + return FAILED; 584 + } 585 + 586 + msleep(500); 587 + rmb(); 588 + tmp = ioread32(regs->arm_to_pciea_msg1); 589 + } 590 + 591 + return SUCCESS; 592 + } 593 + 594 + static void mvumi_backup_bar_addr(struct mvumi_hba *mhba) 595 + { 596 + unsigned char i; 597 + 598 + for (i = 0; i < MAX_BASE_ADDRESS; i++) { 599 + pci_read_config_dword(mhba->pdev, 0x10 + i * 4, 600 + &mhba->pci_base[i]); 601 + } 602 + } 603 + 604 + static void mvumi_restore_bar_addr(struct mvumi_hba *mhba) 605 + { 606 + unsigned char i; 607 + 608 + for (i = 0; i < MAX_BASE_ADDRESS; i++) { 609 + if (mhba->pci_base[i]) 610 + pci_write_config_dword(mhba->pdev, 0x10 + i * 4, 611 + mhba->pci_base[i]); 612 + } 613 + } 614 + 615 + static unsigned int mvumi_pci_set_master(struct pci_dev *pdev) 616 + { 617 + unsigned int ret = 0; 618 + pci_set_master(pdev); 619 + 620 + if (IS_DMA64) { 621 + if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) 622 + ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 623 + } else 624 + ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 625 + 626 + return ret; 627 + } 628 + 629 + static int mvumi_reset_host_9580(struct mvumi_hba *mhba) 630 + { 631 + mhba->fw_state = FW_STATE_ABORT; 632 + 633 + iowrite32(0, mhba->regs->reset_enable); 634 + iowrite32(0xf, mhba->regs->reset_request); 635 + 636 + iowrite32(0x10, mhba->regs->reset_enable); 637 + iowrite32(0x10, mhba->regs->reset_request); 638 + msleep(100); 639 + pci_disable_device(mhba->pdev); 640 + 641 + if (pci_enable_device(mhba->pdev)) { 642 + dev_err(&mhba->pdev->dev, "enable device failed\n"); 643 + return FAILED; 644 + } 645 + if (mvumi_pci_set_master(mhba->pdev)) { 646 + dev_err(&mhba->pdev->dev, "set master failed\n"); 647 + return FAILED; 648 + } 649 + mvumi_restore_bar_addr(mhba); 650 + if (mvumi_wait_for_fw(mhba) == FAILED) 651 + return FAILED; 652 + 653 + return mvumi_wait_for_outstanding(mhba); 654 + } 655 + 656 + static int mvumi_reset_host_9143(struct mvumi_hba *mhba) 657 + { 658 + return mvumi_wait_for_outstanding(mhba); 632 659 } 633 660 634 661 static int mvumi_host_reset(struct scsi_cmnd *scmd) ··· 732 575 scmd_printk(KERN_NOTICE, scmd, "RESET -%ld cmd=%x retries=%x\n", 733 576 scmd->serial_number, scmd->cmnd[0], scmd->retries); 734 577 735 - return mvumi_wait_for_outstanding(mhba); 578 + return mhba->instancet->reset_host(mhba); 736 579 } 737 580 738 581 static int mvumi_issue_blocked_cmd(struct mvumi_hba *mhba, ··· 785 628 mvumi_free_cmds(mhba); 786 629 mvumi_release_mem_resource(mhba); 787 630 mvumi_unmap_pci_addr(mhba->pdev, mhba->base_addr); 788 - kfree(mhba->handshake_page); 631 + pci_free_consistent(mhba->pdev, HSP_MAX_SIZE, 632 + mhba->handshake_page, mhba->handshake_page_phys); 633 + kfree(mhba->regs); 789 634 pci_release_regions(mhba->pdev); 790 635 } 791 636 ··· 824 665 frame->cdb_length = MAX_COMMAND_SIZE; 825 666 memset(frame->cdb, 0, MAX_COMMAND_SIZE); 826 667 frame->cdb[0] = SCSI_CMD_MARVELL_SPECIFIC; 668 + frame->cdb[1] = CDB_CORE_MODULE; 827 669 frame->cdb[2] = CDB_CORE_SHUTDOWN; 828 670 829 671 mvumi_issue_blocked_cmd(mhba, cmd); ··· 855 695 return ret; 856 696 } 857 697 858 - void mvumi_hs_build_page(struct mvumi_hba *mhba, 698 + static void mvumi_hs_build_page(struct mvumi_hba *mhba, 859 699 struct mvumi_hs_header *hs_header) 860 700 { 861 701 struct mvumi_hs_page2 *hs_page2; ··· 870 710 hs_header->frame_length = sizeof(*hs_page2) - 4; 871 711 memset(hs_header->frame_content, 0, hs_header->frame_length); 872 712 hs_page2->host_type = 3; /* 3 mean linux*/ 713 + if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC) 714 + hs_page2->host_cap = 0x08;/* host dynamic source mode */ 873 715 hs_page2->host_ver.ver_major = VER_MAJOR; 874 716 hs_page2->host_ver.ver_minor = VER_MINOR; 875 717 hs_page2->host_ver.ver_oem = VER_OEM; ··· 907 745 hs_page4->ob_baseaddr_h = upper_32_bits(mhba->ob_list_phys); 908 746 hs_page4->ib_entry_size = mhba->ib_max_size_setting; 909 747 hs_page4->ob_entry_size = mhba->ob_max_size_setting; 910 - hs_page4->ob_depth = mhba->list_num_io; 911 - hs_page4->ib_depth = mhba->list_num_io; 748 + if (mhba->hba_capability 749 + & HS_CAPABILITY_NEW_PAGE_IO_DEPTH_DEF) { 750 + hs_page4->ob_depth = find_first_bit((unsigned long *) 751 + &mhba->list_num_io, 752 + BITS_PER_LONG); 753 + hs_page4->ib_depth = find_first_bit((unsigned long *) 754 + &mhba->list_num_io, 755 + BITS_PER_LONG); 756 + } else { 757 + hs_page4->ob_depth = (u8) mhba->list_num_io; 758 + hs_page4->ib_depth = (u8) mhba->list_num_io; 759 + } 912 760 hs_header->checksum = mvumi_calculate_checksum(hs_header, 913 761 hs_header->frame_length); 914 762 break; ··· 946 774 return 0; 947 775 948 776 tmp_size = mhba->ib_max_size * mhba->max_io; 777 + if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC) 778 + tmp_size += sizeof(struct mvumi_dyn_list_entry) * mhba->max_io; 779 + 949 780 tmp_size += 128 + mhba->ob_max_size * mhba->max_io; 950 - tmp_size += 8 + sizeof(u32) + 16; 781 + tmp_size += 8 + sizeof(u32)*2 + 16; 951 782 952 783 res_mgnt = mvumi_alloc_mem_resource(mhba, 953 784 RESOURCE_UNCACHED_MEMORY, tmp_size); ··· 968 793 v += offset; 969 794 mhba->ib_list = v; 970 795 mhba->ib_list_phys = p; 796 + if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC) { 797 + v += sizeof(struct mvumi_dyn_list_entry) * mhba->max_io; 798 + p += sizeof(struct mvumi_dyn_list_entry) * mhba->max_io; 799 + mhba->ib_frame = v; 800 + mhba->ib_frame_phys = p; 801 + } 971 802 v += mhba->ib_max_size * mhba->max_io; 972 803 p += mhba->ib_max_size * mhba->max_io; 804 + 973 805 /* ib shadow */ 974 806 offset = round_up(p, 8) - p; 975 807 p += offset; 976 808 v += offset; 977 809 mhba->ib_shadow = v; 978 810 mhba->ib_shadow_phys = p; 979 - p += sizeof(u32); 980 - v += sizeof(u32); 811 + p += sizeof(u32)*2; 812 + v += sizeof(u32)*2; 981 813 /* ob shadow */ 982 - offset = round_up(p, 8) - p; 983 - p += offset; 984 - v += offset; 985 - mhba->ob_shadow = v; 986 - mhba->ob_shadow_phys = p; 987 - p += 8; 988 - v += 8; 814 + if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9580) { 815 + offset = round_up(p, 8) - p; 816 + p += offset; 817 + v += offset; 818 + mhba->ob_shadow = v; 819 + mhba->ob_shadow_phys = p; 820 + p += 8; 821 + v += 8; 822 + } else { 823 + offset = round_up(p, 4) - p; 824 + p += offset; 825 + v += offset; 826 + mhba->ob_shadow = v; 827 + mhba->ob_shadow_phys = p; 828 + p += 4; 829 + v += 4; 830 + } 989 831 990 832 /* ob list */ 991 833 offset = round_up(p, 128) - p; ··· 1094 902 dev_dbg(&mhba->pdev->dev, "FW version:%d\n", 1095 903 hs_page1->fw_ver.ver_build); 1096 904 905 + if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) 906 + mhba->eot_flag = 22; 907 + else 908 + mhba->eot_flag = 27; 909 + if (mhba->hba_capability & HS_CAPABILITY_NEW_PAGE_IO_DEPTH_DEF) 910 + mhba->list_num_io = 1 << hs_page1->cl_inout_list_depth; 1097 911 break; 1098 912 default: 1099 913 dev_err(&mhba->pdev->dev, "handshake: page code error\n"); ··· 1121 923 { 1122 924 unsigned int hs_state, tmp, hs_fun; 1123 925 struct mvumi_hs_header *hs_header; 1124 - void *regs = mhba->mmio; 926 + struct mvumi_hw_regs *regs = mhba->regs; 1125 927 1126 928 if (mhba->fw_state == FW_STATE_STARTING) 1127 929 hs_state = HS_S_START; 1128 930 else { 1129 - tmp = ioread32(regs + CPU_ARM_TO_PCIEA_MSG0); 931 + tmp = ioread32(regs->arm_to_pciea_msg0); 1130 932 hs_state = HS_GET_STATE(tmp); 1131 933 dev_dbg(&mhba->pdev->dev, "handshake state[0x%x].\n", hs_state); 1132 934 if (HS_GET_STATUS(tmp) != HS_STATUS_OK) { ··· 1141 943 mhba->fw_state = FW_STATE_HANDSHAKING; 1142 944 HS_SET_STATUS(hs_fun, HS_STATUS_OK); 1143 945 HS_SET_STATE(hs_fun, HS_S_RESET); 1144 - iowrite32(HANDSHAKE_SIGNATURE, regs + CPU_PCIEA_TO_ARM_MSG1); 1145 - iowrite32(hs_fun, regs + CPU_PCIEA_TO_ARM_MSG0); 1146 - iowrite32(DRBL_HANDSHAKE, regs + CPU_PCIEA_TO_ARM_DRBL_REG); 946 + iowrite32(HANDSHAKE_SIGNATURE, regs->pciea_to_arm_msg1); 947 + iowrite32(hs_fun, regs->pciea_to_arm_msg0); 948 + iowrite32(DRBL_HANDSHAKE, regs->pciea_to_arm_drbl_reg); 1147 949 break; 1148 950 1149 951 case HS_S_RESET: 1150 952 iowrite32(lower_32_bits(mhba->handshake_page_phys), 1151 - regs + CPU_PCIEA_TO_ARM_MSG1); 953 + regs->pciea_to_arm_msg1); 1152 954 iowrite32(upper_32_bits(mhba->handshake_page_phys), 1153 - regs + CPU_ARM_TO_PCIEA_MSG1); 955 + regs->arm_to_pciea_msg1); 1154 956 HS_SET_STATUS(hs_fun, HS_STATUS_OK); 1155 957 HS_SET_STATE(hs_fun, HS_S_PAGE_ADDR); 1156 - iowrite32(hs_fun, regs + CPU_PCIEA_TO_ARM_MSG0); 1157 - iowrite32(DRBL_HANDSHAKE, regs + CPU_PCIEA_TO_ARM_DRBL_REG); 1158 - 958 + iowrite32(hs_fun, regs->pciea_to_arm_msg0); 959 + iowrite32(DRBL_HANDSHAKE, regs->pciea_to_arm_drbl_reg); 1159 960 break; 1160 961 1161 962 case HS_S_PAGE_ADDR: ··· 1194 997 HS_SET_STATE(hs_fun, HS_S_END); 1195 998 1196 999 HS_SET_STATUS(hs_fun, HS_STATUS_OK); 1197 - iowrite32(hs_fun, regs + CPU_PCIEA_TO_ARM_MSG0); 1198 - iowrite32(DRBL_HANDSHAKE, regs + CPU_PCIEA_TO_ARM_DRBL_REG); 1000 + iowrite32(hs_fun, regs->pciea_to_arm_msg0); 1001 + iowrite32(DRBL_HANDSHAKE, regs->pciea_to_arm_drbl_reg); 1199 1002 break; 1200 1003 1201 1004 case HS_S_END: 1202 1005 /* Set communication list ISR */ 1203 - tmp = ioread32(regs + CPU_ENPOINTA_MASK_REG); 1204 - tmp |= INT_MAP_COMAOUT | INT_MAP_COMAERR; 1205 - iowrite32(tmp, regs + CPU_ENPOINTA_MASK_REG); 1006 + tmp = ioread32(regs->enpointa_mask_reg); 1007 + tmp |= regs->int_comaout | regs->int_comaerr; 1008 + iowrite32(tmp, regs->enpointa_mask_reg); 1206 1009 iowrite32(mhba->list_num_io, mhba->ib_shadow); 1207 1010 /* Set InBound List Available count shadow */ 1208 1011 iowrite32(lower_32_bits(mhba->ib_shadow_phys), 1209 - regs + CLA_INB_AVAL_COUNT_BASEL); 1012 + regs->inb_aval_count_basel); 1210 1013 iowrite32(upper_32_bits(mhba->ib_shadow_phys), 1211 - regs + CLA_INB_AVAL_COUNT_BASEH); 1014 + regs->inb_aval_count_baseh); 1212 1015 1213 - /* Set OutBound List Available count shadow */ 1214 - iowrite32((mhba->list_num_io-1) | CL_POINTER_TOGGLE, 1215 - mhba->ob_shadow); 1216 - iowrite32(lower_32_bits(mhba->ob_shadow_phys), regs + 0x5B0); 1217 - iowrite32(upper_32_bits(mhba->ob_shadow_phys), regs + 0x5B4); 1016 + if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9143) { 1017 + /* Set OutBound List Available count shadow */ 1018 + iowrite32((mhba->list_num_io-1) | 1019 + regs->cl_pointer_toggle, 1020 + mhba->ob_shadow); 1021 + iowrite32(lower_32_bits(mhba->ob_shadow_phys), 1022 + regs->outb_copy_basel); 1023 + iowrite32(upper_32_bits(mhba->ob_shadow_phys), 1024 + regs->outb_copy_baseh); 1025 + } 1218 1026 1219 - mhba->ib_cur_slot = (mhba->list_num_io - 1) | CL_POINTER_TOGGLE; 1220 - mhba->ob_cur_slot = (mhba->list_num_io - 1) | CL_POINTER_TOGGLE; 1027 + mhba->ib_cur_slot = (mhba->list_num_io - 1) | 1028 + regs->cl_pointer_toggle; 1029 + mhba->ob_cur_slot = (mhba->list_num_io - 1) | 1030 + regs->cl_pointer_toggle; 1221 1031 mhba->fw_state = FW_STATE_STARTED; 1222 1032 1223 1033 break; ··· 1244 1040 before = jiffies; 1245 1041 mvumi_handshake(mhba); 1246 1042 do { 1247 - isr_status = mhba->instancet->read_fw_status_reg(mhba->mmio); 1043 + isr_status = mhba->instancet->read_fw_status_reg(mhba); 1248 1044 1249 1045 if (mhba->fw_state == FW_STATE_STARTED) 1250 1046 return 0; ··· 1266 1062 1267 1063 static unsigned char mvumi_check_handshake(struct mvumi_hba *mhba) 1268 1064 { 1269 - void *regs = mhba->mmio; 1270 1065 unsigned int tmp; 1271 1066 unsigned long before; 1272 1067 1273 1068 before = jiffies; 1274 - tmp = ioread32(regs + CPU_ARM_TO_PCIEA_MSG1); 1069 + tmp = ioread32(mhba->regs->arm_to_pciea_msg1); 1275 1070 while ((tmp != HANDSHAKE_READYSTATE) && (tmp != HANDSHAKE_DONESTATE)) { 1276 1071 if (tmp != HANDSHAKE_READYSTATE) 1277 1072 iowrite32(DRBL_MU_RESET, 1278 - regs + CPU_PCIEA_TO_ARM_DRBL_REG); 1073 + mhba->regs->pciea_to_arm_drbl_reg); 1279 1074 if (time_after(jiffies, before + FW_MAX_DELAY * HZ)) { 1280 1075 dev_err(&mhba->pdev->dev, 1281 1076 "invalid signature [0x%x].\n", tmp); ··· 1282 1079 } 1283 1080 usleep_range(1000, 2000); 1284 1081 rmb(); 1285 - tmp = ioread32(regs + CPU_ARM_TO_PCIEA_MSG1); 1082 + tmp = ioread32(mhba->regs->arm_to_pciea_msg1); 1286 1083 } 1287 1084 1288 1085 mhba->fw_state = FW_STATE_STARTING; ··· 1303 1100 1304 1101 static unsigned char mvumi_start(struct mvumi_hba *mhba) 1305 1102 { 1306 - void *regs = mhba->mmio; 1307 1103 unsigned int tmp; 1308 - /* clear Door bell */ 1309 - tmp = ioread32(regs + CPU_ARM_TO_PCIEA_DRBL_REG); 1310 - iowrite32(tmp, regs + CPU_ARM_TO_PCIEA_DRBL_REG); 1104 + struct mvumi_hw_regs *regs = mhba->regs; 1311 1105 1312 - iowrite32(0x3FFFFFFF, regs + CPU_ARM_TO_PCIEA_MASK_REG); 1313 - tmp = ioread32(regs + CPU_ENPOINTA_MASK_REG) | INT_MAP_DL_CPU2PCIEA; 1314 - iowrite32(tmp, regs + CPU_ENPOINTA_MASK_REG); 1106 + /* clear Door bell */ 1107 + tmp = ioread32(regs->arm_to_pciea_drbl_reg); 1108 + iowrite32(tmp, regs->arm_to_pciea_drbl_reg); 1109 + 1110 + iowrite32(regs->int_drbl_int_mask, regs->arm_to_pciea_mask_reg); 1111 + tmp = ioread32(regs->enpointa_mask_reg) | regs->int_dl_cpu2pciea; 1112 + iowrite32(tmp, regs->enpointa_mask_reg); 1113 + msleep(100); 1315 1114 if (mvumi_check_handshake(mhba)) 1316 1115 return -1; 1317 1116 ··· 1371 1166 cmd->scmd->scsi_done(scmd); 1372 1167 mvumi_return_cmd(mhba, cmd); 1373 1168 } 1169 + 1374 1170 static void mvumi_complete_internal_cmd(struct mvumi_hba *mhba, 1375 1171 struct mvumi_cmd *cmd, 1376 1172 struct mvumi_rsp_frame *ob_frame) ··· 1416 1210 } 1417 1211 } 1418 1212 1213 + static int mvumi_handle_hotplug(struct mvumi_hba *mhba, u16 devid, int status) 1214 + { 1215 + struct scsi_device *sdev; 1216 + int ret = -1; 1217 + 1218 + if (status == DEVICE_OFFLINE) { 1219 + sdev = scsi_device_lookup(mhba->shost, 0, devid, 0); 1220 + if (sdev) { 1221 + dev_dbg(&mhba->pdev->dev, "remove disk %d-%d-%d.\n", 0, 1222 + sdev->id, 0); 1223 + scsi_remove_device(sdev); 1224 + scsi_device_put(sdev); 1225 + ret = 0; 1226 + } else 1227 + dev_err(&mhba->pdev->dev, " no disk[%d] to remove\n", 1228 + devid); 1229 + } else if (status == DEVICE_ONLINE) { 1230 + sdev = scsi_device_lookup(mhba->shost, 0, devid, 0); 1231 + if (!sdev) { 1232 + scsi_add_device(mhba->shost, 0, devid, 0); 1233 + dev_dbg(&mhba->pdev->dev, " add disk %d-%d-%d.\n", 0, 1234 + devid, 0); 1235 + ret = 0; 1236 + } else { 1237 + dev_err(&mhba->pdev->dev, " don't add disk %d-%d-%d.\n", 1238 + 0, devid, 0); 1239 + scsi_device_put(sdev); 1240 + } 1241 + } 1242 + return ret; 1243 + } 1244 + 1245 + static u64 mvumi_inquiry(struct mvumi_hba *mhba, 1246 + unsigned int id, struct mvumi_cmd *cmd) 1247 + { 1248 + struct mvumi_msg_frame *frame; 1249 + u64 wwid = 0; 1250 + int cmd_alloc = 0; 1251 + int data_buf_len = 64; 1252 + 1253 + if (!cmd) { 1254 + cmd = mvumi_create_internal_cmd(mhba, data_buf_len); 1255 + if (cmd) 1256 + cmd_alloc = 1; 1257 + else 1258 + return 0; 1259 + } else { 1260 + memset(cmd->data_buf, 0, data_buf_len); 1261 + } 1262 + cmd->scmd = NULL; 1263 + cmd->cmd_status = REQ_STATUS_PENDING; 1264 + atomic_set(&cmd->sync_cmd, 0); 1265 + frame = cmd->frame; 1266 + frame->device_id = (u16) id; 1267 + frame->cmd_flag = CMD_FLAG_DATA_IN; 1268 + frame->req_function = CL_FUN_SCSI_CMD; 1269 + frame->cdb_length = 6; 1270 + frame->data_transfer_length = MVUMI_INQUIRY_LENGTH; 1271 + memset(frame->cdb, 0, frame->cdb_length); 1272 + frame->cdb[0] = INQUIRY; 1273 + frame->cdb[4] = frame->data_transfer_length; 1274 + 1275 + mvumi_issue_blocked_cmd(mhba, cmd); 1276 + 1277 + if (cmd->cmd_status == SAM_STAT_GOOD) { 1278 + if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9143) 1279 + wwid = id + 1; 1280 + else 1281 + memcpy((void *)&wwid, 1282 + (cmd->data_buf + MVUMI_INQUIRY_UUID_OFF), 1283 + MVUMI_INQUIRY_UUID_LEN); 1284 + dev_dbg(&mhba->pdev->dev, 1285 + "inquiry device(0:%d:0) wwid(%llx)\n", id, wwid); 1286 + } else { 1287 + wwid = 0; 1288 + } 1289 + if (cmd_alloc) 1290 + mvumi_delete_internal_cmd(mhba, cmd); 1291 + 1292 + return wwid; 1293 + } 1294 + 1295 + static void mvumi_detach_devices(struct mvumi_hba *mhba) 1296 + { 1297 + struct mvumi_device *mv_dev = NULL , *dev_next; 1298 + struct scsi_device *sdev = NULL; 1299 + 1300 + mutex_lock(&mhba->device_lock); 1301 + 1302 + /* detach Hard Disk */ 1303 + list_for_each_entry_safe(mv_dev, dev_next, 1304 + &mhba->shost_dev_list, list) { 1305 + mvumi_handle_hotplug(mhba, mv_dev->id, DEVICE_OFFLINE); 1306 + list_del_init(&mv_dev->list); 1307 + dev_dbg(&mhba->pdev->dev, "release device(0:%d:0) wwid(%llx)\n", 1308 + mv_dev->id, mv_dev->wwid); 1309 + kfree(mv_dev); 1310 + } 1311 + list_for_each_entry_safe(mv_dev, dev_next, &mhba->mhba_dev_list, list) { 1312 + list_del_init(&mv_dev->list); 1313 + dev_dbg(&mhba->pdev->dev, "release device(0:%d:0) wwid(%llx)\n", 1314 + mv_dev->id, mv_dev->wwid); 1315 + kfree(mv_dev); 1316 + } 1317 + 1318 + /* detach virtual device */ 1319 + if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9580) 1320 + sdev = scsi_device_lookup(mhba->shost, 0, 1321 + mhba->max_target_id - 1, 0); 1322 + 1323 + if (sdev) { 1324 + scsi_remove_device(sdev); 1325 + scsi_device_put(sdev); 1326 + } 1327 + 1328 + mutex_unlock(&mhba->device_lock); 1329 + } 1330 + 1331 + static void mvumi_rescan_devices(struct mvumi_hba *mhba, int id) 1332 + { 1333 + struct scsi_device *sdev; 1334 + 1335 + sdev = scsi_device_lookup(mhba->shost, 0, id, 0); 1336 + if (sdev) { 1337 + scsi_rescan_device(&sdev->sdev_gendev); 1338 + scsi_device_put(sdev); 1339 + } 1340 + } 1341 + 1342 + static int mvumi_match_devices(struct mvumi_hba *mhba, int id, u64 wwid) 1343 + { 1344 + struct mvumi_device *mv_dev = NULL; 1345 + 1346 + list_for_each_entry(mv_dev, &mhba->shost_dev_list, list) { 1347 + if (mv_dev->wwid == wwid) { 1348 + if (mv_dev->id != id) { 1349 + dev_err(&mhba->pdev->dev, 1350 + "%s has same wwid[%llx] ," 1351 + " but different id[%d %d]\n", 1352 + __func__, mv_dev->wwid, mv_dev->id, id); 1353 + return -1; 1354 + } else { 1355 + if (mhba->pdev->device == 1356 + PCI_DEVICE_ID_MARVELL_MV9143) 1357 + mvumi_rescan_devices(mhba, id); 1358 + return 1; 1359 + } 1360 + } 1361 + } 1362 + return 0; 1363 + } 1364 + 1365 + static void mvumi_remove_devices(struct mvumi_hba *mhba, int id) 1366 + { 1367 + struct mvumi_device *mv_dev = NULL, *dev_next; 1368 + 1369 + list_for_each_entry_safe(mv_dev, dev_next, 1370 + &mhba->shost_dev_list, list) { 1371 + if (mv_dev->id == id) { 1372 + dev_dbg(&mhba->pdev->dev, 1373 + "detach device(0:%d:0) wwid(%llx) from HOST\n", 1374 + mv_dev->id, mv_dev->wwid); 1375 + mvumi_handle_hotplug(mhba, mv_dev->id, DEVICE_OFFLINE); 1376 + list_del_init(&mv_dev->list); 1377 + kfree(mv_dev); 1378 + } 1379 + } 1380 + } 1381 + 1382 + static int mvumi_probe_devices(struct mvumi_hba *mhba) 1383 + { 1384 + int id, maxid; 1385 + u64 wwid = 0; 1386 + struct mvumi_device *mv_dev = NULL; 1387 + struct mvumi_cmd *cmd = NULL; 1388 + int found = 0; 1389 + 1390 + cmd = mvumi_create_internal_cmd(mhba, 64); 1391 + if (!cmd) 1392 + return -1; 1393 + 1394 + if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9143) 1395 + maxid = mhba->max_target_id; 1396 + else 1397 + maxid = mhba->max_target_id - 1; 1398 + 1399 + for (id = 0; id < maxid; id++) { 1400 + wwid = mvumi_inquiry(mhba, id, cmd); 1401 + if (!wwid) { 1402 + /* device no response, remove it */ 1403 + mvumi_remove_devices(mhba, id); 1404 + } else { 1405 + /* device response, add it */ 1406 + found = mvumi_match_devices(mhba, id, wwid); 1407 + if (!found) { 1408 + mvumi_remove_devices(mhba, id); 1409 + mv_dev = kzalloc(sizeof(struct mvumi_device), 1410 + GFP_KERNEL); 1411 + if (!mv_dev) { 1412 + dev_err(&mhba->pdev->dev, 1413 + "%s alloc mv_dev failed\n", 1414 + __func__); 1415 + continue; 1416 + } 1417 + mv_dev->id = id; 1418 + mv_dev->wwid = wwid; 1419 + mv_dev->sdev = NULL; 1420 + INIT_LIST_HEAD(&mv_dev->list); 1421 + list_add_tail(&mv_dev->list, 1422 + &mhba->mhba_dev_list); 1423 + dev_dbg(&mhba->pdev->dev, 1424 + "probe a new device(0:%d:0)" 1425 + " wwid(%llx)\n", id, mv_dev->wwid); 1426 + } else if (found == -1) 1427 + return -1; 1428 + else 1429 + continue; 1430 + } 1431 + } 1432 + 1433 + if (cmd) 1434 + mvumi_delete_internal_cmd(mhba, cmd); 1435 + 1436 + return 0; 1437 + } 1438 + 1439 + static int mvumi_rescan_bus(void *data) 1440 + { 1441 + int ret = 0; 1442 + struct mvumi_hba *mhba = (struct mvumi_hba *) data; 1443 + struct mvumi_device *mv_dev = NULL , *dev_next; 1444 + 1445 + while (!kthread_should_stop()) { 1446 + 1447 + set_current_state(TASK_INTERRUPTIBLE); 1448 + if (!atomic_read(&mhba->pnp_count)) 1449 + schedule(); 1450 + msleep(1000); 1451 + atomic_set(&mhba->pnp_count, 0); 1452 + __set_current_state(TASK_RUNNING); 1453 + 1454 + mutex_lock(&mhba->device_lock); 1455 + ret = mvumi_probe_devices(mhba); 1456 + if (!ret) { 1457 + list_for_each_entry_safe(mv_dev, dev_next, 1458 + &mhba->mhba_dev_list, list) { 1459 + if (mvumi_handle_hotplug(mhba, mv_dev->id, 1460 + DEVICE_ONLINE)) { 1461 + dev_err(&mhba->pdev->dev, 1462 + "%s add device(0:%d:0) failed" 1463 + "wwid(%llx) has exist\n", 1464 + __func__, 1465 + mv_dev->id, mv_dev->wwid); 1466 + list_del_init(&mv_dev->list); 1467 + kfree(mv_dev); 1468 + } else { 1469 + list_move_tail(&mv_dev->list, 1470 + &mhba->shost_dev_list); 1471 + } 1472 + } 1473 + } 1474 + mutex_unlock(&mhba->device_lock); 1475 + } 1476 + return 0; 1477 + } 1478 + 1479 + static void mvumi_proc_msg(struct mvumi_hba *mhba, 1480 + struct mvumi_hotplug_event *param) 1481 + { 1482 + u16 size = param->size; 1483 + const unsigned long *ar_bitmap; 1484 + const unsigned long *re_bitmap; 1485 + int index; 1486 + 1487 + if (mhba->fw_flag & MVUMI_FW_ATTACH) { 1488 + index = -1; 1489 + ar_bitmap = (const unsigned long *) param->bitmap; 1490 + re_bitmap = (const unsigned long *) &param->bitmap[size >> 3]; 1491 + 1492 + mutex_lock(&mhba->sas_discovery_mutex); 1493 + do { 1494 + index = find_next_zero_bit(ar_bitmap, size, index + 1); 1495 + if (index >= size) 1496 + break; 1497 + mvumi_handle_hotplug(mhba, index, DEVICE_ONLINE); 1498 + } while (1); 1499 + 1500 + index = -1; 1501 + do { 1502 + index = find_next_zero_bit(re_bitmap, size, index + 1); 1503 + if (index >= size) 1504 + break; 1505 + mvumi_handle_hotplug(mhba, index, DEVICE_OFFLINE); 1506 + } while (1); 1507 + mutex_unlock(&mhba->sas_discovery_mutex); 1508 + } 1509 + } 1510 + 1419 1511 static void mvumi_notification(struct mvumi_hba *mhba, u8 msg, void *buffer) 1420 1512 { 1421 1513 if (msg == APICDB1_EVENT_GETEVENT) { ··· 1731 1227 param = &er->events[i]; 1732 1228 mvumi_show_event(mhba, param); 1733 1229 } 1230 + } else if (msg == APICDB1_HOST_GETEVENT) { 1231 + mvumi_proc_msg(mhba, buffer); 1734 1232 } 1735 1233 } 1736 1234 ··· 1777 1271 kfree(mu_ev); 1778 1272 } 1779 1273 1780 - static void mvumi_launch_events(struct mvumi_hba *mhba, u8 msg) 1274 + static void mvumi_launch_events(struct mvumi_hba *mhba, u32 isr_status) 1781 1275 { 1782 1276 struct mvumi_events_wq *mu_ev; 1783 1277 1784 - mu_ev = kzalloc(sizeof(*mu_ev), GFP_ATOMIC); 1785 - if (mu_ev) { 1786 - INIT_WORK(&mu_ev->work_q, mvumi_scan_events); 1787 - mu_ev->mhba = mhba; 1788 - mu_ev->event = msg; 1789 - mu_ev->param = NULL; 1790 - schedule_work(&mu_ev->work_q); 1278 + while (isr_status & (DRBL_BUS_CHANGE | DRBL_EVENT_NOTIFY)) { 1279 + if (isr_status & DRBL_BUS_CHANGE) { 1280 + atomic_inc(&mhba->pnp_count); 1281 + wake_up_process(mhba->dm_thread); 1282 + isr_status &= ~(DRBL_BUS_CHANGE); 1283 + continue; 1284 + } 1285 + 1286 + mu_ev = kzalloc(sizeof(*mu_ev), GFP_ATOMIC); 1287 + if (mu_ev) { 1288 + INIT_WORK(&mu_ev->work_q, mvumi_scan_events); 1289 + mu_ev->mhba = mhba; 1290 + mu_ev->event = APICDB1_EVENT_GETEVENT; 1291 + isr_status &= ~(DRBL_EVENT_NOTIFY); 1292 + mu_ev->param = NULL; 1293 + schedule_work(&mu_ev->work_q); 1294 + } 1791 1295 } 1792 1296 } 1793 1297 ··· 1838 1322 return IRQ_NONE; 1839 1323 } 1840 1324 1841 - if (mhba->global_isr & INT_MAP_DL_CPU2PCIEA) { 1325 + if (mhba->global_isr & mhba->regs->int_dl_cpu2pciea) { 1326 + if (mhba->isr_status & (DRBL_BUS_CHANGE | DRBL_EVENT_NOTIFY)) 1327 + mvumi_launch_events(mhba, mhba->isr_status); 1842 1328 if (mhba->isr_status & DRBL_HANDSHAKE_ISR) { 1843 1329 dev_warn(&mhba->pdev->dev, "enter handshake again!\n"); 1844 1330 mvumi_handshake(mhba); 1845 1331 } 1846 - if (mhba->isr_status & DRBL_EVENT_NOTIFY) 1847 - mvumi_launch_events(mhba, APICDB1_EVENT_GETEVENT); 1332 + 1848 1333 } 1849 1334 1850 - if (mhba->global_isr & INT_MAP_COMAOUT) 1335 + if (mhba->global_isr & mhba->regs->int_comaout) 1851 1336 mvumi_receive_ob_list_entry(mhba); 1852 1337 1853 1338 mhba->global_isr = 0; ··· 1875 1358 dev_dbg(&mhba->pdev->dev, "no free tag.\n"); 1876 1359 return MV_QUEUE_COMMAND_RESULT_NO_RESOURCE; 1877 1360 } 1878 - if (mvumi_get_ib_list_entry(mhba, &ib_entry)) 1879 - return MV_QUEUE_COMMAND_RESULT_NO_RESOURCE; 1361 + mvumi_get_ib_list_entry(mhba, &ib_entry); 1880 1362 1881 1363 cmd->frame->tag = tag_get_one(mhba, &mhba->tag_pool); 1882 1364 cmd->frame->request_id = mhba->io_seq++; ··· 1883 1367 mhba->tag_cmd[cmd->frame->tag] = cmd; 1884 1368 frame_len = sizeof(*ib_frame) - 4 + 1885 1369 ib_frame->sg_counts * sizeof(struct mvumi_sgl); 1886 - memcpy(ib_entry, ib_frame, frame_len); 1370 + if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC) { 1371 + struct mvumi_dyn_list_entry *dle; 1372 + dle = ib_entry; 1373 + dle->src_low_addr = 1374 + cpu_to_le32(lower_32_bits(cmd->frame_phys)); 1375 + dle->src_high_addr = 1376 + cpu_to_le32(upper_32_bits(cmd->frame_phys)); 1377 + dle->if_length = (frame_len >> 2) & 0xFFF; 1378 + } else { 1379 + memcpy(ib_entry, ib_frame, frame_len); 1380 + } 1887 1381 return MV_QUEUE_COMMAND_RESULT_SENT; 1888 1382 } 1889 1383 1890 1384 static void mvumi_fire_cmd(struct mvumi_hba *mhba, struct mvumi_cmd *cmd) 1891 1385 { 1892 1386 unsigned short num_of_cl_sent = 0; 1387 + unsigned int count; 1893 1388 enum mvumi_qc_result result; 1894 1389 1895 1390 if (cmd) 1896 1391 list_add_tail(&cmd->queue_pointer, &mhba->waiting_req_list); 1392 + count = mhba->instancet->check_ib_list(mhba); 1393 + if (list_empty(&mhba->waiting_req_list) || !count) 1394 + return; 1897 1395 1898 - while (!list_empty(&mhba->waiting_req_list)) { 1396 + do { 1899 1397 cmd = list_first_entry(&mhba->waiting_req_list, 1900 - struct mvumi_cmd, queue_pointer); 1398 + struct mvumi_cmd, queue_pointer); 1901 1399 list_del_init(&cmd->queue_pointer); 1902 1400 result = mvumi_send_command(mhba, cmd); 1903 1401 switch (result) { ··· 1925 1395 1926 1396 return; 1927 1397 } 1928 - } 1398 + } while (!list_empty(&mhba->waiting_req_list) && count--); 1399 + 1929 1400 if (num_of_cl_sent > 0) 1930 1401 mvumi_send_ib_list_entry(mhba); 1931 1402 } 1932 1403 1933 1404 /** 1934 1405 * mvumi_enable_intr - Enables interrupts 1935 - * @regs: FW register set 1406 + * @mhba: Adapter soft state 1936 1407 */ 1937 - static void mvumi_enable_intr(void *regs) 1408 + static void mvumi_enable_intr(struct mvumi_hba *mhba) 1938 1409 { 1939 1410 unsigned int mask; 1411 + struct mvumi_hw_regs *regs = mhba->regs; 1940 1412 1941 - iowrite32(0x3FFFFFFF, regs + CPU_ARM_TO_PCIEA_MASK_REG); 1942 - mask = ioread32(regs + CPU_ENPOINTA_MASK_REG); 1943 - mask |= INT_MAP_DL_CPU2PCIEA | INT_MAP_COMAOUT | INT_MAP_COMAERR; 1944 - iowrite32(mask, regs + CPU_ENPOINTA_MASK_REG); 1413 + iowrite32(regs->int_drbl_int_mask, regs->arm_to_pciea_mask_reg); 1414 + mask = ioread32(regs->enpointa_mask_reg); 1415 + mask |= regs->int_dl_cpu2pciea | regs->int_comaout | regs->int_comaerr; 1416 + iowrite32(mask, regs->enpointa_mask_reg); 1945 1417 } 1946 1418 1947 1419 /** 1948 1420 * mvumi_disable_intr -Disables interrupt 1949 - * @regs: FW register set 1421 + * @mhba: Adapter soft state 1950 1422 */ 1951 - static void mvumi_disable_intr(void *regs) 1423 + static void mvumi_disable_intr(struct mvumi_hba *mhba) 1952 1424 { 1953 1425 unsigned int mask; 1426 + struct mvumi_hw_regs *regs = mhba->regs; 1954 1427 1955 - iowrite32(0, regs + CPU_ARM_TO_PCIEA_MASK_REG); 1956 - mask = ioread32(regs + CPU_ENPOINTA_MASK_REG); 1957 - mask &= ~(INT_MAP_DL_CPU2PCIEA | INT_MAP_COMAOUT | INT_MAP_COMAERR); 1958 - iowrite32(mask, regs + CPU_ENPOINTA_MASK_REG); 1428 + iowrite32(0, regs->arm_to_pciea_mask_reg); 1429 + mask = ioread32(regs->enpointa_mask_reg); 1430 + mask &= ~(regs->int_dl_cpu2pciea | regs->int_comaout | 1431 + regs->int_comaerr); 1432 + iowrite32(mask, regs->enpointa_mask_reg); 1959 1433 } 1960 1434 1961 1435 static int mvumi_clear_intr(void *extend) 1962 1436 { 1963 1437 struct mvumi_hba *mhba = (struct mvumi_hba *) extend; 1964 1438 unsigned int status, isr_status = 0, tmp = 0; 1965 - void *regs = mhba->mmio; 1439 + struct mvumi_hw_regs *regs = mhba->regs; 1966 1440 1967 - status = ioread32(regs + CPU_MAIN_INT_CAUSE_REG); 1968 - if (!(status & INT_MAP_MU) || status == 0xFFFFFFFF) 1441 + status = ioread32(regs->main_int_cause_reg); 1442 + if (!(status & regs->int_mu) || status == 0xFFFFFFFF) 1969 1443 return 1; 1970 - if (unlikely(status & INT_MAP_COMAERR)) { 1971 - tmp = ioread32(regs + CLA_ISR_CAUSE); 1972 - if (tmp & (CLIC_IN_ERR_IRQ | CLIC_OUT_ERR_IRQ)) 1973 - iowrite32(tmp & (CLIC_IN_ERR_IRQ | CLIC_OUT_ERR_IRQ), 1974 - regs + CLA_ISR_CAUSE); 1975 - status ^= INT_MAP_COMAERR; 1444 + if (unlikely(status & regs->int_comaerr)) { 1445 + tmp = ioread32(regs->outb_isr_cause); 1446 + if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9580) { 1447 + if (tmp & regs->clic_out_err) { 1448 + iowrite32(tmp & regs->clic_out_err, 1449 + regs->outb_isr_cause); 1450 + } 1451 + } else { 1452 + if (tmp & (regs->clic_in_err | regs->clic_out_err)) 1453 + iowrite32(tmp & (regs->clic_in_err | 1454 + regs->clic_out_err), 1455 + regs->outb_isr_cause); 1456 + } 1457 + status ^= mhba->regs->int_comaerr; 1976 1458 /* inbound or outbound parity error, command will timeout */ 1977 1459 } 1978 - if (status & INT_MAP_COMAOUT) { 1979 - tmp = ioread32(regs + CLA_ISR_CAUSE); 1980 - if (tmp & CLIC_OUT_IRQ) 1981 - iowrite32(tmp & CLIC_OUT_IRQ, regs + CLA_ISR_CAUSE); 1460 + if (status & regs->int_comaout) { 1461 + tmp = ioread32(regs->outb_isr_cause); 1462 + if (tmp & regs->clic_irq) 1463 + iowrite32(tmp & regs->clic_irq, regs->outb_isr_cause); 1982 1464 } 1983 - if (status & INT_MAP_DL_CPU2PCIEA) { 1984 - isr_status = ioread32(regs + CPU_ARM_TO_PCIEA_DRBL_REG); 1465 + if (status & regs->int_dl_cpu2pciea) { 1466 + isr_status = ioread32(regs->arm_to_pciea_drbl_reg); 1985 1467 if (isr_status) 1986 - iowrite32(isr_status, regs + CPU_ARM_TO_PCIEA_DRBL_REG); 1468 + iowrite32(isr_status, regs->arm_to_pciea_drbl_reg); 1987 1469 } 1988 1470 1989 1471 mhba->global_isr = status; ··· 2006 1464 2007 1465 /** 2008 1466 * mvumi_read_fw_status_reg - returns the current FW status value 2009 - * @regs: FW register set 1467 + * @mhba: Adapter soft state 2010 1468 */ 2011 - static unsigned int mvumi_read_fw_status_reg(void *regs) 1469 + static unsigned int mvumi_read_fw_status_reg(struct mvumi_hba *mhba) 2012 1470 { 2013 1471 unsigned int status; 2014 1472 2015 - status = ioread32(regs + CPU_ARM_TO_PCIEA_DRBL_REG); 1473 + status = ioread32(mhba->regs->arm_to_pciea_drbl_reg); 2016 1474 if (status) 2017 - iowrite32(status, regs + CPU_ARM_TO_PCIEA_DRBL_REG); 1475 + iowrite32(status, mhba->regs->arm_to_pciea_drbl_reg); 2018 1476 return status; 2019 1477 } 2020 1478 2021 - static struct mvumi_instance_template mvumi_instance_template = { 1479 + static struct mvumi_instance_template mvumi_instance_9143 = { 2022 1480 .fire_cmd = mvumi_fire_cmd, 2023 1481 .enable_intr = mvumi_enable_intr, 2024 1482 .disable_intr = mvumi_disable_intr, 2025 1483 .clear_intr = mvumi_clear_intr, 2026 1484 .read_fw_status_reg = mvumi_read_fw_status_reg, 1485 + .check_ib_list = mvumi_check_ib_list_9143, 1486 + .check_ob_list = mvumi_check_ob_list_9143, 1487 + .reset_host = mvumi_reset_host_9143, 1488 + }; 1489 + 1490 + static struct mvumi_instance_template mvumi_instance_9580 = { 1491 + .fire_cmd = mvumi_fire_cmd, 1492 + .enable_intr = mvumi_enable_intr, 1493 + .disable_intr = mvumi_disable_intr, 1494 + .clear_intr = mvumi_clear_intr, 1495 + .read_fw_status_reg = mvumi_read_fw_status_reg, 1496 + .check_ib_list = mvumi_check_ib_list_9580, 1497 + .check_ob_list = mvumi_check_ob_list_9580, 1498 + .reset_host = mvumi_reset_host_9580, 2027 1499 }; 2028 1500 2029 1501 static int mvumi_slave_configure(struct scsi_device *sdev) ··· 2237 1681 .eh_timed_out = mvumi_timed_out, 2238 1682 }; 2239 1683 1684 + static int mvumi_cfg_hw_reg(struct mvumi_hba *mhba) 1685 + { 1686 + void *base = NULL; 1687 + struct mvumi_hw_regs *regs; 1688 + 1689 + switch (mhba->pdev->device) { 1690 + case PCI_DEVICE_ID_MARVELL_MV9143: 1691 + mhba->mmio = mhba->base_addr[0]; 1692 + base = mhba->mmio; 1693 + if (!mhba->regs) { 1694 + mhba->regs = kzalloc(sizeof(*regs), GFP_KERNEL); 1695 + if (mhba->regs == NULL) 1696 + return -ENOMEM; 1697 + } 1698 + regs = mhba->regs; 1699 + 1700 + /* For Arm */ 1701 + regs->ctrl_sts_reg = base + 0x20104; 1702 + regs->rstoutn_mask_reg = base + 0x20108; 1703 + regs->sys_soft_rst_reg = base + 0x2010C; 1704 + regs->main_int_cause_reg = base + 0x20200; 1705 + regs->enpointa_mask_reg = base + 0x2020C; 1706 + regs->rstoutn_en_reg = base + 0xF1400; 1707 + /* For Doorbell */ 1708 + regs->pciea_to_arm_drbl_reg = base + 0x20400; 1709 + regs->arm_to_pciea_drbl_reg = base + 0x20408; 1710 + regs->arm_to_pciea_mask_reg = base + 0x2040C; 1711 + regs->pciea_to_arm_msg0 = base + 0x20430; 1712 + regs->pciea_to_arm_msg1 = base + 0x20434; 1713 + regs->arm_to_pciea_msg0 = base + 0x20438; 1714 + regs->arm_to_pciea_msg1 = base + 0x2043C; 1715 + 1716 + /* For Message Unit */ 1717 + 1718 + regs->inb_aval_count_basel = base + 0x508; 1719 + regs->inb_aval_count_baseh = base + 0x50C; 1720 + regs->inb_write_pointer = base + 0x518; 1721 + regs->inb_read_pointer = base + 0x51C; 1722 + regs->outb_coal_cfg = base + 0x568; 1723 + regs->outb_copy_basel = base + 0x5B0; 1724 + regs->outb_copy_baseh = base + 0x5B4; 1725 + regs->outb_copy_pointer = base + 0x544; 1726 + regs->outb_read_pointer = base + 0x548; 1727 + regs->outb_isr_cause = base + 0x560; 1728 + regs->outb_coal_cfg = base + 0x568; 1729 + /* Bit setting for HW */ 1730 + regs->int_comaout = 1 << 8; 1731 + regs->int_comaerr = 1 << 6; 1732 + regs->int_dl_cpu2pciea = 1 << 1; 1733 + regs->cl_pointer_toggle = 1 << 12; 1734 + regs->clic_irq = 1 << 1; 1735 + regs->clic_in_err = 1 << 8; 1736 + regs->clic_out_err = 1 << 12; 1737 + regs->cl_slot_num_mask = 0xFFF; 1738 + regs->int_drbl_int_mask = 0x3FFFFFFF; 1739 + regs->int_mu = regs->int_dl_cpu2pciea | regs->int_comaout | 1740 + regs->int_comaerr; 1741 + break; 1742 + case PCI_DEVICE_ID_MARVELL_MV9580: 1743 + mhba->mmio = mhba->base_addr[2]; 1744 + base = mhba->mmio; 1745 + if (!mhba->regs) { 1746 + mhba->regs = kzalloc(sizeof(*regs), GFP_KERNEL); 1747 + if (mhba->regs == NULL) 1748 + return -ENOMEM; 1749 + } 1750 + regs = mhba->regs; 1751 + /* For Arm */ 1752 + regs->ctrl_sts_reg = base + 0x20104; 1753 + regs->rstoutn_mask_reg = base + 0x1010C; 1754 + regs->sys_soft_rst_reg = base + 0x10108; 1755 + regs->main_int_cause_reg = base + 0x10200; 1756 + regs->enpointa_mask_reg = base + 0x1020C; 1757 + regs->rstoutn_en_reg = base + 0xF1400; 1758 + 1759 + /* For Doorbell */ 1760 + regs->pciea_to_arm_drbl_reg = base + 0x10460; 1761 + regs->arm_to_pciea_drbl_reg = base + 0x10480; 1762 + regs->arm_to_pciea_mask_reg = base + 0x10484; 1763 + regs->pciea_to_arm_msg0 = base + 0x10400; 1764 + regs->pciea_to_arm_msg1 = base + 0x10404; 1765 + regs->arm_to_pciea_msg0 = base + 0x10420; 1766 + regs->arm_to_pciea_msg1 = base + 0x10424; 1767 + 1768 + /* For reset*/ 1769 + regs->reset_request = base + 0x10108; 1770 + regs->reset_enable = base + 0x1010c; 1771 + 1772 + /* For Message Unit */ 1773 + regs->inb_aval_count_basel = base + 0x4008; 1774 + regs->inb_aval_count_baseh = base + 0x400C; 1775 + regs->inb_write_pointer = base + 0x4018; 1776 + regs->inb_read_pointer = base + 0x401C; 1777 + regs->outb_copy_basel = base + 0x4058; 1778 + regs->outb_copy_baseh = base + 0x405C; 1779 + regs->outb_copy_pointer = base + 0x406C; 1780 + regs->outb_read_pointer = base + 0x4070; 1781 + regs->outb_coal_cfg = base + 0x4080; 1782 + regs->outb_isr_cause = base + 0x4088; 1783 + /* Bit setting for HW */ 1784 + regs->int_comaout = 1 << 4; 1785 + regs->int_dl_cpu2pciea = 1 << 12; 1786 + regs->int_comaerr = 1 << 29; 1787 + regs->cl_pointer_toggle = 1 << 14; 1788 + regs->cl_slot_num_mask = 0x3FFF; 1789 + regs->clic_irq = 1 << 0; 1790 + regs->clic_out_err = 1 << 1; 1791 + regs->int_drbl_int_mask = 0x3FFFFFFF; 1792 + regs->int_mu = regs->int_dl_cpu2pciea | regs->int_comaout; 1793 + break; 1794 + default: 1795 + return -1; 1796 + break; 1797 + } 1798 + 1799 + return 0; 1800 + } 1801 + 2240 1802 /** 2241 1803 * mvumi_init_fw - Initializes the FW 2242 1804 * @mhba: Adapter soft state ··· 2373 1699 if (ret) 2374 1700 goto fail_ioremap; 2375 1701 2376 - mhba->mmio = mhba->base_addr[0]; 2377 - 2378 1702 switch (mhba->pdev->device) { 2379 1703 case PCI_DEVICE_ID_MARVELL_MV9143: 2380 - mhba->instancet = &mvumi_instance_template; 1704 + mhba->instancet = &mvumi_instance_9143; 2381 1705 mhba->io_seq = 0; 2382 1706 mhba->max_sge = MVUMI_MAX_SG_ENTRY; 2383 1707 mhba->request_id_enabled = 1; 1708 + break; 1709 + case PCI_DEVICE_ID_MARVELL_MV9580: 1710 + mhba->instancet = &mvumi_instance_9580; 1711 + mhba->io_seq = 0; 1712 + mhba->max_sge = MVUMI_MAX_SG_ENTRY; 2384 1713 break; 2385 1714 default: 2386 1715 dev_err(&mhba->pdev->dev, "device 0x%x not supported!\n", ··· 2394 1717 } 2395 1718 dev_dbg(&mhba->pdev->dev, "device id : %04X is found.\n", 2396 1719 mhba->pdev->device); 2397 - 2398 - mhba->handshake_page = kzalloc(HSP_MAX_SIZE, GFP_KERNEL); 1720 + ret = mvumi_cfg_hw_reg(mhba); 1721 + if (ret) { 1722 + dev_err(&mhba->pdev->dev, 1723 + "failed to allocate memory for reg\n"); 1724 + ret = -ENOMEM; 1725 + goto fail_alloc_mem; 1726 + } 1727 + mhba->handshake_page = pci_alloc_consistent(mhba->pdev, HSP_MAX_SIZE, 1728 + &mhba->handshake_page_phys); 2399 1729 if (!mhba->handshake_page) { 2400 1730 dev_err(&mhba->pdev->dev, 2401 1731 "failed to allocate memory for handshake\n"); 2402 1732 ret = -ENOMEM; 2403 - goto fail_alloc_mem; 1733 + goto fail_alloc_page; 2404 1734 } 2405 - mhba->handshake_page_phys = virt_to_phys(mhba->handshake_page); 2406 1735 2407 1736 if (mvumi_start(mhba)) { 2408 1737 ret = -EINVAL; ··· 2422 1739 2423 1740 fail_ready_state: 2424 1741 mvumi_release_mem_resource(mhba); 2425 - kfree(mhba->handshake_page); 1742 + pci_free_consistent(mhba->pdev, HSP_MAX_SIZE, 1743 + mhba->handshake_page, mhba->handshake_page_phys); 1744 + fail_alloc_page: 1745 + kfree(mhba->regs); 2426 1746 fail_alloc_mem: 2427 1747 mvumi_unmap_pci_addr(mhba->pdev, mhba->base_addr); 2428 1748 fail_ioremap: ··· 2441 1755 static int mvumi_io_attach(struct mvumi_hba *mhba) 2442 1756 { 2443 1757 struct Scsi_Host *host = mhba->shost; 1758 + struct scsi_device *sdev = NULL; 2444 1759 int ret; 2445 1760 unsigned int max_sg = (mhba->ib_max_size + 4 - 2446 1761 sizeof(struct mvumi_msg_frame)) / sizeof(struct mvumi_sgl); ··· 2451 1764 host->can_queue = (mhba->max_io - 1) ? (mhba->max_io - 1) : 1; 2452 1765 host->sg_tablesize = mhba->max_sge > max_sg ? max_sg : mhba->max_sge; 2453 1766 host->max_sectors = mhba->max_transfer_size / 512; 2454 - host->cmd_per_lun = (mhba->max_io - 1) ? (mhba->max_io - 1) : 1; 1767 + host->cmd_per_lun = (mhba->max_io - 1) ? (mhba->max_io - 1) : 1; 2455 1768 host->max_id = mhba->max_target_id; 2456 1769 host->max_cmd_len = MAX_COMMAND_SIZE; 2457 1770 host->transportt = &mvumi_transport_template; ··· 2462 1775 return ret; 2463 1776 } 2464 1777 mhba->fw_flag |= MVUMI_FW_ATTACH; 2465 - scsi_scan_host(host); 2466 1778 1779 + mutex_lock(&mhba->sas_discovery_mutex); 1780 + if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9580) 1781 + ret = scsi_add_device(host, 0, mhba->max_target_id - 1, 0); 1782 + else 1783 + ret = 0; 1784 + if (ret) { 1785 + dev_err(&mhba->pdev->dev, "add virtual device failed\n"); 1786 + mutex_unlock(&mhba->sas_discovery_mutex); 1787 + goto fail_add_device; 1788 + } 1789 + 1790 + mhba->dm_thread = kthread_create(mvumi_rescan_bus, 1791 + mhba, "mvumi_scanthread"); 1792 + if (IS_ERR(mhba->dm_thread)) { 1793 + dev_err(&mhba->pdev->dev, 1794 + "failed to create device scan thread\n"); 1795 + mutex_unlock(&mhba->sas_discovery_mutex); 1796 + goto fail_create_thread; 1797 + } 1798 + atomic_set(&mhba->pnp_count, 1); 1799 + wake_up_process(mhba->dm_thread); 1800 + 1801 + mutex_unlock(&mhba->sas_discovery_mutex); 2467 1802 return 0; 1803 + 1804 + fail_create_thread: 1805 + if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9580) 1806 + sdev = scsi_device_lookup(mhba->shost, 0, 1807 + mhba->max_target_id - 1, 0); 1808 + if (sdev) { 1809 + scsi_remove_device(sdev); 1810 + scsi_device_put(sdev); 1811 + } 1812 + fail_add_device: 1813 + scsi_remove_host(mhba->shost); 1814 + return ret; 2468 1815 } 2469 1816 2470 1817 /** ··· 2549 1828 INIT_LIST_HEAD(&mhba->free_ob_list); 2550 1829 INIT_LIST_HEAD(&mhba->res_list); 2551 1830 INIT_LIST_HEAD(&mhba->waiting_req_list); 1831 + mutex_init(&mhba->device_lock); 1832 + INIT_LIST_HEAD(&mhba->mhba_dev_list); 1833 + INIT_LIST_HEAD(&mhba->shost_dev_list); 2552 1834 atomic_set(&mhba->fw_outstanding, 0); 2553 1835 init_waitqueue_head(&mhba->int_cmd_wait_q); 1836 + mutex_init(&mhba->sas_discovery_mutex); 2554 1837 2555 1838 mhba->pdev = pdev; 2556 1839 mhba->shost = host; ··· 2570 1845 dev_err(&pdev->dev, "failed to register IRQ\n"); 2571 1846 goto fail_init_irq; 2572 1847 } 2573 - mhba->instancet->enable_intr(mhba->mmio); 1848 + 1849 + mhba->instancet->enable_intr(mhba); 2574 1850 pci_set_drvdata(pdev, mhba); 2575 1851 2576 1852 ret = mvumi_io_attach(mhba); 2577 1853 if (ret) 2578 1854 goto fail_io_attach; 1855 + 1856 + mvumi_backup_bar_addr(mhba); 2579 1857 dev_dbg(&pdev->dev, "probe mvumi driver successfully.\n"); 2580 1858 2581 1859 return 0; 2582 1860 2583 1861 fail_io_attach: 2584 1862 pci_set_drvdata(pdev, NULL); 2585 - mhba->instancet->disable_intr(mhba->mmio); 1863 + mhba->instancet->disable_intr(mhba); 2586 1864 free_irq(mhba->pdev->irq, mhba); 2587 1865 fail_init_irq: 2588 1866 mvumi_release_fw(mhba); ··· 2605 1877 struct mvumi_hba *mhba; 2606 1878 2607 1879 mhba = pci_get_drvdata(pdev); 1880 + if (mhba->dm_thread) { 1881 + kthread_stop(mhba->dm_thread); 1882 + mhba->dm_thread = NULL; 1883 + } 1884 + 1885 + mvumi_detach_devices(mhba); 2608 1886 host = mhba->shost; 2609 1887 scsi_remove_host(mhba->shost); 2610 1888 mvumi_flush_cache(mhba); 2611 1889 2612 - mhba->instancet->disable_intr(mhba->mmio); 1890 + mhba->instancet->disable_intr(mhba); 2613 1891 free_irq(mhba->pdev->irq, mhba); 2614 1892 mvumi_release_fw(mhba); 2615 1893 scsi_host_put(host); ··· 2643 1909 mvumi_flush_cache(mhba); 2644 1910 2645 1911 pci_set_drvdata(pdev, mhba); 2646 - mhba->instancet->disable_intr(mhba->mmio); 1912 + mhba->instancet->disable_intr(mhba); 2647 1913 free_irq(mhba->pdev->irq, mhba); 2648 1914 mvumi_unmap_pci_addr(pdev, mhba->base_addr); 2649 1915 pci_release_regions(pdev); ··· 2690 1956 if (ret) 2691 1957 goto release_regions; 2692 1958 1959 + if (mvumi_cfg_hw_reg(mhba)) { 1960 + ret = -EINVAL; 1961 + goto unmap_pci_addr; 1962 + } 1963 + 2693 1964 mhba->mmio = mhba->base_addr[0]; 2694 - mvumi_reset(mhba->mmio); 1965 + mvumi_reset(mhba); 2695 1966 2696 1967 if (mvumi_start(mhba)) { 2697 1968 ret = -EINVAL; ··· 2709 1970 dev_err(&pdev->dev, "failed to register IRQ\n"); 2710 1971 goto unmap_pci_addr; 2711 1972 } 2712 - mhba->instancet->enable_intr(mhba->mmio); 1973 + mhba->instancet->enable_intr(mhba); 2713 1974 2714 1975 return 0; 2715 1976
+154 -85
drivers/scsi/mvumi.h
··· 34 34 #define MV_DRIVER_NAME "mvumi" 35 35 #define PCI_VENDOR_ID_MARVELL_2 0x1b4b 36 36 #define PCI_DEVICE_ID_MARVELL_MV9143 0x9143 37 + #define PCI_DEVICE_ID_MARVELL_MV9580 0x9580 37 38 38 39 #define MVUMI_INTERNAL_CMD_WAIT_TIME 45 40 + #define MVUMI_INQUIRY_LENGTH 44 41 + #define MVUMI_INQUIRY_UUID_OFF 36 42 + #define MVUMI_INQUIRY_UUID_LEN 8 39 43 40 44 #define IS_DMA64 (sizeof(dma_addr_t) == 8) 41 45 42 46 enum mvumi_qc_result { 43 - MV_QUEUE_COMMAND_RESULT_SENT = 0, 47 + MV_QUEUE_COMMAND_RESULT_SENT = 0, 44 48 MV_QUEUE_COMMAND_RESULT_NO_RESOURCE, 45 49 }; 46 50 51 + struct mvumi_hw_regs { 52 + /* For CPU */ 53 + void *main_int_cause_reg; 54 + void *enpointa_mask_reg; 55 + void *enpointb_mask_reg; 56 + void *rstoutn_en_reg; 57 + void *ctrl_sts_reg; 58 + void *rstoutn_mask_reg; 59 + void *sys_soft_rst_reg; 60 + 61 + /* For Doorbell */ 62 + void *pciea_to_arm_drbl_reg; 63 + void *arm_to_pciea_drbl_reg; 64 + void *arm_to_pciea_mask_reg; 65 + void *pciea_to_arm_msg0; 66 + void *pciea_to_arm_msg1; 67 + void *arm_to_pciea_msg0; 68 + void *arm_to_pciea_msg1; 69 + 70 + /* reset register */ 71 + void *reset_request; 72 + void *reset_enable; 73 + 74 + /* For Message Unit */ 75 + void *inb_list_basel; 76 + void *inb_list_baseh; 77 + void *inb_aval_count_basel; 78 + void *inb_aval_count_baseh; 79 + void *inb_write_pointer; 80 + void *inb_read_pointer; 81 + void *outb_list_basel; 82 + void *outb_list_baseh; 83 + void *outb_copy_basel; 84 + void *outb_copy_baseh; 85 + void *outb_copy_pointer; 86 + void *outb_read_pointer; 87 + void *inb_isr_cause; 88 + void *outb_isr_cause; 89 + void *outb_coal_cfg; 90 + void *outb_coal_timeout; 91 + 92 + /* Bit setting for HW */ 93 + u32 int_comaout; 94 + u32 int_comaerr; 95 + u32 int_dl_cpu2pciea; 96 + u32 int_mu; 97 + u32 int_drbl_int_mask; 98 + u32 int_main_int_mask; 99 + u32 cl_pointer_toggle; 100 + u32 cl_slot_num_mask; 101 + u32 clic_irq; 102 + u32 clic_in_err; 103 + u32 clic_out_err; 104 + }; 105 + 106 + struct mvumi_dyn_list_entry { 107 + u32 src_low_addr; 108 + u32 src_high_addr; 109 + u32 if_length; 110 + u32 reserve; 111 + }; 112 + 113 + #define SCSI_CMD_MARVELL_SPECIFIC 0xE1 114 + #define CDB_CORE_MODULE 0x1 115 + #define CDB_CORE_SHUTDOWN 0xB 116 + 47 117 enum { 48 - /*******************************************/ 49 - 50 - /* ARM Mbus Registers Map */ 51 - 52 - /*******************************************/ 53 - CPU_MAIN_INT_CAUSE_REG = 0x20200, 54 - CPU_MAIN_IRQ_MASK_REG = 0x20204, 55 - CPU_MAIN_FIQ_MASK_REG = 0x20208, 56 - CPU_ENPOINTA_MASK_REG = 0x2020C, 57 - CPU_ENPOINTB_MASK_REG = 0x20210, 58 - 59 - INT_MAP_COMAERR = 1 << 6, 60 - INT_MAP_COMAIN = 1 << 7, 61 - INT_MAP_COMAOUT = 1 << 8, 62 - INT_MAP_COMBERR = 1 << 9, 63 - INT_MAP_COMBIN = 1 << 10, 64 - INT_MAP_COMBOUT = 1 << 11, 65 - 66 - INT_MAP_COMAINT = (INT_MAP_COMAOUT | INT_MAP_COMAERR), 67 - INT_MAP_COMBINT = (INT_MAP_COMBOUT | INT_MAP_COMBIN | INT_MAP_COMBERR), 68 - 69 - INT_MAP_DL_PCIEA2CPU = 1 << 0, 70 - INT_MAP_DL_CPU2PCIEA = 1 << 1, 71 - 72 - /***************************************/ 73 - 74 - /* ARM Doorbell Registers Map */ 75 - 76 - /***************************************/ 77 - CPU_PCIEA_TO_ARM_DRBL_REG = 0x20400, 78 - CPU_PCIEA_TO_ARM_MASK_REG = 0x20404, 79 - CPU_ARM_TO_PCIEA_DRBL_REG = 0x20408, 80 - CPU_ARM_TO_PCIEA_MASK_REG = 0x2040C, 81 - 82 118 DRBL_HANDSHAKE = 1 << 0, 83 119 DRBL_SOFT_RESET = 1 << 1, 84 120 DRBL_BUS_CHANGE = 1 << 2, 85 121 DRBL_EVENT_NOTIFY = 1 << 3, 86 122 DRBL_MU_RESET = 1 << 4, 87 123 DRBL_HANDSHAKE_ISR = DRBL_HANDSHAKE, 88 - 89 - CPU_PCIEA_TO_ARM_MSG0 = 0x20430, 90 - CPU_PCIEA_TO_ARM_MSG1 = 0x20434, 91 - CPU_ARM_TO_PCIEA_MSG0 = 0x20438, 92 - CPU_ARM_TO_PCIEA_MSG1 = 0x2043C, 93 - 94 - /*******************************************/ 95 - 96 - /* ARM Communication List Registers Map */ 97 - 98 - /*******************************************/ 99 - CLA_INB_LIST_BASEL = 0x500, 100 - CLA_INB_LIST_BASEH = 0x504, 101 - CLA_INB_AVAL_COUNT_BASEL = 0x508, 102 - CLA_INB_AVAL_COUNT_BASEH = 0x50C, 103 - CLA_INB_DESTI_LIST_BASEL = 0x510, 104 - CLA_INB_DESTI_LIST_BASEH = 0x514, 105 - CLA_INB_WRITE_POINTER = 0x518, 106 - CLA_INB_READ_POINTER = 0x51C, 107 - 108 - CLA_OUTB_LIST_BASEL = 0x530, 109 - CLA_OUTB_LIST_BASEH = 0x534, 110 - CLA_OUTB_SOURCE_LIST_BASEL = 0x538, 111 - CLA_OUTB_SOURCE_LIST_BASEH = 0x53C, 112 - CLA_OUTB_COPY_POINTER = 0x544, 113 - CLA_OUTB_READ_POINTER = 0x548, 114 - 115 - CLA_ISR_CAUSE = 0x560, 116 - CLA_ISR_MASK = 0x564, 117 - 118 - INT_MAP_MU = (INT_MAP_DL_CPU2PCIEA | INT_MAP_COMAINT), 119 - 120 - CL_POINTER_TOGGLE = 1 << 12, 121 - 122 - CLIC_IN_IRQ = 1 << 0, 123 - CLIC_OUT_IRQ = 1 << 1, 124 - CLIC_IN_ERR_IRQ = 1 << 8, 125 - CLIC_OUT_ERR_IRQ = 1 << 12, 126 - 127 - CL_SLOT_NUM_MASK = 0xFFF, 128 124 129 125 /* 130 126 * Command flag is the flag for the CDB command itself ··· 133 137 CMD_FLAG_DATA_IN = 1 << 3, 134 138 /* 1-host write data */ 135 139 CMD_FLAG_DATA_OUT = 1 << 4, 136 - 137 - SCSI_CMD_MARVELL_SPECIFIC = 0xE1, 138 - CDB_CORE_SHUTDOWN = 0xB, 140 + CMD_FLAG_PRDT_IN_HOST = 1 << 5, 139 141 }; 140 142 141 143 #define APICDB0_EVENT 0xF4 142 144 #define APICDB1_EVENT_GETEVENT 0 145 + #define APICDB1_HOST_GETEVENT 1 143 146 #define MAX_EVENTS_RETURNED 6 147 + 148 + #define DEVICE_OFFLINE 0 149 + #define DEVICE_ONLINE 1 150 + 151 + struct mvumi_hotplug_event { 152 + u16 size; 153 + u8 dummy[2]; 154 + u8 bitmap[0]; 155 + }; 144 156 145 157 struct mvumi_driver_event { 146 158 u32 time_stamp; ··· 176 172 void *param; 177 173 }; 178 174 175 + #define HS_CAPABILITY_SUPPORT_COMPACT_SG (1U << 4) 176 + #define HS_CAPABILITY_SUPPORT_PRD_HOST (1U << 5) 177 + #define HS_CAPABILITY_SUPPORT_DYN_SRC (1U << 6) 178 + #define HS_CAPABILITY_NEW_PAGE_IO_DEPTH_DEF (1U << 14) 179 + 179 180 #define MVUMI_MAX_SG_ENTRY 32 180 181 #define SGD_EOT (1L << 27) 182 + #define SGD_EOT_CP (1L << 22) 181 183 182 184 struct mvumi_sgl { 183 185 u32 baseaddr_l; ··· 191 181 u32 flags; 192 182 u32 size; 193 183 }; 184 + struct mvumi_compact_sgl { 185 + u32 baseaddr_l; 186 + u32 baseaddr_h; 187 + u32 flags; 188 + }; 189 + 190 + #define GET_COMPACT_SGD_SIZE(sgd) \ 191 + ((((struct mvumi_compact_sgl *)(sgd))->flags) & 0x3FFFFFL) 192 + 193 + #define SET_COMPACT_SGD_SIZE(sgd, sz) do { \ 194 + (((struct mvumi_compact_sgl *)(sgd))->flags) &= ~0x3FFFFFL; \ 195 + (((struct mvumi_compact_sgl *)(sgd))->flags) |= (sz); \ 196 + } while (0) 197 + #define sgd_getsz(_mhba, sgd, sz) do { \ 198 + if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \ 199 + (sz) = GET_COMPACT_SGD_SIZE(sgd); \ 200 + else \ 201 + (sz) = (sgd)->size; \ 202 + } while (0) 203 + 204 + #define sgd_setsz(_mhba, sgd, sz) do { \ 205 + if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \ 206 + SET_COMPACT_SGD_SIZE(sgd, sz); \ 207 + else \ 208 + (sgd)->size = (sz); \ 209 + } while (0) 210 + 211 + #define sgd_inc(_mhba, sgd) do { \ 212 + if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \ 213 + sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 12); \ 214 + else \ 215 + sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 16); \ 216 + } while (0) 194 217 195 218 struct mvumi_res { 196 219 struct list_head entry; ··· 240 197 }; 241 198 242 199 struct mvumi_sense_data { 243 - u8 error_eode:7; 200 + u8 error_code:7; 244 201 u8 valid:1; 245 202 u8 segment_number; 246 203 u8 sense_key:4; ··· 263 220 struct mvumi_cmd { 264 221 struct list_head queue_pointer; 265 222 struct mvumi_msg_frame *frame; 223 + dma_addr_t frame_phys; 266 224 struct scsi_cmnd *scmd; 267 225 atomic_t sync_cmd; 268 226 void *data_buf; ··· 437 393 u16 frame_length; 438 394 439 395 u8 host_type; 440 - u8 reserved[3]; 396 + u8 host_cap; 397 + u8 reserved[2]; 441 398 struct version_info host_ver; 442 399 u32 system_io_bus; 443 400 u32 slot_number; ··· 480 435 unsigned short size; 481 436 }; 482 437 438 + struct mvumi_device { 439 + struct list_head list; 440 + struct scsi_device *sdev; 441 + u64 wwid; 442 + u8 dev_type; 443 + int id; 444 + }; 445 + 483 446 struct mvumi_hba { 484 447 void *base_addr[MAX_BASE_ADDRESS]; 448 + u32 pci_base[MAX_BASE_ADDRESS]; 485 449 void *mmio; 486 450 struct list_head cmd_pool; 487 451 struct Scsi_Host *shost; ··· 502 448 503 449 void *ib_list; 504 450 dma_addr_t ib_list_phys; 451 + 452 + void *ib_frame; 453 + dma_addr_t ib_frame_phys; 505 454 506 455 void *ob_list; 507 456 dma_addr_t ob_list_phys; ··· 534 477 unsigned char hba_total_pages; 535 478 unsigned char fw_flag; 536 479 unsigned char request_id_enabled; 480 + unsigned char eot_flag; 537 481 unsigned short hba_capability; 538 482 unsigned short io_seq; 539 483 540 484 unsigned int ib_cur_slot; 541 485 unsigned int ob_cur_slot; 542 486 unsigned int fw_state; 487 + struct mutex sas_discovery_mutex; 543 488 544 489 struct list_head ob_data_list; 545 490 struct list_head free_ob_list; ··· 550 491 551 492 struct mvumi_tag tag_pool; 552 493 struct mvumi_cmd **tag_cmd; 494 + struct mvumi_hw_regs *regs; 495 + struct mutex device_lock; 496 + struct list_head mhba_dev_list; 497 + struct list_head shost_dev_list; 498 + struct task_struct *dm_thread; 499 + atomic_t pnp_count; 553 500 }; 554 501 555 502 struct mvumi_instance_template { 556 - void (*fire_cmd)(struct mvumi_hba *, struct mvumi_cmd *); 557 - void (*enable_intr)(void *) ; 558 - void (*disable_intr)(void *); 559 - int (*clear_intr)(void *); 560 - unsigned int (*read_fw_status_reg)(void *); 503 + void (*fire_cmd) (struct mvumi_hba *, struct mvumi_cmd *); 504 + void (*enable_intr) (struct mvumi_hba *); 505 + void (*disable_intr) (struct mvumi_hba *); 506 + int (*clear_intr) (void *); 507 + unsigned int (*read_fw_status_reg) (struct mvumi_hba *); 508 + unsigned int (*check_ib_list) (struct mvumi_hba *); 509 + int (*check_ob_list) (struct mvumi_hba *, unsigned int *, 510 + unsigned int *); 511 + int (*reset_host) (struct mvumi_hba *); 561 512 }; 562 513 563 514 extern struct timezone sys_tz;