tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/amd/psp: Add C2P registers to mp_13_0_2 header

Add additional registers.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Andrey Grodzovsky and committed by
Alex Deucher bce04f21 594a1d0f

+120
+48
drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h
··· 172 172 #define regMP0_SMN_C2PMSG_102_BASE_IDX 0 173 173 #define regMP0_SMN_C2PMSG_103 0x00a7 174 174 #define regMP0_SMN_C2PMSG_103_BASE_IDX 0 175 + #define regMP0_SMN_C2PMSG_104 0x00a8 176 + #define regMP0_SMN_C2PMSG_104_BASE_IDX 0 177 + #define regMP0_SMN_C2PMSG_105 0x00a9 178 + #define regMP0_SMN_C2PMSG_105_BASE_IDX 0 179 + #define regMP0_SMN_C2PMSG_106 0x00aa 180 + #define regMP0_SMN_C2PMSG_106_BASE_IDX 0 181 + #define regMP0_SMN_C2PMSG_107 0x00ab 182 + #define regMP0_SMN_C2PMSG_107_BASE_IDX 0 183 + #define regMP0_SMN_C2PMSG_108 0x00ac 184 + #define regMP0_SMN_C2PMSG_108_BASE_IDX 0 185 + #define regMP0_SMN_C2PMSG_109 0x00ad 186 + #define regMP0_SMN_C2PMSG_109_BASE_IDX 0 187 + #define regMP0_SMN_C2PMSG_110 0x00ae 188 + #define regMP0_SMN_C2PMSG_110_BASE_IDX 0 189 + #define regMP0_SMN_C2PMSG_111 0x00af 190 + #define regMP0_SMN_C2PMSG_111_BASE_IDX 0 191 + #define regMP0_SMN_C2PMSG_112 0x00b0 192 + #define regMP0_SMN_C2PMSG_112_BASE_IDX 0 193 + #define regMP0_SMN_C2PMSG_113 0x00b1 194 + #define regMP0_SMN_C2PMSG_113_BASE_IDX 0 195 + #define regMP0_SMN_C2PMSG_114 0x00b2 196 + #define regMP0_SMN_C2PMSG_114_BASE_IDX 0 197 + #define regMP0_SMN_C2PMSG_115 0x00b3 198 + #define regMP0_SMN_C2PMSG_115_BASE_IDX 0 199 + #define regMP0_SMN_C2PMSG_116 0x00b4 200 + #define regMP0_SMN_C2PMSG_116_BASE_IDX 0 201 + #define regMP0_SMN_C2PMSG_117 0x00b5 202 + #define regMP0_SMN_C2PMSG_117_BASE_IDX 0 203 + #define regMP0_SMN_C2PMSG_118 0x00b6 204 + #define regMP0_SMN_C2PMSG_118_BASE_IDX 0 205 + #define regMP0_SMN_C2PMSG_119 0x00b7 206 + #define regMP0_SMN_C2PMSG_119_BASE_IDX 0 207 + #define regMP0_SMN_C2PMSG_120 0x00b8 208 + #define regMP0_SMN_C2PMSG_120_BASE_IDX 0 209 + #define regMP0_SMN_C2PMSG_121 0x00b9 210 + #define regMP0_SMN_C2PMSG_121_BASE_IDX 0 211 + #define regMP0_SMN_C2PMSG_122 0x00ba 212 + #define regMP0_SMN_C2PMSG_122_BASE_IDX 0 213 + #define regMP0_SMN_C2PMSG_123 0x00bb 214 + #define regMP0_SMN_C2PMSG_123_BASE_IDX 0 215 + #define regMP0_SMN_C2PMSG_124 0x00bc 216 + #define regMP0_SMN_C2PMSG_124_BASE_IDX 0 217 + #define regMP0_SMN_C2PMSG_125 0x00bd 218 + #define regMP0_SMN_C2PMSG_125_BASE_IDX 0 219 + #define regMP0_SMN_C2PMSG_126 0x00be 220 + #define regMP0_SMN_C2PMSG_126_BASE_IDX 0 221 + #define regMP0_SMN_C2PMSG_127 0x00bf 222 + #define regMP0_SMN_C2PMSG_127_BASE_IDX 0 175 223 #define regMP0_SMN_IH_CREDIT 0x00c1 176 224 #define regMP0_SMN_IH_CREDIT_BASE_IDX 0 177 225 #define regMP0_SMN_IH_SW_INT 0x00c2
+72
drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h
··· 484 484 //MP1_SMN_C2PMSG_103 485 485 #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 486 486 #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 487 + //MP1_SMN_C2PMSG_104 488 + #define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0 489 + #define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL 490 + //MP1_SMN_C2PMSG_105 491 + #define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0 492 + #define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL 493 + //MP1_SMN_C2PMSG_106 494 + #define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0 495 + #define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL 496 + //MP1_SMN_C2PMSG_107 497 + #define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0 498 + #define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL 499 + //MP1_SMN_C2PMSG_108 500 + #define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0 501 + #define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL 502 + //MP1_SMN_C2PMSG_109 503 + #define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 504 + #define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL 505 + //MP1_SMN_C2PMSG_110 506 + #define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0 507 + #define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL 508 + //MP1_SMN_C2PMSG_111 509 + #define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0 510 + #define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL 511 + //MP1_SMN_C2PMSG_112 512 + #define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0 513 + #define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL 514 + //MP1_SMN_C2PMSG_113 515 + #define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0 516 + #define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL 517 + //MP1_SMN_C2PMSG_114 518 + #define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0 519 + #define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL 520 + //MP1_SMN_C2PMSG_115 521 + #define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0 522 + #define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL 523 + //MP1_SMN_C2PMSG_116 524 + #define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0 525 + #define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL 526 + //MP1_SMN_C2PMSG_117 527 + #define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0 528 + #define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL 529 + //MP1_SMN_C2PMSG_118 530 + #define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0 531 + #define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL 532 + //MP1_SMN_C2PMSG_119 533 + #define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0 534 + #define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL 535 + //MP1_SMN_C2PMSG_120 536 + #define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0 537 + #define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL 538 + //MP1_SMN_C2PMSG_121 539 + #define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0 540 + #define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL 541 + //MP1_SMN_C2PMSG_122 542 + #define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0 543 + #define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL 544 + //MP1_SMN_C2PMSG_123 545 + #define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0 546 + #define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL 547 + //MP1_SMN_C2PMSG_124 548 + #define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0 549 + #define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL 550 + //MP1_SMN_C2PMSG_125 551 + #define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0 552 + #define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL 553 + //MP1_SMN_C2PMSG_126 554 + #define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0 555 + #define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL 556 + //MP1_SMN_C2PMSG_127 557 + #define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0 558 + #define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL 487 559 //MP1_SMN_IH_CREDIT 488 560 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 489 561 #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10