Merge tag 'mips_5.2_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

+6

arch/mips/Kconfig

··· 674 674 select SYS_HAS_EARLY_PRINTK 675 675 select HAVE_PCI 676 676 select IRQ_MIPS_CPU 677 + select IRQ_DOMAIN_HIERARCHY 677 678 select NR_CPUS_DEFAULT_64 679 + select PCI_DRIVERS_GENERIC 680 + select PCI_XTALK_BRIDGE 678 681 select SYS_HAS_CPU_R10000 679 682 select SYS_SUPPORTS_64BIT_KERNEL 680 683 select SYS_SUPPORTS_BIG_ENDIAN ··· 1242 1239 bool 1243 1240 1244 1241 config PCI_GT64XXX_PCI0 1242 + bool 1243 + 1244 + config PCI_XTALK_BRIDGE 1245 1245 bool 1246 1246 1247 1247 config NO_EXCEPT_FILL

+14 -8

arch/mips/alchemy/common/platform.c

··· 131 131 } 132 132 133 133 134 - /* The dmamask must be set for OHCI/EHCI to work */ 135 - static u64 alchemy_ohci_dmamask = DMA_BIT_MASK(32); 136 - static u64 __maybe_unused alchemy_ehci_dmamask = DMA_BIT_MASK(32); 134 + static u64 alchemy_all_dmamask = DMA_BIT_MASK(32); 137 135 138 136 /* Power on callback for the ehci platform driver */ 139 137 static int alchemy_ehci_power_on(struct platform_device *pdev) ··· 229 231 res[1].flags = IORESOURCE_IRQ; 230 232 pdev->name = "ohci-platform"; 231 233 pdev->id = 0; 232 - pdev->dev.dma_mask = &alchemy_ohci_dmamask; 234 + pdev->dev.dma_mask = &alchemy_all_dmamask; 233 235 pdev->dev.platform_data = &alchemy_ohci_pdata; 234 236 235 237 if (platform_device_register(pdev)) ··· 249 251 res[1].flags = IORESOURCE_IRQ; 250 252 pdev->name = "ehci-platform"; 251 253 pdev->id = 0; 252 - pdev->dev.dma_mask = &alchemy_ehci_dmamask; 254 + pdev->dev.dma_mask = &alchemy_all_dmamask; 253 255 pdev->dev.platform_data = &alchemy_ehci_pdata; 254 256 255 257 if (platform_device_register(pdev)) ··· 269 271 res[1].flags = IORESOURCE_IRQ; 270 272 pdev->name = "ohci-platform"; 271 273 pdev->id = 1; 272 - pdev->dev.dma_mask = &alchemy_ohci_dmamask; 274 + pdev->dev.dma_mask = &alchemy_all_dmamask; 273 275 pdev->dev.platform_data = &alchemy_ohci_pdata; 274 276 275 277 if (platform_device_register(pdev)) ··· 336 338 .name = "au1000-eth", 337 339 .id = 0, 338 340 .num_resources = MAC_RES_COUNT, 339 - .dev.platform_data = &au1xxx_eth0_platform_data, 341 + .dev = { 342 + .dma_mask = &alchemy_all_dmamask, 343 + .coherent_dma_mask = DMA_BIT_MASK(32), 344 + .platform_data = &au1xxx_eth0_platform_data, 345 + }, 340 346 }; 341 347 342 348 static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = { ··· 372 370 .name = "au1000-eth", 373 371 .id = 1, 374 372 .num_resources = MAC_RES_COUNT, 375 - .dev.platform_data = &au1xxx_eth1_platform_data, 373 + .dev = { 374 + .dma_mask = &alchemy_all_dmamask, 375 + .coherent_dma_mask = DMA_BIT_MASK(32), 376 + .platform_data = &au1xxx_eth1_platform_data, 377 + }, 376 378 }; 377 379 378 380 void __init au1xxx_override_eth_cfg(unsigned int port,

+2 -2

arch/mips/generic/init.c

··· 43 43 /* Already set up */ 44 44 return (void *)fdt; 45 45 46 - if ((fw_arg0 == -2) && !fdt_check_header((void *)fw_arg1)) { 46 + if ((fw_arg0 == -2) && !fdt_check_header((void *)fw_passed_dtb)) { 47 47 /* 48 48 * We booted using the UHI boot protocol, so we have been 49 49 * provided with the appropriate device tree for the board. 50 50 * Make use of it & search for any machine struct based upon 51 51 * the root compatible string. 52 52 */ 53 - fdt = (void *)fw_arg1; 53 + fdt = (void *)fw_passed_dtb; 54 54 55 55 for_each_mips_machine(check_mach) { 56 56 match = mips_machine_is_compatible(check_mach, fdt);

+1 -10

arch/mips/include/asm/mach-ip27/topology.h

··· 7 7 #include <asm/mmzone.h> 8 8 9 9 struct cpuinfo_ip27 { 10 - // cpuid_t p_cpuid; /* PROM assigned cpuid */ 11 10 cnodeid_t p_nodeid; /* my node ID in compact-id-space */ 12 11 nasid_t p_nasid; /* my node ID in numa-as-id-space */ 13 12 unsigned char p_slice; /* Physical position on node board */ 14 - #if 0 15 - unsigned long loops_per_sec; 16 - unsigned long ipi_count; 17 - unsigned long irq_attempt[NR_IRQS]; 18 - unsigned long smp_local_irq_count; 19 - unsigned long prof_multiplier; 20 - unsigned long prof_counter; 21 - #endif 22 13 }; 23 14 24 15 extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS]; ··· 21 30 struct pci_bus; 22 31 extern int pcibus_to_node(struct pci_bus *); 23 32 24 - #define cpumask_of_pcibus(bus) (cpu_online_mask) 33 + #define cpumask_of_pcibus(bus) (cpumask_of_node(pcibus_to_node(bus))) 25 34 26 35 extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES]; 27 36

+4 -10

arch/mips/include/asm/pci/bridge.h

··· 801 801 #define PCI64_ATTR_RMF_SHFT 48 802 802 803 803 struct bridge_controller { 804 - struct pci_controller pc; 805 - struct resource mem; 806 - struct resource io; 807 804 struct resource busn; 808 805 struct bridge_regs *base; 809 - nasid_t nasid; 810 - unsigned int widget_id; 811 - u64 baddr; 806 + unsigned long baddr; 807 + unsigned long intr_addr; 808 + struct irq_domain *domain; 812 809 unsigned int pci_int[8]; 810 + nasid_t nasid; 813 811 }; 814 812 815 813 #define BRIDGE_CONTROLLER(bus) \ ··· 819 821 __raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg) 820 822 #define bridge_clr(bc, reg, val) \ 821 823 __raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg) 822 - 823 - extern int request_bridge_irq(struct bridge_controller *bc, int pin); 824 - 825 - extern struct pci_ops bridge_pci_ops; 826 824 827 825 #endif /* _ASM_PCI_BRIDGE_H */

+11

arch/mips/include/asm/sn/irq_alloc.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + #ifndef __ASM_SN_IRQ_ALLOC_H 3 + #define __ASM_SN_IRQ_ALLOC_H 4 + 5 + struct irq_alloc_info { 6 + void *ctrl; 7 + nasid_t nasid; 8 + int pin; 9 + }; 10 + 11 + #endif /* __ASM_SN_IRQ_ALLOC_H */

-9

arch/mips/include/asm/xtalk/xtalk.h

··· 47 47 #define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) 48 48 #define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) 49 49 50 - #ifdef CONFIG_PCI 51 - extern int bridge_probe(nasid_t nasid, int widget, int masterwid); 52 - #else 53 - static inline int bridge_probe(nasid_t nasid, int widget, int masterwid) 54 - { 55 - return 0; 56 - } 57 - #endif 58 - 59 50 #endif /* !__ASSEMBLY__ */ 60 51 61 52 #endif /* _ASM_XTALK_XTALK_H */

+8

arch/mips/kernel/cpu-probe.c

··· 1973 1973 panic("Unknown Ingenic Processor ID!"); 1974 1974 break; 1975 1975 } 1976 + 1977 + /* 1978 + * The config0 register in the Xburst CPUs with a processor ID of 1979 + * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible, 1980 + * but they don't actually support this ISA. 1981 + */ 1982 + if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D0) 1983 + c->isa_level &= ~MIPS_CPU_ISA_M32R2; 1976 1984 } 1977 1985 1978 1986 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)

+3 -18

arch/mips/kernel/perf_event_mipsxx.c

··· 64 64 #define CNTR_EVEN 0x55555555 65 65 #define CNTR_ODD 0xaaaaaaaa 66 66 #define CNTR_ALL 0xffffffff 67 - #ifdef CONFIG_MIPS_MT_SMP 68 67 enum { 69 68 T = 0, 70 69 V = 1, 71 70 P = 2, 72 71 } range; 73 - #else 74 - #define T 75 - #define V 76 - #define P 77 - #endif 78 72 }; 79 73 80 74 static struct mips_perf_event raw_event; ··· 319 325 { 320 326 struct perf_event *event = container_of(evt, struct perf_event, hw); 321 327 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 322 - #ifdef CONFIG_MIPS_MT_SMP 323 328 unsigned int range = evt->event_base >> 24; 324 - #endif /* CONFIG_MIPS_MT_SMP */ 325 329 326 330 WARN_ON(idx < 0 || idx >= mipspmu.num_counters); 327 331 ··· 328 336 /* Make sure interrupt enabled. */ 329 337 MIPS_PERFCTRL_IE; 330 338 331 - #ifdef CONFIG_CPU_BMIPS5000 332 - { 339 + if (IS_ENABLED(CONFIG_CPU_BMIPS5000)) { 333 340 /* enable the counter for the calling thread */ 334 341 cpuc->saved_ctrl[idx] |= 335 342 (1 << (12 + vpe_id())) | BRCM_PERFCTRL_TC; 336 - } 337 - #else 338 - #ifdef CONFIG_MIPS_MT_SMP 339 - if (range > V) { 343 + } else if (IS_ENABLED(CONFIG_MIPS_MT_SMP) && range > V) { 340 344 /* The counter is processor wide. Set it up to count all TCs. */ 341 345 pr_debug("Enabling perf counter for all TCs\n"); 342 346 cpuc->saved_ctrl[idx] |= M_TC_EN_ALL; 343 - } else 344 - #endif /* CONFIG_MIPS_MT_SMP */ 345 - { 347 + } else { 346 348 unsigned int cpu, ctrl; 347 349 348 350 /* ··· 351 365 cpuc->saved_ctrl[idx] |= ctrl; 352 366 pr_debug("Enabling perf counter for CPU%d\n", cpu); 353 367 } 354 - #endif /* CONFIG_CPU_BMIPS5000 */ 355 368 /* 356 369 * We do not actually let the counter run. Leave it until start(). 357 370 */

+2 -1

arch/mips/pci/Makefile

··· 26 26 obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o 27 27 obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o 28 28 obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o 29 + obj-$(CONFIG_PCI_XTALK_BRIDGE) += pci-xtalk-bridge.o 29 30 # 30 31 # These are still pretty much in the old state, watch, go blind. 31 32 # ··· 40 39 obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 41 40 obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 42 41 obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o 43 - obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o 42 + obj-$(CONFIG_SGI_IP27) += pci-ip27.o 44 43 obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o 45 44 obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o 46 45 obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o

-302

arch/mips/pci/ops-bridge.c

··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 1999, 2000, 04, 06 Ralf Baechle (ralf@linux-mips.org) 7 - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 - */ 9 - #include <linux/pci.h> 10 - #include <asm/paccess.h> 11 - #include <asm/pci/bridge.h> 12 - #include <asm/sn/arch.h> 13 - #include <asm/sn/intr.h> 14 - #include <asm/sn/sn0/hub.h> 15 - 16 - /* 17 - * Most of the IOC3 PCI config register aren't present 18 - * we emulate what is needed for a normal PCI enumeration 19 - */ 20 - static u32 emulate_ioc3_cfg(int where, int size) 21 - { 22 - if (size == 1 && where == 0x3d) 23 - return 0x01; 24 - else if (size == 2 && where == 0x3c) 25 - return 0x0100; 26 - else if (size == 4 && where == 0x3c) 27 - return 0x00000100; 28 - 29 - return 0; 30 - } 31 - 32 - /* 33 - * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is 34 - * not really documented, so right now I can't write code which uses it. 35 - * Therefore we use type 0 accesses for now even though they won't work 36 - * correctly for PCI-to-PCI bridges. 37 - * 38 - * The function is complicated by the ultimate brokenness of the IOC3 chip 39 - * which is used in SGI systems. The IOC3 can only handle 32-bit PCI 40 - * accesses and does only decode parts of it's address space. 41 - */ 42 - 43 - static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn, 44 - int where, int size, u32 * value) 45 - { 46 - struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 47 - struct bridge_regs *bridge = bc->base; 48 - int slot = PCI_SLOT(devfn); 49 - int fn = PCI_FUNC(devfn); 50 - volatile void *addr; 51 - u32 cf, shift, mask; 52 - int res; 53 - 54 - addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; 55 - if (get_dbe(cf, (u32 *) addr)) 56 - return PCIBIOS_DEVICE_NOT_FOUND; 57 - 58 - /* 59 - * IOC3 is broken beyond belief ... Don't even give the 60 - * generic PCI code a chance to look at it for real ... 61 - */ 62 - if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) 63 - goto is_ioc3; 64 - 65 - addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; 66 - 67 - if (size == 1) 68 - res = get_dbe(*value, (u8 *) addr); 69 - else if (size == 2) 70 - res = get_dbe(*value, (u16 *) addr); 71 - else 72 - res = get_dbe(*value, (u32 *) addr); 73 - 74 - return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 75 - 76 - is_ioc3: 77 - 78 - /* 79 - * IOC3 special handling 80 - */ 81 - if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { 82 - *value = emulate_ioc3_cfg(where, size); 83 - return PCIBIOS_SUCCESSFUL; 84 - } 85 - 86 - addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 87 - 88 - if (get_dbe(cf, (u32 *) addr)) 89 - return PCIBIOS_DEVICE_NOT_FOUND; 90 - 91 - shift = ((where & 3) << 3); 92 - mask = (0xffffffffU >> ((4 - size) << 3)); 93 - *value = (cf >> shift) & mask; 94 - 95 - return PCIBIOS_SUCCESSFUL; 96 - } 97 - 98 - static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn, 99 - int where, int size, u32 * value) 100 - { 101 - struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 102 - struct bridge_regs *bridge = bc->base; 103 - int busno = bus->number; 104 - int slot = PCI_SLOT(devfn); 105 - int fn = PCI_FUNC(devfn); 106 - volatile void *addr; 107 - u32 cf, shift, mask; 108 - int res; 109 - 110 - bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 111 - addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; 112 - if (get_dbe(cf, (u32 *) addr)) 113 - return PCIBIOS_DEVICE_NOT_FOUND; 114 - 115 - /* 116 - * IOC3 is broken beyond belief ... Don't even give the 117 - * generic PCI code a chance to look at it for real ... 118 - */ 119 - if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) 120 - goto is_ioc3; 121 - 122 - bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 123 - addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; 124 - 125 - if (size == 1) 126 - res = get_dbe(*value, (u8 *) addr); 127 - else if (size == 2) 128 - res = get_dbe(*value, (u16 *) addr); 129 - else 130 - res = get_dbe(*value, (u32 *) addr); 131 - 132 - return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 133 - 134 - is_ioc3: 135 - 136 - /* 137 - * IOC3 special handling 138 - */ 139 - if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { 140 - *value = emulate_ioc3_cfg(where, size); 141 - return PCIBIOS_SUCCESSFUL; 142 - } 143 - 144 - bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 145 - addr = &bridge->b_type1_cfg.c[(fn << 8) | where]; 146 - 147 - if (get_dbe(cf, (u32 *) addr)) 148 - return PCIBIOS_DEVICE_NOT_FOUND; 149 - 150 - shift = ((where & 3) << 3); 151 - mask = (0xffffffffU >> ((4 - size) << 3)); 152 - *value = (cf >> shift) & mask; 153 - 154 - return PCIBIOS_SUCCESSFUL; 155 - } 156 - 157 - static int pci_read_config(struct pci_bus *bus, unsigned int devfn, 158 - int where, int size, u32 * value) 159 - { 160 - if (!pci_is_root_bus(bus)) 161 - return pci_conf1_read_config(bus, devfn, where, size, value); 162 - 163 - return pci_conf0_read_config(bus, devfn, where, size, value); 164 - } 165 - 166 - static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn, 167 - int where, int size, u32 value) 168 - { 169 - struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 170 - struct bridge_regs *bridge = bc->base; 171 - int slot = PCI_SLOT(devfn); 172 - int fn = PCI_FUNC(devfn); 173 - volatile void *addr; 174 - u32 cf, shift, mask, smask; 175 - int res; 176 - 177 - addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; 178 - if (get_dbe(cf, (u32 *) addr)) 179 - return PCIBIOS_DEVICE_NOT_FOUND; 180 - 181 - /* 182 - * IOC3 is broken beyond belief ... Don't even give the 183 - * generic PCI code a chance to look at it for real ... 184 - */ 185 - if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) 186 - goto is_ioc3; 187 - 188 - addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; 189 - 190 - if (size == 1) { 191 - res = put_dbe(value, (u8 *) addr); 192 - } else if (size == 2) { 193 - res = put_dbe(value, (u16 *) addr); 194 - } else { 195 - res = put_dbe(value, (u32 *) addr); 196 - } 197 - 198 - if (res) 199 - return PCIBIOS_DEVICE_NOT_FOUND; 200 - 201 - return PCIBIOS_SUCCESSFUL; 202 - 203 - is_ioc3: 204 - 205 - /* 206 - * IOC3 special handling 207 - */ 208 - if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) 209 - return PCIBIOS_SUCCESSFUL; 210 - 211 - addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 212 - 213 - if (get_dbe(cf, (u32 *) addr)) 214 - return PCIBIOS_DEVICE_NOT_FOUND; 215 - 216 - shift = ((where & 3) << 3); 217 - mask = (0xffffffffU >> ((4 - size) << 3)); 218 - smask = mask << shift; 219 - 220 - cf = (cf & ~smask) | ((value & mask) << shift); 221 - if (put_dbe(cf, (u32 *) addr)) 222 - return PCIBIOS_DEVICE_NOT_FOUND; 223 - 224 - return PCIBIOS_SUCCESSFUL; 225 - } 226 - 227 - static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn, 228 - int where, int size, u32 value) 229 - { 230 - struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 231 - struct bridge_regs *bridge = bc->base; 232 - int slot = PCI_SLOT(devfn); 233 - int fn = PCI_FUNC(devfn); 234 - int busno = bus->number; 235 - volatile void *addr; 236 - u32 cf, shift, mask, smask; 237 - int res; 238 - 239 - bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 240 - addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; 241 - if (get_dbe(cf, (u32 *) addr)) 242 - return PCIBIOS_DEVICE_NOT_FOUND; 243 - 244 - /* 245 - * IOC3 is broken beyond belief ... Don't even give the 246 - * generic PCI code a chance to look at it for real ... 247 - */ 248 - if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) 249 - goto is_ioc3; 250 - 251 - addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; 252 - 253 - if (size == 1) { 254 - res = put_dbe(value, (u8 *) addr); 255 - } else if (size == 2) { 256 - res = put_dbe(value, (u16 *) addr); 257 - } else { 258 - res = put_dbe(value, (u32 *) addr); 259 - } 260 - 261 - if (res) 262 - return PCIBIOS_DEVICE_NOT_FOUND; 263 - 264 - return PCIBIOS_SUCCESSFUL; 265 - 266 - is_ioc3: 267 - 268 - /* 269 - * IOC3 special handling 270 - */ 271 - if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) 272 - return PCIBIOS_SUCCESSFUL; 273 - 274 - addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 275 - 276 - if (get_dbe(cf, (u32 *) addr)) 277 - return PCIBIOS_DEVICE_NOT_FOUND; 278 - 279 - shift = ((where & 3) << 3); 280 - mask = (0xffffffffU >> ((4 - size) << 3)); 281 - smask = mask << shift; 282 - 283 - cf = (cf & ~smask) | ((value & mask) << shift); 284 - if (put_dbe(cf, (u32 *) addr)) 285 - return PCIBIOS_DEVICE_NOT_FOUND; 286 - 287 - return PCIBIOS_SUCCESSFUL; 288 - } 289 - 290 - static int pci_write_config(struct pci_bus *bus, unsigned int devfn, 291 - int where, int size, u32 value) 292 - { 293 - if (!pci_is_root_bus(bus)) 294 - return pci_conf1_write_config(bus, devfn, where, size, value); 295 - 296 - return pci_conf0_write_config(bus, devfn, where, size, value); 297 - } 298 - 299 - struct pci_ops bridge_pci_ops = { 300 - .read = pci_read_config, 301 - .write = pci_write_config, 302 - };

-181

arch/mips/pci/pci-ip27.c

··· 7 7 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) 8 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 9 */ 10 - #include <linux/kernel.h> 11 - #include <linux/export.h> 12 - #include <linux/pci.h> 13 - #include <linux/smp.h> 14 - #include <linux/dma-direct.h> 15 - #include <asm/sn/arch.h> 16 10 #include <asm/pci/bridge.h> 17 - #include <asm/paccess.h> 18 - #include <asm/sn/intr.h> 19 - #include <asm/sn/sn0/hub.h> 20 - 21 - /* 22 - * Max #PCI busses we can handle; ie, max #PCI bridges. 23 - */ 24 - #define MAX_PCI_BUSSES 40 25 - 26 - /* 27 - * XXX: No kmalloc available when we do our crosstalk scan, 28 - * we should try to move it later in the boot process. 29 - */ 30 - static struct bridge_controller bridges[MAX_PCI_BUSSES]; 31 - 32 - extern struct pci_ops bridge_pci_ops; 33 - 34 - int bridge_probe(nasid_t nasid, int widget_id, int masterwid) 35 - { 36 - unsigned long offset = NODE_OFFSET(nasid); 37 - struct bridge_controller *bc; 38 - static int num_bridges = 0; 39 - int slot; 40 - 41 - pci_set_flags(PCI_PROBE_ONLY); 42 - 43 - printk("a bridge\n"); 44 - 45 - /* XXX: kludge alert.. */ 46 - if (!num_bridges) 47 - ioport_resource.end = ~0UL; 48 - 49 - bc = &bridges[num_bridges]; 50 - 51 - bc->pc.pci_ops = &bridge_pci_ops; 52 - bc->pc.mem_resource = &bc->mem; 53 - bc->pc.io_resource = &bc->io; 54 - 55 - bc->pc.index = num_bridges; 56 - 57 - bc->mem.name = "Bridge PCI MEM"; 58 - bc->pc.mem_offset = offset; 59 - bc->mem.start = 0; 60 - bc->mem.end = ~0UL; 61 - bc->mem.flags = IORESOURCE_MEM; 62 - 63 - bc->io.name = "Bridge IO MEM"; 64 - bc->pc.io_offset = offset; 65 - bc->io.start = 0UL; 66 - bc->io.end = ~0UL; 67 - bc->io.flags = IORESOURCE_IO; 68 - 69 - bc->widget_id = widget_id; 70 - bc->nasid = nasid; 71 - 72 - bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR; 73 - 74 - /* 75 - * point to this bridge 76 - */ 77 - bc->base = (struct bridge_regs *)RAW_NODE_SWIN_BASE(nasid, widget_id); 78 - 79 - /* 80 - * Clear all pending interrupts. 81 - */ 82 - bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR); 83 - 84 - /* 85 - * Until otherwise set up, assume all interrupts are from slot 0 86 - */ 87 - bridge_write(bc, b_int_device, 0x0); 88 - 89 - /* 90 - * swap pio's to pci mem and io space (big windows) 91 - */ 92 - bridge_set(bc, b_wid_control, BRIDGE_CTRL_IO_SWAP | 93 - BRIDGE_CTRL_MEM_SWAP); 94 - #ifdef CONFIG_PAGE_SIZE_4KB 95 - bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE); 96 - #else /* 16kB or larger */ 97 - bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE); 98 - #endif 99 - 100 - /* 101 - * Hmm... IRIX sets additional bits in the address which 102 - * are documented as reserved in the bridge docs. 103 - */ 104 - bridge_write(bc, b_wid_int_upper, 0x8000 | (masterwid << 16)); 105 - bridge_write(bc, b_wid_int_lower, 0x01800090); /* PI_INT_PEND_MOD off*/ 106 - bridge_write(bc, b_dir_map, (masterwid << 20)); /* DMA */ 107 - bridge_write(bc, b_int_enable, 0); 108 - 109 - for (slot = 0; slot < 8; slot ++) { 110 - bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR); 111 - bc->pci_int[slot] = -1; 112 - } 113 - bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */ 114 - 115 - register_pci_controller(&bc->pc); 116 - 117 - num_bridges++; 118 - 119 - return 0; 120 - } 121 - 122 - /* 123 - * All observed requests have pin == 1. We could have a global here, that 124 - * gets incremented and returned every time - unfortunately, pci_map_irq 125 - * may be called on the same device over and over, and need to return the 126 - * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7]. 127 - * 128 - * A given PCI device, in general, should be able to intr any of the cpus 129 - * on any one of the hubs connected to its xbow. 130 - */ 131 - int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 132 - { 133 - return 0; 134 - } 135 - 136 - static inline struct pci_dev *bridge_root_dev(struct pci_dev *dev) 137 - { 138 - while (dev->bus->parent) { 139 - /* Move up the chain of bridges. */ 140 - dev = dev->bus->self; 141 - } 142 - 143 - return dev; 144 - } 145 - 146 - /* Do platform specific device initialization at pci_enable_device() time */ 147 - int pcibios_plat_dev_init(struct pci_dev *dev) 148 - { 149 - struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 150 - struct pci_dev *rdev = bridge_root_dev(dev); 151 - int slot = PCI_SLOT(rdev->devfn); 152 - int irq; 153 - 154 - irq = bc->pci_int[slot]; 155 - if (irq == -1) { 156 - irq = request_bridge_irq(bc, slot); 157 - if (irq < 0) 158 - return irq; 159 - 160 - bc->pci_int[slot] = irq; 161 - } 162 - dev->irq = irq; 163 - 164 - return 0; 165 - } 166 11 167 12 dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) 168 13 { ··· 22 177 return dma_addr & ~(0xffUL << 56); 23 178 } 24 179 25 - /* 26 - * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses 27 - * to find the slot number in sense of the bridge device register. 28 - * XXX This also means multiple devices might rely on conflicting bridge 29 - * settings. 30 - */ 31 - 32 - static inline void pci_disable_swapping(struct pci_dev *dev) 33 - { 34 - struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 35 - struct bridge_regs *bridge = bc->base; 36 - int slot = PCI_SLOT(dev->devfn); 37 - 38 - /* Turn off byte swapping */ 39 - bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR; 40 - bridge->b_widget.w_tflush; /* Flush */ 41 - } 42 - 43 - static void pci_fixup_ioc3(struct pci_dev *d) 44 - { 45 - pci_disable_swapping(d); 46 - } 47 - 48 180 #ifdef CONFIG_NUMA 49 181 int pcibus_to_node(struct pci_bus *bus) 50 182 { ··· 31 209 } 32 210 EXPORT_SYMBOL(pcibus_to_node); 33 211 #endif /* CONFIG_NUMA */ 34 - 35 - DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 36 - pci_fixup_ioc3);

+610

arch/mips/pci/pci-xtalk-bridge.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright (C) 2003 Christoph Hellwig (hch@lst.de) 4 + * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) 5 + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 6 + */ 7 + #include <linux/kernel.h> 8 + #include <linux/export.h> 9 + #include <linux/pci.h> 10 + #include <linux/smp.h> 11 + #include <linux/dma-direct.h> 12 + #include <linux/platform_device.h> 13 + #include <linux/platform_data/xtalk-bridge.h> 14 + 15 + #include <asm/pci/bridge.h> 16 + #include <asm/paccess.h> 17 + #include <asm/sn/irq_alloc.h> 18 + 19 + /* 20 + * Most of the IOC3 PCI config register aren't present 21 + * we emulate what is needed for a normal PCI enumeration 22 + */ 23 + static u32 emulate_ioc3_cfg(int where, int size) 24 + { 25 + if (size == 1 && where == 0x3d) 26 + return 0x01; 27 + else if (size == 2 && where == 0x3c) 28 + return 0x0100; 29 + else if (size == 4 && where == 0x3c) 30 + return 0x00000100; 31 + 32 + return 0; 33 + } 34 + 35 + static void bridge_disable_swapping(struct pci_dev *dev) 36 + { 37 + struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 38 + int slot = PCI_SLOT(dev->devfn); 39 + 40 + /* Turn off byte swapping */ 41 + bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR); 42 + bridge_read(bc, b_widget.w_tflush); /* Flush */ 43 + } 44 + 45 + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 46 + bridge_disable_swapping); 47 + 48 + 49 + /* 50 + * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is 51 + * not really documented, so right now I can't write code which uses it. 52 + * Therefore we use type 0 accesses for now even though they won't work 53 + * correctly for PCI-to-PCI bridges. 54 + * 55 + * The function is complicated by the ultimate brokenness of the IOC3 chip 56 + * which is used in SGI systems. The IOC3 can only handle 32-bit PCI 57 + * accesses and does only decode parts of it's address space. 58 + */ 59 + static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn, 60 + int where, int size, u32 *value) 61 + { 62 + struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 63 + struct bridge_regs *bridge = bc->base; 64 + int slot = PCI_SLOT(devfn); 65 + int fn = PCI_FUNC(devfn); 66 + void *addr; 67 + u32 cf, shift, mask; 68 + int res; 69 + 70 + addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; 71 + if (get_dbe(cf, (u32 *)addr)) 72 + return PCIBIOS_DEVICE_NOT_FOUND; 73 + 74 + /* 75 + * IOC3 is broken beyond belief ... Don't even give the 76 + * generic PCI code a chance to look at it for real ... 77 + */ 78 + if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) 79 + goto is_ioc3; 80 + 81 + addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; 82 + 83 + if (size == 1) 84 + res = get_dbe(*value, (u8 *)addr); 85 + else if (size == 2) 86 + res = get_dbe(*value, (u16 *)addr); 87 + else 88 + res = get_dbe(*value, (u32 *)addr); 89 + 90 + return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 91 + 92 + is_ioc3: 93 + 94 + /* 95 + * IOC3 special handling 96 + */ 97 + if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { 98 + *value = emulate_ioc3_cfg(where, size); 99 + return PCIBIOS_SUCCESSFUL; 100 + } 101 + 102 + addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 103 + if (get_dbe(cf, (u32 *)addr)) 104 + return PCIBIOS_DEVICE_NOT_FOUND; 105 + 106 + shift = ((where & 3) << 3); 107 + mask = (0xffffffffU >> ((4 - size) << 3)); 108 + *value = (cf >> shift) & mask; 109 + 110 + return PCIBIOS_SUCCESSFUL; 111 + } 112 + 113 + static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn, 114 + int where, int size, u32 *value) 115 + { 116 + struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 117 + struct bridge_regs *bridge = bc->base; 118 + int busno = bus->number; 119 + int slot = PCI_SLOT(devfn); 120 + int fn = PCI_FUNC(devfn); 121 + void *addr; 122 + u32 cf, shift, mask; 123 + int res; 124 + 125 + bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 126 + addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; 127 + if (get_dbe(cf, (u32 *)addr)) 128 + return PCIBIOS_DEVICE_NOT_FOUND; 129 + 130 + /* 131 + * IOC3 is broken beyond belief ... Don't even give the 132 + * generic PCI code a chance to look at it for real ... 133 + */ 134 + if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) 135 + goto is_ioc3; 136 + 137 + addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; 138 + 139 + if (size == 1) 140 + res = get_dbe(*value, (u8 *)addr); 141 + else if (size == 2) 142 + res = get_dbe(*value, (u16 *)addr); 143 + else 144 + res = get_dbe(*value, (u32 *)addr); 145 + 146 + return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 147 + 148 + is_ioc3: 149 + 150 + /* 151 + * IOC3 special handling 152 + */ 153 + if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { 154 + *value = emulate_ioc3_cfg(where, size); 155 + return PCIBIOS_SUCCESSFUL; 156 + } 157 + 158 + addr = &bridge->b_type1_cfg.c[(fn << 8) | where]; 159 + if (get_dbe(cf, (u32 *)addr)) 160 + return PCIBIOS_DEVICE_NOT_FOUND; 161 + 162 + shift = ((where & 3) << 3); 163 + mask = (0xffffffffU >> ((4 - size) << 3)); 164 + *value = (cf >> shift) & mask; 165 + 166 + return PCIBIOS_SUCCESSFUL; 167 + } 168 + 169 + static int pci_read_config(struct pci_bus *bus, unsigned int devfn, 170 + int where, int size, u32 *value) 171 + { 172 + if (!pci_is_root_bus(bus)) 173 + return pci_conf1_read_config(bus, devfn, where, size, value); 174 + 175 + return pci_conf0_read_config(bus, devfn, where, size, value); 176 + } 177 + 178 + static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn, 179 + int where, int size, u32 value) 180 + { 181 + struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 182 + struct bridge_regs *bridge = bc->base; 183 + int slot = PCI_SLOT(devfn); 184 + int fn = PCI_FUNC(devfn); 185 + void *addr; 186 + u32 cf, shift, mask, smask; 187 + int res; 188 + 189 + addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; 190 + if (get_dbe(cf, (u32 *)addr)) 191 + return PCIBIOS_DEVICE_NOT_FOUND; 192 + 193 + /* 194 + * IOC3 is broken beyond belief ... Don't even give the 195 + * generic PCI code a chance to look at it for real ... 196 + */ 197 + if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) 198 + goto is_ioc3; 199 + 200 + addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; 201 + 202 + if (size == 1) 203 + res = put_dbe(value, (u8 *)addr); 204 + else if (size == 2) 205 + res = put_dbe(value, (u16 *)addr); 206 + else 207 + res = put_dbe(value, (u32 *)addr); 208 + 209 + if (res) 210 + return PCIBIOS_DEVICE_NOT_FOUND; 211 + 212 + return PCIBIOS_SUCCESSFUL; 213 + 214 + is_ioc3: 215 + 216 + /* 217 + * IOC3 special handling 218 + */ 219 + if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) 220 + return PCIBIOS_SUCCESSFUL; 221 + 222 + addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 223 + 224 + if (get_dbe(cf, (u32 *)addr)) 225 + return PCIBIOS_DEVICE_NOT_FOUND; 226 + 227 + shift = ((where & 3) << 3); 228 + mask = (0xffffffffU >> ((4 - size) << 3)); 229 + smask = mask << shift; 230 + 231 + cf = (cf & ~smask) | ((value & mask) << shift); 232 + if (put_dbe(cf, (u32 *)addr)) 233 + return PCIBIOS_DEVICE_NOT_FOUND; 234 + 235 + return PCIBIOS_SUCCESSFUL; 236 + } 237 + 238 + static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn, 239 + int where, int size, u32 value) 240 + { 241 + struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 242 + struct bridge_regs *bridge = bc->base; 243 + int slot = PCI_SLOT(devfn); 244 + int fn = PCI_FUNC(devfn); 245 + int busno = bus->number; 246 + void *addr; 247 + u32 cf, shift, mask, smask; 248 + int res; 249 + 250 + bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 251 + addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; 252 + if (get_dbe(cf, (u32 *)addr)) 253 + return PCIBIOS_DEVICE_NOT_FOUND; 254 + 255 + /* 256 + * IOC3 is broken beyond belief ... Don't even give the 257 + * generic PCI code a chance to look at it for real ... 258 + */ 259 + if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) 260 + goto is_ioc3; 261 + 262 + addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; 263 + 264 + if (size == 1) 265 + res = put_dbe(value, (u8 *)addr); 266 + else if (size == 2) 267 + res = put_dbe(value, (u16 *)addr); 268 + else 269 + res = put_dbe(value, (u32 *)addr); 270 + 271 + if (res) 272 + return PCIBIOS_DEVICE_NOT_FOUND; 273 + 274 + return PCIBIOS_SUCCESSFUL; 275 + 276 + is_ioc3: 277 + 278 + /* 279 + * IOC3 special handling 280 + */ 281 + if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) 282 + return PCIBIOS_SUCCESSFUL; 283 + 284 + addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 285 + if (get_dbe(cf, (u32 *)addr)) 286 + return PCIBIOS_DEVICE_NOT_FOUND; 287 + 288 + shift = ((where & 3) << 3); 289 + mask = (0xffffffffU >> ((4 - size) << 3)); 290 + smask = mask << shift; 291 + 292 + cf = (cf & ~smask) | ((value & mask) << shift); 293 + if (put_dbe(cf, (u32 *)addr)) 294 + return PCIBIOS_DEVICE_NOT_FOUND; 295 + 296 + return PCIBIOS_SUCCESSFUL; 297 + } 298 + 299 + static int pci_write_config(struct pci_bus *bus, unsigned int devfn, 300 + int where, int size, u32 value) 301 + { 302 + if (!pci_is_root_bus(bus)) 303 + return pci_conf1_write_config(bus, devfn, where, size, value); 304 + 305 + return pci_conf0_write_config(bus, devfn, where, size, value); 306 + } 307 + 308 + static struct pci_ops bridge_pci_ops = { 309 + .read = pci_read_config, 310 + .write = pci_write_config, 311 + }; 312 + 313 + struct bridge_irq_chip_data { 314 + struct bridge_controller *bc; 315 + nasid_t nasid; 316 + }; 317 + 318 + static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask, 319 + bool force) 320 + { 321 + #ifdef CONFIG_NUMA 322 + struct bridge_irq_chip_data *data = d->chip_data; 323 + int bit = d->parent_data->hwirq; 324 + int pin = d->hwirq; 325 + nasid_t nasid; 326 + int ret, cpu; 327 + 328 + ret = irq_chip_set_affinity_parent(d, mask, force); 329 + if (ret >= 0) { 330 + cpu = cpumask_first_and(mask, cpu_online_mask); 331 + nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 332 + bridge_write(data->bc, b_int_addr[pin].addr, 333 + (((data->bc->intr_addr >> 30) & 0x30000) | 334 + bit | (nasid << 8))); 335 + bridge_read(data->bc, b_wid_tflush); 336 + } 337 + return ret; 338 + #else 339 + return irq_chip_set_affinity_parent(d, mask, force); 340 + #endif 341 + } 342 + 343 + struct irq_chip bridge_irq_chip = { 344 + .name = "BRIDGE", 345 + .irq_mask = irq_chip_mask_parent, 346 + .irq_unmask = irq_chip_unmask_parent, 347 + .irq_set_affinity = bridge_set_affinity 348 + }; 349 + 350 + static int bridge_domain_alloc(struct irq_domain *domain, unsigned int virq, 351 + unsigned int nr_irqs, void *arg) 352 + { 353 + struct bridge_irq_chip_data *data; 354 + struct irq_alloc_info *info = arg; 355 + int ret; 356 + 357 + if (nr_irqs > 1 || !info) 358 + return -EINVAL; 359 + 360 + data = kzalloc(sizeof(*data), GFP_KERNEL); 361 + if (!data) 362 + return -ENOMEM; 363 + 364 + ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 365 + if (ret >= 0) { 366 + data->bc = info->ctrl; 367 + data->nasid = info->nasid; 368 + irq_domain_set_info(domain, virq, info->pin, &bridge_irq_chip, 369 + data, handle_level_irq, NULL, NULL); 370 + } else { 371 + kfree(data); 372 + } 373 + 374 + return ret; 375 + } 376 + 377 + static void bridge_domain_free(struct irq_domain *domain, unsigned int virq, 378 + unsigned int nr_irqs) 379 + { 380 + struct irq_data *irqd = irq_domain_get_irq_data(domain, virq); 381 + 382 + if (nr_irqs) 383 + return; 384 + 385 + kfree(irqd->chip_data); 386 + irq_domain_free_irqs_top(domain, virq, nr_irqs); 387 + } 388 + 389 + static int bridge_domain_activate(struct irq_domain *domain, 390 + struct irq_data *irqd, bool reserve) 391 + { 392 + struct bridge_irq_chip_data *data = irqd->chip_data; 393 + struct bridge_controller *bc = data->bc; 394 + int bit = irqd->parent_data->hwirq; 395 + int pin = irqd->hwirq; 396 + u32 device; 397 + 398 + bridge_write(bc, b_int_addr[pin].addr, 399 + (((bc->intr_addr >> 30) & 0x30000) | 400 + bit | (data->nasid << 8))); 401 + bridge_set(bc, b_int_enable, (1 << pin)); 402 + bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */ 403 + 404 + /* 405 + * Enable sending of an interrupt clear packt to the hub on a high to 406 + * low transition of the interrupt pin. 407 + * 408 + * IRIX sets additional bits in the address which are documented as 409 + * reserved in the bridge docs. 410 + */ 411 + bridge_set(bc, b_int_mode, (1UL << pin)); 412 + 413 + /* 414 + * We assume the bridge to have a 1:1 mapping between devices 415 + * (slots) and intr pins. 416 + */ 417 + device = bridge_read(bc, b_int_device); 418 + device &= ~(7 << (pin*3)); 419 + device |= (pin << (pin*3)); 420 + bridge_write(bc, b_int_device, device); 421 + 422 + bridge_read(bc, b_wid_tflush); 423 + return 0; 424 + } 425 + 426 + static void bridge_domain_deactivate(struct irq_domain *domain, 427 + struct irq_data *irqd) 428 + { 429 + struct bridge_irq_chip_data *data = irqd->chip_data; 430 + 431 + bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq)); 432 + bridge_read(data->bc, b_wid_tflush); 433 + } 434 + 435 + static const struct irq_domain_ops bridge_domain_ops = { 436 + .alloc = bridge_domain_alloc, 437 + .free = bridge_domain_free, 438 + .activate = bridge_domain_activate, 439 + .deactivate = bridge_domain_deactivate 440 + }; 441 + 442 + /* 443 + * All observed requests have pin == 1. We could have a global here, that 444 + * gets incremented and returned every time - unfortunately, pci_map_irq 445 + * may be called on the same device over and over, and need to return the 446 + * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7]. 447 + * 448 + * A given PCI device, in general, should be able to intr any of the cpus 449 + * on any one of the hubs connected to its xbow. 450 + */ 451 + static int bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 452 + { 453 + struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 454 + struct irq_alloc_info info; 455 + int irq; 456 + 457 + irq = bc->pci_int[slot]; 458 + if (irq == -1) { 459 + info.ctrl = bc; 460 + info.nasid = bc->nasid; 461 + info.pin = slot; 462 + 463 + irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info); 464 + if (irq < 0) 465 + return irq; 466 + 467 + bc->pci_int[slot] = irq; 468 + } 469 + return irq; 470 + } 471 + 472 + static int bridge_probe(struct platform_device *pdev) 473 + { 474 + struct xtalk_bridge_platform_data *bd = dev_get_platdata(&pdev->dev); 475 + struct device *dev = &pdev->dev; 476 + struct bridge_controller *bc; 477 + struct pci_host_bridge *host; 478 + struct irq_domain *domain, *parent; 479 + struct fwnode_handle *fn; 480 + int slot; 481 + int err; 482 + 483 + parent = irq_get_default_host(); 484 + if (!parent) 485 + return -ENODEV; 486 + fn = irq_domain_alloc_named_fwnode("BRIDGE"); 487 + if (!fn) 488 + return -ENOMEM; 489 + domain = irq_domain_create_hierarchy(parent, 0, 8, fn, 490 + &bridge_domain_ops, NULL); 491 + irq_domain_free_fwnode(fn); 492 + if (!domain) 493 + return -ENOMEM; 494 + 495 + pci_set_flags(PCI_PROBE_ONLY); 496 + 497 + host = devm_pci_alloc_host_bridge(dev, sizeof(*bc)); 498 + if (!host) { 499 + err = -ENOMEM; 500 + goto err_remove_domain; 501 + } 502 + 503 + bc = pci_host_bridge_priv(host); 504 + 505 + bc->busn.name = "Bridge PCI busn"; 506 + bc->busn.start = 0; 507 + bc->busn.end = 0xff; 508 + bc->busn.flags = IORESOURCE_BUS; 509 + 510 + bc->domain = domain; 511 + 512 + pci_add_resource_offset(&host->windows, &bd->mem, bd->mem_offset); 513 + pci_add_resource_offset(&host->windows, &bd->io, bd->io_offset); 514 + pci_add_resource(&host->windows, &bc->busn); 515 + 516 + err = devm_request_pci_bus_resources(dev, &host->windows); 517 + if (err < 0) 518 + goto err_free_resource; 519 + 520 + bc->nasid = bd->nasid; 521 + 522 + bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR; 523 + bc->base = (struct bridge_regs *)bd->bridge_addr; 524 + bc->intr_addr = bd->intr_addr; 525 + 526 + /* 527 + * Clear all pending interrupts. 528 + */ 529 + bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR); 530 + 531 + /* 532 + * Until otherwise set up, assume all interrupts are from slot 0 533 + */ 534 + bridge_write(bc, b_int_device, 0x0); 535 + 536 + /* 537 + * disable swapping for big windows 538 + */ 539 + bridge_clr(bc, b_wid_control, 540 + BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP); 541 + #ifdef CONFIG_PAGE_SIZE_4KB 542 + bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE); 543 + #else /* 16kB or larger */ 544 + bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE); 545 + #endif 546 + 547 + /* 548 + * Hmm... IRIX sets additional bits in the address which 549 + * are documented as reserved in the bridge docs. 550 + */ 551 + bridge_write(bc, b_wid_int_upper, 552 + ((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16)); 553 + bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff); 554 + bridge_write(bc, b_dir_map, (bd->masterwid << 20)); /* DMA */ 555 + bridge_write(bc, b_int_enable, 0); 556 + 557 + for (slot = 0; slot < 8; slot++) { 558 + bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR); 559 + bc->pci_int[slot] = -1; 560 + } 561 + bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */ 562 + 563 + host->dev.parent = dev; 564 + host->sysdata = bc; 565 + host->busnr = 0; 566 + host->ops = &bridge_pci_ops; 567 + host->map_irq = bridge_map_irq; 568 + host->swizzle_irq = pci_common_swizzle; 569 + 570 + err = pci_scan_root_bus_bridge(host); 571 + if (err < 0) 572 + goto err_free_resource; 573 + 574 + pci_bus_claim_resources(host->bus); 575 + pci_bus_add_devices(host->bus); 576 + 577 + platform_set_drvdata(pdev, host->bus); 578 + 579 + return 0; 580 + 581 + err_free_resource: 582 + pci_free_resource_list(&host->windows); 583 + err_remove_domain: 584 + irq_domain_remove(domain); 585 + return err; 586 + } 587 + 588 + static int bridge_remove(struct platform_device *pdev) 589 + { 590 + struct pci_bus *bus = platform_get_drvdata(pdev); 591 + struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 592 + 593 + irq_domain_remove(bc->domain); 594 + pci_lock_rescan_remove(); 595 + pci_stop_root_bus(bus); 596 + pci_remove_root_bus(bus); 597 + pci_unlock_rescan_remove(); 598 + 599 + return 0; 600 + } 601 + 602 + static struct platform_driver bridge_driver = { 603 + .probe = bridge_probe, 604 + .remove = bridge_remove, 605 + .driver = { 606 + .name = "xtalk-bridge", 607 + } 608 + }; 609 + 610 + builtin_platform_driver(bridge_driver);

+13

arch/mips/sgi-ip22/ip22-platform.c

··· 3 3 #include <linux/if_ether.h> 4 4 #include <linux/kernel.h> 5 5 #include <linux/platform_device.h> 6 + #include <linux/dma-mapping.h> 6 7 7 8 #include <asm/paccess.h> 8 9 #include <asm/sgi/ip22.h> ··· 26 25 .irq = SGI_WD93_0_IRQ, 27 26 }; 28 27 28 + static u64 sgiwd93_0_dma_mask = DMA_BIT_MASK(32); 29 + 29 30 static struct platform_device sgiwd93_0_device = { 30 31 .name = "sgiwd93", 31 32 .id = 0, ··· 35 32 .resource = sgiwd93_0_resources, 36 33 .dev = { 37 34 .platform_data = &sgiwd93_0_pd, 35 + .dma_mask = &sgiwd93_0_dma_mask, 36 + .coherent_dma_mask = DMA_BIT_MASK(32), 38 37 }, 39 38 }; 40 39 ··· 54 49 .irq = SGI_WD93_1_IRQ, 55 50 }; 56 51 52 + static u64 sgiwd93_1_dma_mask = DMA_BIT_MASK(32); 53 + 57 54 static struct platform_device sgiwd93_1_device = { 58 55 .name = "sgiwd93", 59 56 .id = 1, ··· 63 56 .resource = sgiwd93_1_resources, 64 57 .dev = { 65 58 .platform_data = &sgiwd93_1_pd, 59 + .dma_mask = &sgiwd93_1_dma_mask, 60 + .coherent_dma_mask = DMA_BIT_MASK(32), 66 61 }, 67 62 }; 68 63 ··· 105 96 106 97 static struct sgiseeq_platform_data eth0_pd; 107 98 99 + static u64 sgiseeq_dma_mask = DMA_BIT_MASK(32); 100 + 108 101 static struct platform_device eth0_device = { 109 102 .name = "sgiseeq", 110 103 .id = 0, ··· 114 103 .resource = sgiseeq_0_resources, 115 104 .dev = { 116 105 .platform_data = &eth0_pd, 106 + .dma_mask = &sgiseeq_dma_mask, 107 + .coherent_dma_mask = DMA_BIT_MASK(32), 117 108 }, 118 109 }; 119 110

+2

arch/mips/sgi-ip27/ip27-init.c

··· 184 184 185 185 ioc3_eth_init(); 186 186 187 + ioport_resource.start = 0; 188 + ioport_resource.end = ~0UL; 187 189 set_io_port_base(IO_BASE); 188 190 }

+84 -106

arch/mips/sgi-ip27/ip27-irq.c

··· 12 12 #include <linux/ioport.h> 13 13 #include <linux/kernel.h> 14 14 #include <linux/bitops.h> 15 + #include <linux/sched.h> 15 16 16 17 #include <asm/io.h> 17 18 #include <asm/irq_cpu.h> 18 - #include <asm/pci/bridge.h> 19 19 #include <asm/sn/addrs.h> 20 20 #include <asm/sn/agent.h> 21 21 #include <asm/sn/arch.h> 22 22 #include <asm/sn/hub.h> 23 23 #include <asm/sn/intr.h> 24 + #include <asm/sn/irq_alloc.h> 24 25 25 26 struct hub_irq_data { 26 - struct bridge_controller *bc; 27 27 u64 *irq_mask[2]; 28 28 cpuid_t cpu; 29 - int bit; 30 - int pin; 31 29 }; 32 30 33 31 static DECLARE_BITMAP(hub_irq_map, IP27_HUB_IRQ_COUNT); ··· 52 54 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 53 55 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); 54 56 55 - set_bit(hd->bit, mask); 57 + set_bit(d->hwirq, mask); 56 58 __raw_writeq(mask[0], hd->irq_mask[0]); 57 59 __raw_writeq(mask[1], hd->irq_mask[1]); 58 60 } ··· 62 64 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 63 65 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); 64 66 65 - clear_bit(hd->bit, mask); 67 + clear_bit(d->hwirq, mask); 66 68 __raw_writeq(mask[0], hd->irq_mask[0]); 67 69 __raw_writeq(mask[1], hd->irq_mask[1]); 68 - } 69 - 70 - static unsigned int startup_bridge_irq(struct irq_data *d) 71 - { 72 - struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 73 - struct bridge_controller *bc; 74 - nasid_t nasid; 75 - u32 device; 76 - int pin; 77 - 78 - if (!hd) 79 - return -EINVAL; 80 - 81 - pin = hd->pin; 82 - bc = hd->bc; 83 - 84 - nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(hd->cpu)); 85 - bridge_write(bc, b_int_addr[pin].addr, 86 - (0x20000 | hd->bit | (nasid << 8))); 87 - bridge_set(bc, b_int_enable, (1 << pin)); 88 - bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */ 89 - 90 - /* 91 - * Enable sending of an interrupt clear packt to the hub on a high to 92 - * low transition of the interrupt pin. 93 - * 94 - * IRIX sets additional bits in the address which are documented as 95 - * reserved in the bridge docs. 96 - */ 97 - bridge_set(bc, b_int_mode, (1UL << pin)); 98 - 99 - /* 100 - * We assume the bridge to have a 1:1 mapping between devices 101 - * (slots) and intr pins. 102 - */ 103 - device = bridge_read(bc, b_int_device); 104 - device &= ~(7 << (pin*3)); 105 - device |= (pin << (pin*3)); 106 - bridge_write(bc, b_int_device, device); 107 - 108 - bridge_read(bc, b_wid_tflush); 109 - 110 - enable_hub_irq(d); 111 - 112 - return 0; /* Never anything pending. */ 113 - } 114 - 115 - static void shutdown_bridge_irq(struct irq_data *d) 116 - { 117 - struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 118 - struct bridge_controller *bc; 119 - 120 - if (!hd) 121 - return; 122 - 123 - disable_hub_irq(d); 124 - 125 - bc = hd->bc; 126 - bridge_clr(bc, b_int_enable, (1 << hd->pin)); 127 - bridge_read(bc, b_wid_tflush); 128 70 } 129 71 130 72 static void setup_hub_mask(struct hub_irq_data *hd, const struct cpumask *mask) ··· 82 144 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_B); 83 145 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_B); 84 146 } 85 - 86 - /* Make sure it's not already pending when we connect it. */ 87 - REMOTE_HUB_CLR_INTR(nasid, hd->bit); 88 147 } 89 148 90 149 static int set_affinity_hub_irq(struct irq_data *d, const struct cpumask *mask, ··· 98 163 setup_hub_mask(hd, mask); 99 164 100 165 if (irqd_is_started(d)) 101 - startup_bridge_irq(d); 166 + enable_hub_irq(d); 102 167 103 168 irq_data_update_effective_affinity(d, cpumask_of(hd->cpu)); 104 169 ··· 107 172 108 173 static struct irq_chip hub_irq_type = { 109 174 .name = "HUB", 110 - .irq_startup = startup_bridge_irq, 111 - .irq_shutdown = shutdown_bridge_irq, 112 175 .irq_mask = disable_hub_irq, 113 176 .irq_unmask = enable_hub_irq, 114 177 .irq_set_affinity = set_affinity_hub_irq, 115 178 }; 116 179 117 - int request_bridge_irq(struct bridge_controller *bc, int pin) 180 + static int hub_domain_alloc(struct irq_domain *domain, unsigned int virq, 181 + unsigned int nr_irqs, void *arg) 118 182 { 183 + struct irq_alloc_info *info = arg; 119 184 struct hub_irq_data *hd; 120 185 struct hub_data *hub; 121 186 struct irq_desc *desc; 122 187 int swlevel; 123 - int irq; 188 + 189 + if (nr_irqs > 1 || !info) 190 + return -EINVAL; 124 191 125 192 hd = kzalloc(sizeof(*hd), GFP_KERNEL); 126 193 if (!hd) ··· 133 196 kfree(hd); 134 197 return -EAGAIN; 135 198 } 136 - irq = swlevel + IP27_HUB_IRQ_BASE; 137 - 138 - hd->bc = bc; 139 - hd->bit = swlevel; 140 - hd->pin = pin; 141 - irq_set_chip_data(irq, hd); 199 + irq_domain_set_info(domain, virq, swlevel, &hub_irq_type, hd, 200 + handle_level_irq, NULL, NULL); 142 201 143 202 /* use CPU connected to nearest hub */ 144 - hub = hub_data(NASID_TO_COMPACT_NODEID(bc->nasid)); 203 + hub = hub_data(NASID_TO_COMPACT_NODEID(info->nasid)); 145 204 setup_hub_mask(hd, &hub->h_cpus); 146 205 147 - desc = irq_to_desc(irq); 148 - desc->irq_common_data.node = bc->nasid; 206 + /* Make sure it's not already pending when we connect it. */ 207 + REMOTE_HUB_CLR_INTR(info->nasid, swlevel); 208 + 209 + desc = irq_to_desc(virq); 210 + desc->irq_common_data.node = info->nasid; 149 211 cpumask_copy(desc->irq_common_data.affinity, &hub->h_cpus); 150 212 151 - return irq; 213 + return 0; 152 214 } 153 215 154 - void ip27_hub_irq_init(void) 216 + static void hub_domain_free(struct irq_domain *domain, 217 + unsigned int virq, unsigned int nr_irqs) 155 218 { 156 - int i; 219 + struct irq_data *irqd; 157 220 158 - for (i = IP27_HUB_IRQ_BASE; 159 - i < (IP27_HUB_IRQ_BASE + IP27_HUB_IRQ_COUNT); i++) 160 - irq_set_chip_and_handler(i, &hub_irq_type, handle_level_irq); 221 + if (nr_irqs > 1) 222 + return; 161 223 162 - /* 163 - * Some interrupts are reserved by hardware or by software convention. 164 - * Mark these as reserved right away so they won't be used accidentally 165 - * later. 166 - */ 167 - for (i = 0; i <= BASE_PCI_IRQ; i++) 168 - set_bit(i, hub_irq_map); 169 - 170 - set_bit(IP_PEND0_6_63, hub_irq_map); 171 - 172 - for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) 173 - set_bit(i, hub_irq_map); 224 + irqd = irq_domain_get_irq_data(domain, virq); 225 + if (irqd && irqd->chip_data) 226 + kfree(irqd->chip_data); 174 227 } 228 + 229 + static const struct irq_domain_ops hub_domain_ops = { 230 + .alloc = hub_domain_alloc, 231 + .free = hub_domain_free, 232 + }; 175 233 176 234 /* 177 235 * This code is unnecessarily complex, because we do ··· 184 252 { 185 253 cpuid_t cpu = smp_processor_id(); 186 254 unsigned long *mask = per_cpu(irq_enable_mask, cpu); 255 + struct irq_domain *domain; 187 256 u64 pend0; 257 + int irq; 188 258 189 259 /* copied from Irix intpend0() */ 190 260 pend0 = LOCAL_HUB_L(PI_INT_PEND0); ··· 210 276 generic_smp_call_function_interrupt(); 211 277 } else 212 278 #endif 213 - generic_handle_irq(__ffs(pend0) + IP27_HUB_IRQ_BASE); 279 + { 280 + domain = irq_desc_get_handler_data(desc); 281 + irq = irq_linear_revmap(domain, __ffs(pend0)); 282 + if (irq) 283 + generic_handle_irq(irq); 284 + else 285 + spurious_interrupt(); 286 + } 214 287 215 288 LOCAL_HUB_L(PI_INT_PEND0); 216 289 } ··· 226 285 { 227 286 cpuid_t cpu = smp_processor_id(); 228 287 unsigned long *mask = per_cpu(irq_enable_mask, cpu); 288 + struct irq_domain *domain; 229 289 u64 pend1; 290 + int irq; 230 291 231 292 /* copied from Irix intpend0() */ 232 293 pend1 = LOCAL_HUB_L(PI_INT_PEND1); ··· 237 294 if (!pend1) 238 295 return; 239 296 240 - generic_handle_irq(__ffs(pend1) + IP27_HUB_IRQ_BASE + 64); 297 + domain = irq_desc_get_handler_data(desc); 298 + irq = irq_linear_revmap(domain, __ffs(pend1) + 64); 299 + if (irq) 300 + generic_handle_irq(irq); 301 + else 302 + spurious_interrupt(); 241 303 242 304 LOCAL_HUB_L(PI_INT_PEND1); 243 305 } ··· 273 325 274 326 void __init arch_init_irq(void) 275 327 { 328 + struct irq_domain *domain; 329 + struct fwnode_handle *fn; 330 + int i; 331 + 276 332 mips_cpu_irq_init(); 277 - ip27_hub_irq_init(); 333 + 334 + /* 335 + * Some interrupts are reserved by hardware or by software convention. 336 + * Mark these as reserved right away so they won't be used accidentally 337 + * later. 338 + */ 339 + for (i = 0; i <= BASE_PCI_IRQ; i++) 340 + set_bit(i, hub_irq_map); 341 + 342 + set_bit(IP_PEND0_6_63, hub_irq_map); 343 + 344 + for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) 345 + set_bit(i, hub_irq_map); 346 + 347 + fn = irq_domain_alloc_named_fwnode("HUB"); 348 + WARN_ON(fn == NULL); 349 + if (!fn) 350 + return; 351 + domain = irq_domain_create_linear(fn, IP27_HUB_IRQ_COUNT, 352 + &hub_domain_ops, NULL); 353 + WARN_ON(domain == NULL); 354 + if (!domain) 355 + return; 356 + 357 + irq_set_default_host(domain); 278 358 279 359 irq_set_percpu_devid(IP27_HUB_PEND0_IRQ); 280 - irq_set_chained_handler(IP27_HUB_PEND0_IRQ, ip27_do_irq_mask0); 360 + irq_set_chained_handler_and_data(IP27_HUB_PEND0_IRQ, ip27_do_irq_mask0, 361 + domain); 281 362 irq_set_percpu_devid(IP27_HUB_PEND1_IRQ); 282 - irq_set_chained_handler(IP27_HUB_PEND1_IRQ, ip27_do_irq_mask1); 363 + irq_set_chained_handler_and_data(IP27_HUB_PEND1_IRQ, ip27_do_irq_mask1, 364 + domain); 283 365 }

+49 -12

arch/mips/sgi-ip27/ip27-xtalk.c

··· 9 9 10 10 #include <linux/kernel.h> 11 11 #include <linux/smp.h> 12 + #include <linux/platform_device.h> 13 + #include <linux/platform_data/xtalk-bridge.h> 14 + #include <asm/sn/addrs.h> 12 15 #include <asm/sn/types.h> 13 16 #include <asm/sn/klconfig.h> 14 17 #include <asm/sn/hub.h> ··· 23 20 #define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbow in Xbridge */ 24 21 #define BASE_XBOW_PORT 8 /* Lowest external port */ 25 22 26 - extern int bridge_probe(nasid_t nasid, int widget, int masterwid); 23 + static void bridge_platform_create(nasid_t nasid, int widget, int masterwid) 24 + { 25 + struct xtalk_bridge_platform_data *bd; 26 + struct platform_device *pdev; 27 + unsigned long offset; 28 + 29 + bd = kzalloc(sizeof(*bd), GFP_KERNEL); 30 + if (!bd) 31 + goto no_mem; 32 + pdev = platform_device_alloc("xtalk-bridge", PLATFORM_DEVID_AUTO); 33 + if (!pdev) { 34 + kfree(bd); 35 + goto no_mem; 36 + } 37 + 38 + offset = NODE_OFFSET(nasid); 39 + 40 + bd->bridge_addr = RAW_NODE_SWIN_BASE(nasid, widget); 41 + bd->intr_addr = BIT_ULL(47) + 0x01800000 + PI_INT_PEND_MOD; 42 + bd->nasid = nasid; 43 + bd->masterwid = masterwid; 44 + 45 + bd->mem.name = "Bridge PCI MEM"; 46 + bd->mem.start = offset + (widget << SWIN_SIZE_BITS); 47 + bd->mem.end = bd->mem.start + SWIN_SIZE - 1; 48 + bd->mem.flags = IORESOURCE_MEM; 49 + bd->mem_offset = offset; 50 + 51 + bd->io.name = "Bridge PCI IO"; 52 + bd->io.start = offset + (widget << SWIN_SIZE_BITS); 53 + bd->io.end = bd->io.start + SWIN_SIZE - 1; 54 + bd->io.flags = IORESOURCE_IO; 55 + bd->io_offset = offset; 56 + 57 + platform_device_add_data(pdev, bd, sizeof(*bd)); 58 + platform_device_add(pdev); 59 + pr_info("xtalk:n%d/%x bridge widget\n", nasid, widget); 60 + return; 61 + 62 + no_mem: 63 + pr_warn("xtalk:n%d/%x bridge create out of memory\n", nasid, widget); 64 + } 27 65 28 66 static int probe_one_port(nasid_t nasid, int widget, int masterwid) 29 67 { ··· 75 31 (RAW_NODE_SWIN_BASE(nasid, widget) + WIDGET_ID); 76 32 partnum = XWIDGET_PART_NUM(widget_id); 77 33 78 - printk(KERN_INFO "Cpu %d, Nasid 0x%x, widget 0x%x (partnum 0x%x) is ", 79 - smp_processor_id(), nasid, widget, partnum); 80 - 81 34 switch (partnum) { 82 35 case BRIDGE_WIDGET_PART_NUM: 83 36 case XBRIDGE_WIDGET_PART_NUM: 84 - bridge_probe(nasid, widget, masterwid); 37 + bridge_platform_create(nasid, widget, masterwid); 85 38 break; 86 39 default: 87 40 break; ··· 92 51 lboard_t *brd; 93 52 klxbow_t *xbow_p; 94 53 unsigned masterwid, i; 95 - 96 - printk("is xbow\n"); 97 54 98 55 /* 99 56 * found xbow, so may have multiple bridges ··· 156 117 (RAW_NODE_SWIN_BASE(nasid, 0x0) + WIDGET_ID); 157 118 partnum = XWIDGET_PART_NUM(widget_id); 158 119 159 - printk(KERN_INFO "Cpu %d, Nasid 0x%x: partnum 0x%x is ", 160 - smp_processor_id(), nasid, partnum); 161 - 162 120 switch (partnum) { 163 121 case BRIDGE_WIDGET_PART_NUM: 164 - bridge_probe(nasid, 0x8, 0xa); 122 + bridge_platform_create(nasid, 0x8, 0xa); 165 123 break; 166 124 case XBOW_WIDGET_PART_NUM: 167 125 case XXBOW_WIDGET_PART_NUM: 126 + pr_info("xtalk:n%d/0 xbow widget\n", nasid); 168 127 xbow_probe(nasid); 169 128 break; 170 129 default: 171 - printk(" unknown widget??\n"); 130 + pr_info("xtalk:n%d/0 unknown widget (0x%x)\n", nasid, partnum); 172 131 break; 173 132 } 174 133 }

+22

include/linux/platform_data/xtalk-bridge.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * SGI PCI Xtalk Bridge 4 + */ 5 + 6 + #ifndef PLATFORM_DATA_XTALK_BRIDGE_H 7 + #define PLATFORM_DATA_XTALK_BRIDGE_H 8 + 9 + #include <asm/sn/types.h> 10 + 11 + struct xtalk_bridge_platform_data { 12 + struct resource mem; 13 + struct resource io; 14 + unsigned long bridge_addr; 15 + unsigned long intr_addr; 16 + unsigned long mem_offset; 17 + unsigned long io_offset; 18 + nasid_t nasid; 19 + int masterwid; 20 + }; 21 + 22 + #endif /* PLATFORM_DATA_XTALK_BRIDGE_H */