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Merge tag 'zynq-dt-fixes-for-3.18' of https://github.com/Xilinx/linux-xlnx into fixes
Merge "Xilinx Zynq dt fixes for v3.18" from Michal Simek:
arm: Xilinx Zynq DT fixes for v3.18
- Fix gem register size
- Fix OPP
- Add missing references
- Trivial cleanup
* tag 'zynq-dt-fixes-for-3.18' of https://github.com/Xilinx/linux-xlnx:
ARM: zynq: DT: trivial: Fix mc node
ARM: zynq: DT: Add cadence watchdog node
ARM: zynq: DT: Add missing reference for memory-controller
ARM: zynq: DT: Add missing reference for ADC
ARM: zynq: DT: Add missing address for L2 pl310
ARM: zynq: DT: Remove 222 MHz OPP
ARM: zynq: DT: Fix GEM register area size
Signed-off-by: Olof Johansson <olof@lixom.net>
+17
-7
arch/arm/boot/dts/zynq-7000.dtsi
+17
-7
arch/arm/boot/dts/zynq-7000.dtsi
···
30
/* kHz uV */
31
666667 1000000
32
333334 1000000
33
-
222223 1000000
34
>;
35
};
36
···
64
interrupt-parent = <&intc>;
65
ranges;
66
67
-
adc@f8007100 {
68
compatible = "xlnx,zynq-xadc-1.00.a";
69
reg = <0xf8007100 0x20>;
70
interrupts = <0 7 4>;
···
136
<0xF8F00100 0x100>;
137
};
138
139
-
L2: cache-controller {
140
compatible = "arm,pl310-cache";
141
reg = <0xF8F02000 0x1000>;
142
arm,data-latency = <3 2 2>;
···
145
cache-level = <2>;
146
};
147
148
-
memory-controller@f8006000 {
149
compatible = "xlnx,zynq-ddrc-a05";
150
reg = <0xf8006000 0x1000>;
151
-
} ;
152
153
uart0: serial@e0000000 {
154
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
···
194
195
gem0: ethernet@e000b000 {
196
compatible = "cdns,gem";
197
-
reg = <0xe000b000 0x4000>;
198
status = "disabled";
199
interrupts = <0 22 4>;
200
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
···
205
206
gem1: ethernet@e000c000 {
207
compatible = "cdns,gem";
208
-
reg = <0xe000c000 0x4000>;
209
status = "disabled";
210
interrupts = <0 45 4>;
211
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
···
313
compatible = "arm,cortex-a9-twd-timer";
314
reg = <0xf8f00600 0x20>;
315
clocks = <&clkc 4>;
316
};
317
};
318
};
···
30
/* kHz uV */
31
666667 1000000
32
333334 1000000
33
>;
34
};
35
···
65
interrupt-parent = <&intc>;
66
ranges;
67
68
+
adc: adc@f8007100 {
69
compatible = "xlnx,zynq-xadc-1.00.a";
70
reg = <0xf8007100 0x20>;
71
interrupts = <0 7 4>;
···
137
<0xF8F00100 0x100>;
138
};
139
140
+
L2: cache-controller@f8f02000 {
141
compatible = "arm,pl310-cache";
142
reg = <0xF8F02000 0x1000>;
143
arm,data-latency = <3 2 2>;
···
146
cache-level = <2>;
147
};
148
149
+
mc: memory-controller@f8006000 {
150
compatible = "xlnx,zynq-ddrc-a05";
151
reg = <0xf8006000 0x1000>;
152
+
};
153
154
uart0: serial@e0000000 {
155
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
···
195
196
gem0: ethernet@e000b000 {
197
compatible = "cdns,gem";
198
+
reg = <0xe000b000 0x1000>;
199
status = "disabled";
200
interrupts = <0 22 4>;
201
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
···
206
207
gem1: ethernet@e000c000 {
208
compatible = "cdns,gem";
209
+
reg = <0xe000c000 0x1000>;
210
status = "disabled";
211
interrupts = <0 45 4>;
212
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
···
314
compatible = "arm,cortex-a9-twd-timer";
315
reg = <0xf8f00600 0x20>;
316
clocks = <&clkc 4>;
317
+
};
318
+
319
+
watchdog0: watchdog@f8005000 {
320
+
clocks = <&clkc 45>;
321
+
compatible = "xlnx,zynq-wdt-r1p2";
322
+
device_type = "watchdog";
323
+
interrupt-parent = <&intc>;
324
+
interrupts = <0 9 1>;
325
+
reg = <0xf8005000 0x1000>;
326
+
reset = <0>;
327
+
timeout-sec = <10>;
328
};
329
};
330
};