tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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[media] drxd: don't re-define u8/u16/u32 types

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

Mauro Carvalho Chehab bccd2d8a 935c630c

+66 -69
+35 -35
drivers/media/dvb/frontends/drxd_firm.c
··· 46 46 #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A 47 47 #define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */ 48 48 49 - u8_t DRXD_InitAtomicRead[] = { 49 + u8 DRXD_InitAtomicRead[] = { 50 50 WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE), 51 51 0x26, 0x00, /* 0 -> ring.rdy; */ 52 52 0x60, 0x04, /* r0rami.dt -> ring.xba; */ ··· 67 67 #define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */ 68 68 69 69 /* D0 Version */ 70 - u8_t DRXD_HiI2cPatch_1[] = { 70 + u8 DRXD_HiI2cPatch_1[] = { 71 71 WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE), 72 72 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */ 73 73 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ ··· 114 114 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ 115 115 116 116 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)), 117 - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), 117 + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 118 118 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)), 119 - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), 119 + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 120 120 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)), 121 - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), 121 + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 122 122 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)), 123 - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), 123 + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 124 124 125 125 /* Force quick and dirty reset */ 126 126 WR16(B_HI_CT_REG_COMM_STATE__A, 0), ··· 128 128 }; 129 129 130 130 /* D0,D1 Version */ 131 - u8_t DRXD_HiI2cPatch_3[] = { 131 + u8 DRXD_HiI2cPatch_3[] = { 132 132 WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE), 133 133 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */ 134 134 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ ··· 175 175 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ 176 176 177 177 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)), 178 - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), 178 + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 179 179 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)), 180 - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), 180 + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 181 181 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)), 182 - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), 182 + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 183 183 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)), 184 - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), 184 + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 185 185 186 186 /* Force quick and dirty reset */ 187 187 WR16(B_HI_CT_REG_COMM_STATE__A, 0), 188 188 END_OF_TABLE 189 189 }; 190 190 191 - u8_t DRXD_ResetCEFR[] = { 191 + u8 DRXD_ResetCEFR[] = { 192 192 WRBLOCK(CE_REG_FR_TREAL00__A, 57), 193 193 0x52, 0x00, /* CE_REG_FR_TREAL00__A */ 194 194 0x00, 0x00, /* CE_REG_FR_TIMAG00__A */ ··· 255 255 END_OF_TABLE 256 256 }; 257 257 258 - u8_t DRXD_InitFEA2_1[] = { 258 + u8 DRXD_InitFEA2_1[] = { 259 259 WRBLOCK(FE_AD_REG_PD__A, 3), 260 260 0x00, 0x00, /* FE_AD_REG_PD__A */ 261 261 0x01, 0x00, /* FE_AD_REG_INVEXT__A */ ··· 341 341 /* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/ 342 342 /* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ 343 343 344 - u8_t DRXD_InitFEA2_2[] = { 344 + u8 DRXD_InitFEA2_2[] = { 345 345 WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010), 346 346 WR16(FE_AG_REG_FGM_WRI__A, 48), 347 347 /* Activate measurement, activate scale */ ··· 359 359 END_OF_TABLE 360 360 }; 361 361 362 - u8_t DRXD_InitFEB1_1[] = { 362 + u8 DRXD_InitFEB1_1[] = { 363 363 WR16(B_FE_AD_REG_PD__A, 0x0000), 364 364 WR16(B_FE_AD_REG_CLKNEG__A, 0x0000), 365 365 WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000), ··· 382 382 /* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */ 383 383 /* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ 384 384 385 - u8_t DRXD_InitFEB1_2[] = { 385 + u8 DRXD_InitFEB1_2[] = { 386 386 WR16(B_FE_COMM_EXEC__A, 0x0001), 387 387 388 388 /* RF-AGC setup */ ··· 404 404 END_OF_TABLE 405 405 }; 406 406 407 - u8_t DRXD_InitCPA2[] = { 407 + u8 DRXD_InitCPA2[] = { 408 408 WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2), 409 409 0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */ 410 410 0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */ ··· 434 434 END_OF_TABLE 435 435 }; 436 436 437 - u8_t DRXD_InitCPB1[] = { 437 + u8 DRXD_InitCPB1[] = { 438 438 WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008), 439 439 WR16(B_CP_COMM_EXEC__A, 0x0001), 440 440 END_OF_TABLE 441 441 }; 442 442 443 - u8_t DRXD_InitCEA2[] = { 443 + u8 DRXD_InitCEA2[] = { 444 444 WRBLOCK(CE_REG_AVG_POW__A, 4), 445 445 0x62, 0x00, /* CE_REG_AVG_POW__A */ 446 446 0x78, 0x00, /* CE_REG_MAX_POW__A */ ··· 483 483 END_OF_TABLE 484 484 }; 485 485 486 - u8_t DRXD_InitCEB1[] = { 486 + u8 DRXD_InitCEB1[] = { 487 487 WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001), 488 488 WR16(B_CE_REG_FR_PM_SET__A, 0x000D), 489 489 490 490 END_OF_TABLE 491 491 }; 492 492 493 - u8_t DRXD_InitEQA2[] = { 493 + u8 DRXD_InitEQA2[] = { 494 494 WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4), 495 495 0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */ 496 496 0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */ ··· 499 499 500 500 WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200), 501 501 WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F), 502 - WR16(EQ_REG_SN_OFFSET__A, (u16_t) (-7)), 502 + WR16(EQ_REG_SN_OFFSET__A, (u16) (-7)), 503 503 WR16(EQ_REG_RC_SEL_CAR__A, 0x0002), 504 504 WR16(EQ_REG_COMM_EXEC__A, 0x0001), 505 505 END_OF_TABLE 506 506 }; 507 507 508 - u8_t DRXD_InitEQB1[] = { 508 + u8 DRXD_InitEQB1[] = { 509 509 WR16(B_EQ_REG_COMM_EXEC__A, 0x0001), 510 510 END_OF_TABLE 511 511 }; 512 512 513 - u8_t DRXD_ResetECRAM[] = { 513 + u8 DRXD_ResetECRAM[] = { 514 514 /* Reset packet sync bytes in EC_VD ram */ 515 515 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000), 516 516 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000), ··· 530 530 END_OF_TABLE 531 531 }; 532 532 533 - u8_t DRXD_InitECA2[] = { 533 + u8 DRXD_InitECA2[] = { 534 534 WRBLOCK(EC_SB_REG_CSI_HI__A, 6), 535 535 0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */ 536 536 0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */ ··· 616 616 END_OF_TABLE 617 617 }; 618 618 619 - u8_t DRXD_InitECB1[] = { 619 + u8 DRXD_InitECB1[] = { 620 620 WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001), 621 621 WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001), 622 622 WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001), ··· 671 671 END_OF_TABLE 672 672 }; 673 673 674 - u8_t DRXD_ResetECA2[] = { 674 + u8 DRXD_ResetECA2[] = { 675 675 676 676 WR16(EC_OC_REG_COMM_EXEC__A, 0x0000), 677 677 WR16(EC_OD_REG_COMM_EXEC__A, 0x0000), ··· 742 742 END_OF_TABLE 743 743 }; 744 744 745 - u8_t DRXD_InitSC[] = { 745 + u8 DRXD_InitSC[] = { 746 746 WR16(SC_COMM_EXEC__A, 0), 747 747 WR16(SC_COMM_STATE__A, 0), 748 748 ··· 756 756 757 757 /* Diversity settings */ 758 758 759 - u8_t DRXD_InitDiversityFront[] = { 759 + u8 DRXD_InitDiversityFront[] = { 760 760 /* Start demod ********* RF in , diversity out **************************** */ 761 761 WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | 762 762 B_SC_RA_RAM_CONFIG_FREQSCAN__M), ··· 793 793 END_OF_TABLE 794 794 }; 795 795 796 - u8_t DRXD_InitDiversityEnd[] = { 796 + u8 DRXD_InitDiversityEnd[] = { 797 797 /* End demod *********** combining RF in and diversity in, MPEG TS out **** */ 798 798 /* disable near/far; switch on timing slave mode */ 799 799 WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | ··· 835 835 END_OF_TABLE 836 836 }; 837 837 838 - u8_t DRXD_DisableDiversity[] = { 838 + u8 DRXD_DisableDiversity[] = { 839 839 WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE), 840 840 WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE), 841 841 WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, ··· 876 876 END_OF_TABLE 877 877 }; 878 878 879 - u8_t DRXD_StartDiversityFront[] = { 879 + u8 DRXD_StartDiversityFront[] = { 880 880 /* Start demod, RF in and diversity out, no combining */ 881 881 WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), 882 882 WR16(B_FE_AD_REG_FDB_IN__A, 0x0), ··· 890 890 END_OF_TABLE 891 891 }; 892 892 893 - u8_t DRXD_StartDiversityEnd[] = { 893 + u8 DRXD_StartDiversityEnd[] = { 894 894 /* End demod, combining RF in and diversity in, MPEG TS out */ 895 895 WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */ 896 896 WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */ ··· 903 903 END_OF_TABLE 904 904 }; 905 905 906 - u8_t DRXD_DiversityDelay8MHZ[] = { 906 + u8 DRXD_DiversityDelay8MHZ[] = { 907 907 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50), 908 908 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50), 909 909 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50), ··· 915 915 END_OF_TABLE 916 916 }; 917 917 918 - u8_t DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */ 918 + u8 DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */ 919 919 { 920 920 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50), 921 921 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50),
+31 -34
drivers/media/dvb/frontends/drxd_firm.h
··· 24 24 #ifndef _DRXD_FIRM_H_ 25 25 #define _DRXD_FIRM_H_ 26 26 27 + #include <linux/types.h> 27 28 #include "drxd_map_firm.h" 28 - 29 - typedef unsigned char u8_t; 30 - typedef unsigned short u16_t; 31 - typedef unsigned long u32_t; 32 29 33 30 #define VERSION_MAJOR 1 34 31 #define VERSION_MINOR 4 ··· 74 77 #define DIFF_TARGET (4) 75 78 #define DIFF_MARGIN (1) 76 79 77 - extern u8_t DRXD_InitAtomicRead[]; 78 - extern u8_t DRXD_HiI2cPatch_1[]; 79 - extern u8_t DRXD_HiI2cPatch_3[]; 80 + extern u8 DRXD_InitAtomicRead[]; 81 + extern u8 DRXD_HiI2cPatch_1[]; 82 + extern u8 DRXD_HiI2cPatch_3[]; 80 83 81 - extern u8_t DRXD_InitSC[]; 84 + extern u8 DRXD_InitSC[]; 82 85 83 - extern u8_t DRXD_ResetCEFR[]; 84 - extern u8_t DRXD_InitFEA2_1[]; 85 - extern u8_t DRXD_InitFEA2_2[]; 86 - extern u8_t DRXD_InitCPA2[]; 87 - extern u8_t DRXD_InitCEA2[]; 88 - extern u8_t DRXD_InitEQA2[]; 89 - extern u8_t DRXD_InitECA2[]; 90 - extern u8_t DRXD_ResetECA2[]; 91 - extern u8_t DRXD_ResetECRAM[]; 86 + extern u8 DRXD_ResetCEFR[]; 87 + extern u8 DRXD_InitFEA2_1[]; 88 + extern u8 DRXD_InitFEA2_2[]; 89 + extern u8 DRXD_InitCPA2[]; 90 + extern u8 DRXD_InitCEA2[]; 91 + extern u8 DRXD_InitEQA2[]; 92 + extern u8 DRXD_InitECA2[]; 93 + extern u8 DRXD_ResetECA2[]; 94 + extern u8 DRXD_ResetECRAM[]; 92 95 93 - extern u8_t DRXD_A2_microcode[]; 94 - extern u32_t DRXD_A2_microcode_length; 96 + extern u8 DRXD_A2_microcode[]; 97 + extern u32 DRXD_A2_microcode_length; 95 98 96 - extern u8_t DRXD_InitFEB1_1[]; 97 - extern u8_t DRXD_InitFEB1_2[]; 98 - extern u8_t DRXD_InitCPB1[]; 99 - extern u8_t DRXD_InitCEB1[]; 100 - extern u8_t DRXD_InitEQB1[]; 101 - extern u8_t DRXD_InitECB1[]; 99 + extern u8 DRXD_InitFEB1_1[]; 100 + extern u8 DRXD_InitFEB1_2[]; 101 + extern u8 DRXD_InitCPB1[]; 102 + extern u8 DRXD_InitCEB1[]; 103 + extern u8 DRXD_InitEQB1[]; 104 + extern u8 DRXD_InitECB1[]; 102 105 103 - extern u8_t DRXD_InitDiversityFront[]; 104 - extern u8_t DRXD_InitDiversityEnd[]; 105 - extern u8_t DRXD_DisableDiversity[]; 106 - extern u8_t DRXD_StartDiversityFront[]; 107 - extern u8_t DRXD_StartDiversityEnd[]; 106 + extern u8 DRXD_InitDiversityFront[]; 107 + extern u8 DRXD_InitDiversityEnd[]; 108 + extern u8 DRXD_DisableDiversity[]; 109 + extern u8 DRXD_StartDiversityFront[]; 110 + extern u8 DRXD_StartDiversityEnd[]; 108 111 109 - extern u8_t DRXD_DiversityDelay8MHZ[]; 110 - extern u8_t DRXD_DiversityDelay6MHZ[]; 112 + extern u8 DRXD_DiversityDelay8MHZ[]; 113 + extern u8 DRXD_DiversityDelay6MHZ[]; 111 114 112 - extern u8_t DRXD_B1_microcode[]; 113 - extern u32_t DRXD_B1_microcode_length; 115 + extern u8 DRXD_B1_microcode[]; 116 + extern u32 DRXD_B1_microcode_length; 114 117 115 118 #endif