tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARCv2: MMUv4: support aliasing icache config
This is also default for AXS103 release
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
+14
-4
+1
-3
arch/arc/include/asm/cache.h
+1
-3
arch/arc/include/asm/cache.h
···
60
60
#define ARC_REG_IC_IVIC 0x10
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#define ARC_REG_IC_CTRL 0x11
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#define ARC_REG_IC_IVIL 0x19
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-
#if defined(CONFIG_ARC_MMU_V3)
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+
#if defined(CONFIG_ARC_MMU_V3) || defined(CONFIG_ARC_MMU_V4)
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#define ARC_REG_IC_PTAG 0x1E
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#endif
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66
···
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#define ARC_REG_DC_IVDL 0x4A
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#define ARC_REG_DC_FLSH 0x4B
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#define ARC_REG_DC_FLDL 0x4C
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-
#if defined(CONFIG_ARC_MMU_V3)
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#define ARC_REG_DC_PTAG 0x5C
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-
#endif
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/* Bit val in DC_CTRL */
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#define DC_CTRL_INV_MODE_FLUSH 0x40
+13
-1
arch/arc/mm/cache.c
+13
-1
arch/arc/mm/cache.c
···
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21
#include <asm/cachectl.h>
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#include <asm/setup.h>
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23
24
+
void (*_cache_line_loop_ic_fn)(unsigned long paddr, unsigned long vaddr,
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+
unsigned long sz, const int cacheop);
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+
24
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char *arc_cache_mumbojumbo(int c, char *buf, int len)
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{
26
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int n = 0;
···
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unsigned long flags;
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local_irq_save(flags);
420
-
__cache_line_loop(paddr, vaddr, sz, OP_INV_IC);
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+
(*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC);
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local_irq_restore(flags);
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}
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420
···
749
746
if (ic->ver != CONFIG_ARC_MMU_VER)
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panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
751
748
ic->ver, CONFIG_ARC_MMU_VER);
749
+
750
+
/*
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+
* In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG
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+
* pair to provide vaddr/paddr respectively, just as in MMU v3
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+
*/
754
+
if (is_isa_arcv2() && ic->alias)
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+
_cache_line_loop_ic_fn = __cache_line_loop_v3;
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+
else
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+
_cache_line_loop_ic_fn = __cache_line_loop;
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}
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754
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if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) {