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ARM: dts: uniphier: update to new Denali NAND binding

With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller
and NAND chips"), the Denali NAND controller driver migrated to the
new controller/chip representation.

Update DT for it.

In the new binding, the number of connected chips are described in
DT instead of run-time probed.

I added just one chip to the reference boards, where we do not know
if the on-board NAND device is a single chip or multiple chips.
If we added too many chips into DT, it would end up with the timeout
error in nand_scan_ident().

I changed all the pinctrl properties to use the single CS.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Masahiro Yamada bc8841f0 a188339c

+30 -4
+4
arch/arm/boot/dts/uniphier-ld4-ref.dts
··· 77 77 78 78 &nand { 79 79 status = "okay"; 80 + 81 + nand@0 { 82 + reg = <0>; 83 + }; 80 84 };
+3 -1
arch/arm/boot/dts/uniphier-ld4.dtsi
··· 403 403 status = "disabled"; 404 404 reg-names = "nand_data", "denali_reg"; 405 405 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 406 + #address-cells = <1>; 407 + #size-cells = <0>; 406 408 interrupts = <0 65 4>; 407 409 pinctrl-names = "default"; 408 - pinctrl-0 = <&pinctrl_nand2cs>; 410 + pinctrl-0 = <&pinctrl_nand>; 409 411 clock-names = "nand", "nand_x", "ecc"; 410 412 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 411 413 resets = <&sys_rst 2>;
+4
arch/arm/boot/dts/uniphier-ld6b-ref.dts
··· 90 90 91 91 &nand { 92 92 status = "okay"; 93 + 94 + nand@0 { 95 + reg = <0>; 96 + }; 93 97 };
+4
arch/arm/boot/dts/uniphier-pro4-ref.dts
··· 98 98 99 99 &nand { 100 100 status = "okay"; 101 + 102 + nand@0 { 103 + reg = <0>; 104 + }; 101 105 };
+2
arch/arm/boot/dts/uniphier-pro4.dtsi
··· 593 593 status = "disabled"; 594 594 reg-names = "nand_data", "denali_reg"; 595 595 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 596 + #address-cells = <1>; 597 + #size-cells = <0>; 596 598 interrupts = <0 65 4>; 597 599 pinctrl-names = "default"; 598 600 pinctrl-0 = <&pinctrl_nand>;
+3 -1
arch/arm/boot/dts/uniphier-pro5.dtsi
··· 458 458 status = "disabled"; 459 459 reg-names = "nand_data", "denali_reg"; 460 460 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 461 + #address-cells = <1>; 462 + #size-cells = <0>; 461 463 interrupts = <0 65 4>; 462 464 pinctrl-names = "default"; 463 - pinctrl-0 = <&pinctrl_nand2cs>; 465 + pinctrl-0 = <&pinctrl_nand>; 464 466 clock-names = "nand", "nand_x", "ecc"; 465 467 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 466 468 resets = <&sys_rst 2>;
+3 -1
arch/arm/boot/dts/uniphier-pxs2.dtsi
··· 766 766 status = "disabled"; 767 767 reg-names = "nand_data", "denali_reg"; 768 768 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 769 + #address-cells = <1>; 770 + #size-cells = <0>; 769 771 interrupts = <0 65 4>; 770 772 pinctrl-names = "default"; 771 - pinctrl-0 = <&pinctrl_nand2cs>; 773 + pinctrl-0 = <&pinctrl_nand>; 772 774 clock-names = "nand", "nand_x", "ecc"; 773 775 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 774 776 resets = <&sys_rst 2>;
+4
arch/arm/boot/dts/uniphier-sld8-ref.dts
··· 81 81 82 82 &nand { 83 83 status = "okay"; 84 + 85 + nand@0 { 86 + reg = <0>; 87 + }; 84 88 };
+3 -1
arch/arm/boot/dts/uniphier-sld8.dtsi
··· 407 407 status = "disabled"; 408 408 reg-names = "nand_data", "denali_reg"; 409 409 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 410 + #address-cells = <1>; 411 + #size-cells = <0>; 410 412 interrupts = <0 65 4>; 411 413 pinctrl-names = "default"; 412 - pinctrl-0 = <&pinctrl_nand2cs>; 414 + pinctrl-0 = <&pinctrl_nand>; 413 415 clock-names = "nand", "nand_x", "ecc"; 414 416 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 415 417 resets = <&sys_rst 2>;