tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/radeon: add support mc ucode loading on CIK (v2)
Load the GDDR5 ucode and train the links.
v2: update ucode
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+132
+116
drivers/gpu/drm/radeon/cik.c
+116
drivers/gpu/drm/radeon/cik.c
···
65
65
extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
66
66
extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
67
67
68
+
#define BONAIRE_IO_MC_REGS_SIZE 36
69
+
70
+
static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
71
+
{
72
+
{0x00000070, 0x04400000},
73
+
{0x00000071, 0x80c01803},
74
+
{0x00000072, 0x00004004},
75
+
{0x00000073, 0x00000100},
76
+
{0x00000074, 0x00ff0000},
77
+
{0x00000075, 0x34000000},
78
+
{0x00000076, 0x08000014},
79
+
{0x00000077, 0x00cc08ec},
80
+
{0x00000078, 0x00000400},
81
+
{0x00000079, 0x00000000},
82
+
{0x0000007a, 0x04090000},
83
+
{0x0000007c, 0x00000000},
84
+
{0x0000007e, 0x4408a8e8},
85
+
{0x0000007f, 0x00000304},
86
+
{0x00000080, 0x00000000},
87
+
{0x00000082, 0x00000001},
88
+
{0x00000083, 0x00000002},
89
+
{0x00000084, 0xf3e4f400},
90
+
{0x00000085, 0x052024e3},
91
+
{0x00000087, 0x00000000},
92
+
{0x00000088, 0x01000000},
93
+
{0x0000008a, 0x1c0a0000},
94
+
{0x0000008b, 0xff010000},
95
+
{0x0000008d, 0xffffefff},
96
+
{0x0000008e, 0xfff3efff},
97
+
{0x0000008f, 0xfff3efbf},
98
+
{0x00000092, 0xf7ffffff},
99
+
{0x00000093, 0xffffff7f},
100
+
{0x00000095, 0x00101101},
101
+
{0x00000096, 0x00000fff},
102
+
{0x00000097, 0x00116fff},
103
+
{0x00000098, 0x60010000},
104
+
{0x00000099, 0x10010000},
105
+
{0x0000009a, 0x00006000},
106
+
{0x0000009b, 0x00001000},
107
+
{0x0000009f, 0x00b48000}
108
+
};
109
+
110
+
/* ucode loading */
111
+
/**
112
+
* ci_mc_load_microcode - load MC ucode into the hw
113
+
*
114
+
* @rdev: radeon_device pointer
115
+
*
116
+
* Load the GDDR MC ucode into the hw (CIK).
117
+
* Returns 0 on success, error on failure.
118
+
*/
119
+
static int ci_mc_load_microcode(struct radeon_device *rdev)
120
+
{
121
+
const __be32 *fw_data;
122
+
u32 running, blackout = 0;
123
+
u32 *io_mc_regs;
124
+
int i, ucode_size, regs_size;
125
+
126
+
if (!rdev->mc_fw)
127
+
return -EINVAL;
128
+
129
+
switch (rdev->family) {
130
+
case CHIP_BONAIRE:
131
+
default:
132
+
io_mc_regs = (u32 *)&bonaire_io_mc_regs;
133
+
ucode_size = CIK_MC_UCODE_SIZE;
134
+
regs_size = BONAIRE_IO_MC_REGS_SIZE;
135
+
break;
136
+
}
137
+
138
+
running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
139
+
140
+
if (running == 0) {
141
+
if (running) {
142
+
blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
143
+
WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
144
+
}
145
+
146
+
/* reset the engine and set to writable */
147
+
WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
148
+
WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
149
+
150
+
/* load mc io regs */
151
+
for (i = 0; i < regs_size; i++) {
152
+
WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
153
+
WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
154
+
}
155
+
/* load the MC ucode */
156
+
fw_data = (const __be32 *)rdev->mc_fw->data;
157
+
for (i = 0; i < ucode_size; i++)
158
+
WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
159
+
160
+
/* put the engine back into the active state */
161
+
WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
162
+
WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
163
+
WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
164
+
165
+
/* wait for training to complete */
166
+
for (i = 0; i < rdev->usec_timeout; i++) {
167
+
if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
168
+
break;
169
+
udelay(1);
170
+
}
171
+
for (i = 0; i < rdev->usec_timeout; i++) {
172
+
if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
173
+
break;
174
+
udelay(1);
175
+
}
176
+
177
+
if (running)
178
+
WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
179
+
}
180
+
181
+
return 0;
182
+
}
183
+
68
184
/**
69
185
* cik_init_microcode - load ucode images from disk
70
186
*
+16
drivers/gpu/drm/radeon/cikd.h
+16
drivers/gpu/drm/radeon/cikd.h
···
139
139
#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
140
140
#define MC_VM_FB_OFFSET 0x2068
141
141
142
+
#define MC_SHARED_BLACKOUT_CNTL 0x20ac
143
+
142
144
#define MC_ARB_RAMCFG 0x2760
143
145
#define NOOFBANK_SHIFT 0
144
146
#define NOOFBANK_MASK 0x00000003
···
154
152
#define CHANSIZE_MASK 0x00000100
155
153
#define NOOFGROUPS_SHIFT 12
156
154
#define NOOFGROUPS_MASK 0x00001000
155
+
156
+
#define MC_SEQ_SUP_CNTL 0x28c8
157
+
#define RUN_MASK (1 << 0)
158
+
#define MC_SEQ_SUP_PGM 0x28cc
159
+
160
+
#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
161
+
#define TRAIN_DONE_D0 (1 << 30)
162
+
#define TRAIN_DONE_D1 (1 << 31)
163
+
164
+
#define MC_IO_PAD_CNTL_D0 0x29d0
165
+
#define MEM_FALL_OUT_CMD (1 << 8)
166
+
167
+
#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
168
+
#define MC_SEQ_IO_DEBUG_DATA 0x2a48
157
169
158
170
#define HDP_HOST_PATH_CNTL 0x2C00
159
171
#define HDP_NONSURFACE_BASE 0x2C04