tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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ARM: dts: uniphier: rename cache controller nodes to follow json-schema

Follow the standard nodename pattern
"^(cache-controller|cpu)(@[0-9a-f,]+)*$" defined in
schemas/cache-controller.yaml of dt-schema.

Otherwise, after the dt-binding is converted to json-schema,
'make ARCH=arm dtbs_check' will show warnings like this:

l2-cache@500c0000: $nodename:0: 'l2-cache@500c0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Masahiro Yamada bc350d10 f215c5ef

+6 -6
+1 -1
arch/arm/boot/dts/uniphier-ld4.dtsi
··· 51 51 ranges; 52 52 interrupt-parent = <&intc>; 53 53 54 - l2: l2-cache@500c0000 { 54 + l2: cache-controller@500c0000 { 55 55 compatible = "socionext,uniphier-system-cache"; 56 56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 57 57 <0x506c0000 0x400>;
+1 -1
arch/arm/boot/dts/uniphier-pro4.dtsi
··· 59 59 ranges; 60 60 interrupt-parent = <&intc>; 61 61 62 - l2: l2-cache@500c0000 { 62 + l2: cache-controller@500c0000 { 63 63 compatible = "socionext,uniphier-system-cache"; 64 64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 65 65 <0x506c0000 0x400>;
+2 -2
arch/arm/boot/dts/uniphier-pro5.dtsi
··· 131 131 ranges; 132 132 interrupt-parent = <&intc>; 133 133 134 - l2: l2-cache@500c0000 { 134 + l2: cache-controller@500c0000 { 135 135 compatible = "socionext,uniphier-system-cache"; 136 136 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 137 137 <0x506c0000 0x400>; ··· 144 144 next-level-cache = <&l3>; 145 145 }; 146 146 147 - l3: l3-cache@500c8000 { 147 + l3: cache-controller@500c8000 { 148 148 compatible = "socionext,uniphier-system-cache"; 149 149 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, 150 150 <0x506c8000 0x400>;
+1 -1
arch/arm/boot/dts/uniphier-pxs2.dtsi
··· 157 157 ranges; 158 158 interrupt-parent = <&intc>; 159 159 160 - l2: l2-cache@500c0000 { 160 + l2: cache-controller@500c0000 { 161 161 compatible = "socionext,uniphier-system-cache"; 162 162 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 163 163 <0x506c0000 0x400>;
+1 -1
arch/arm/boot/dts/uniphier-sld8.dtsi
··· 51 51 ranges; 52 52 interrupt-parent = <&intc>; 53 53 54 - l2: l2-cache@500c0000 { 54 + l2: cache-controller@500c0000 { 55 55 compatible = "socionext,uniphier-system-cache"; 56 56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 57 57 <0x506c0000 0x400>;