tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 platform updates from Ingo Molnar:
"The main change is the addition of SGI/UV4 support"

* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits)
x86/platform/UV: Fix incorrect nodes and pnodes for cpuless and memoryless nodes
x86/platform/UV: Remove Obsolete GRU MMR address translation
x86/platform/UV: Update physical address conversions for UV4
x86/platform/UV: Build GAM reference tables
x86/platform/UV: Support UV4 socket address changes
x86/platform/UV: Add obtaining GAM Range Table from UV BIOS
x86/platform/UV: Add UV4 addressing discovery function
x86/platform/UV: Fold blade info into per node hub info structs
x86/platform/UV: Allocate common per node hub info structs on local node
x86/platform/UV: Move blade local processor ID to the per cpu info struct
x86/platform/UV: Move scir info to the per cpu info struct
x86/platform/UV: Create per cpu info structs to replace per hub info structs
x86/platform/UV: Update MMIOH setup function to work for both UV3 and UV4
x86/platform/UV: Clean up redunduncies after merge of UV4 MMR definitions
x86/platform/UV: Add UV4 Specific MMR definitions
x86/platform/UV: Prep for UV4 MMR updates
x86/platform/UV: Add UV MMR Illegal Access Function
x86/platform/UV: Add UV4 Specific Defines
x86/platform/UV: Add UV Architecture Defines
x86/platform/UV: Add Initial UV4 definitions
...

Linus Torvalds bc231d9e 62a00278

+2903 -801
+8
Documentation/kernel-parameters.txt
··· 131 131 More X86-64 boot options can be found in 132 132 Documentation/x86/x86_64/boot-options.txt . 133 133 X86 Either 32-bit or 64-bit x86 (same as X86-32+X86-64) 134 + X86_UV SGI UV support is enabled. 134 135 XEN Xen support is enabled 135 136 136 137 In addition, the following text indicates that the option: ··· 542 541 audit_backlog_limit= [KNL] Set the audit queue size limit. 543 542 Format: <int> (must be >=0) 544 543 Default: 64 544 + 545 + bau= [X86_UV] Enable the BAU on SGI UV. The default 546 + behavior is to disable the BAU (i.e. bau=0). 547 + Format: { "0" | "1" } 548 + 0 - Disable the BAU. 549 + 1 - Enable the BAU. 550 + unset - Disable the BAU. 545 551 546 552 baycom_epp= [HW,AX25] 547 553 Format: <io>,<mode>
-21
arch/x86/include/asm/bios_ebda.h
··· 17 17 return address; /* 0 means none */ 18 18 } 19 19 20 - /* 21 - * Return the sanitized length of the EBDA in bytes, if it exists. 22 - */ 23 - static inline unsigned int get_bios_ebda_length(void) 24 - { 25 - unsigned int address; 26 - unsigned int length; 27 - 28 - address = get_bios_ebda(); 29 - if (!address) 30 - return 0; 31 - 32 - /* EBDA length is byte 0 of the EBDA (stored in KiB) */ 33 - length = *(unsigned char *)phys_to_virt(address); 34 - length <<= 10; 35 - 36 - /* Trim the length if it extends beyond 640KiB */ 37 - length = min_t(unsigned int, (640 * 1024) - address, length); 38 - return length; 39 - } 40 - 41 20 void reserve_ebda_region(void); 42 21 43 22 #ifdef CONFIG_X86_CHECK_BIOS_CORRUPTION
+57 -2
arch/x86/include/asm/uv/bios.h
··· 51 51 BIOS_STATUS_UNAVAIL = -EBUSY 52 52 }; 53 53 54 + /* Address map parameters */ 55 + struct uv_gam_parameters { 56 + u64 mmr_base; 57 + u64 gru_base; 58 + u8 mmr_shift; /* Convert PNode to MMR space offset */ 59 + u8 gru_shift; /* Convert PNode to GRU space offset */ 60 + u8 gpa_shift; /* Size of offset field in GRU phys addr */ 61 + u8 unused1; 62 + }; 63 + 64 + /* UV_TABLE_GAM_RANGE_ENTRY values */ 65 + #define UV_GAM_RANGE_TYPE_UNUSED 0 /* End of table */ 66 + #define UV_GAM_RANGE_TYPE_RAM 1 /* Normal RAM */ 67 + #define UV_GAM_RANGE_TYPE_NVRAM 2 /* Non-volatile memory */ 68 + #define UV_GAM_RANGE_TYPE_NV_WINDOW 3 /* NVMDIMM block window */ 69 + #define UV_GAM_RANGE_TYPE_NV_MAILBOX 4 /* NVMDIMM mailbox */ 70 + #define UV_GAM_RANGE_TYPE_HOLE 5 /* Unused address range */ 71 + #define UV_GAM_RANGE_TYPE_MAX 6 72 + 73 + /* The structure stores PA bits 56:26, for 64MB granularity */ 74 + #define UV_GAM_RANGE_SHFT 26 /* 64MB */ 75 + 76 + struct uv_gam_range_entry { 77 + char type; /* Entry type: GAM_RANGE_TYPE_UNUSED, etc. */ 78 + char unused1; 79 + u16 nasid; /* HNasid */ 80 + u16 sockid; /* Socket ID, high bits of APIC ID */ 81 + u16 pnode; /* Index to MMR and GRU spaces */ 82 + u32 pxm; /* ACPI proximity domain number */ 83 + u32 limit; /* PA bits 56:26 (UV_GAM_RANGE_SHFT) */ 84 + }; 85 + 86 + #define UV_SYSTAB_SIG "UVST" 87 + #define UV_SYSTAB_VERSION_1 1 /* UV1/2/3 BIOS version */ 88 + #define UV_SYSTAB_VERSION_UV4 0x400 /* UV4 BIOS base version */ 89 + #define UV_SYSTAB_VERSION_UV4_1 0x401 /* + gpa_shift */ 90 + #define UV_SYSTAB_VERSION_UV4_2 0x402 /* + TYPE_NVRAM/WINDOW/MBOX */ 91 + #define UV_SYSTAB_VERSION_UV4_LATEST UV_SYSTAB_VERSION_UV4_2 92 + 93 + #define UV_SYSTAB_TYPE_UNUSED 0 /* End of table (offset == 0) */ 94 + #define UV_SYSTAB_TYPE_GAM_PARAMS 1 /* GAM PARAM conversions */ 95 + #define UV_SYSTAB_TYPE_GAM_RNG_TBL 2 /* GAM entry table */ 96 + #define UV_SYSTAB_TYPE_MAX 3 97 + 54 98 /* 55 99 * The UV system table describes specific firmware 56 100 * capabilities available to the Linux kernel at runtime. 57 101 */ 58 102 struct uv_systab { 59 - char signature[4]; /* must be "UVST" */ 103 + char signature[4]; /* must be UV_SYSTAB_SIG */ 60 104 u32 revision; /* distinguish different firmware revs */ 61 105 u64 function; /* BIOS runtime callback function ptr */ 106 + u32 size; /* systab size (starting with _VERSION_UV4) */ 107 + struct { 108 + u32 type:8; /* type of entry */ 109 + u32 offset:24; /* byte offset from struct start to entry */ 110 + } entry[1]; /* additional entries follow */ 62 111 }; 112 + extern struct uv_systab *uv_systab; 113 + /* (... end of definitions from UV BIOS ...) */ 63 114 64 115 enum { 65 116 BIOS_FREQ_BASE_PLATFORM = 0, ··· 150 99 extern s64 uv_bios_reserved_page_pa(u64, u64 *, u64 *, u64 *); 151 100 extern int uv_bios_set_legacy_vga_target(bool decode, int domain, int bus); 152 101 102 + #ifdef CONFIG_EFI 153 103 extern void uv_bios_init(void); 104 + #else 105 + void uv_bios_init(void) { } 106 + #endif 154 107 155 108 extern unsigned long sn_rtc_cycles_per_second; 156 109 extern int uv_type; ··· 162 107 extern long sn_coherency_id; 163 108 extern long sn_region_size; 164 109 extern long system_serial_number; 165 - #define partition_coherence_id() (sn_coherency_id) 110 + #define uv_partition_coherence_id() (sn_coherency_id) 166 111 167 112 extern struct kobject *sgi_uv_kobj; /* /sys/firmware/sgi_uv */ 168 113
+1 -1
arch/x86/include/asm/uv/uv_bau.h
··· 598 598 int timeout_tries; 599 599 int ipi_attempts; 600 600 int conseccompletes; 601 - short nobau; 601 + bool nobau; 602 602 short baudisabled; 603 603 short cpu; 604 604 short osnode;
+308 -109
arch/x86/include/asm/uv/uv_hub.h
··· 16 16 #include <linux/percpu.h> 17 17 #include <linux/timer.h> 18 18 #include <linux/io.h> 19 + #include <linux/topology.h> 19 20 #include <asm/types.h> 20 21 #include <asm/percpu.h> 21 22 #include <asm/uv/uv_mmrs.h> 23 + #include <asm/uv/bios.h> 22 24 #include <asm/irq_vectors.h> 23 25 #include <asm/io_apic.h> 24 26 ··· 105 103 * processor APICID register. 106 104 */ 107 105 108 - 109 106 /* 110 107 * Maximum number of bricks in all partitions and in all coherency domains. 111 108 * This is the total number of bricks accessible in the numalink fabric. It ··· 128 127 */ 129 128 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) 130 129 130 + /* System Controller Interface Reg info */ 131 131 struct uv_scir_s { 132 132 struct timer_list timer; 133 133 unsigned long offset; ··· 139 137 unsigned char enabled; 140 138 }; 141 139 140 + /* GAM (globally addressed memory) range table */ 141 + struct uv_gam_range_s { 142 + u32 limit; /* PA bits 56:26 (GAM_RANGE_SHFT) */ 143 + u16 nasid; /* node's global physical address */ 144 + s8 base; /* entry index of node's base addr */ 145 + u8 reserved; 146 + }; 147 + 142 148 /* 143 149 * The following defines attributes of the HUB chip. These attributes are 144 - * frequently referenced and are kept in the per-cpu data areas of each cpu. 145 - * They are kept together in a struct to minimize cache misses. 150 + * frequently referenced and are kept in a common per hub struct. 151 + * After setup, the struct is read only, so it should be readily 152 + * available in the L3 cache on the cpu socket for the node. 146 153 */ 147 154 struct uv_hub_info_s { 148 155 unsigned long global_mmr_base; 156 + unsigned long global_mmr_shift; 149 157 unsigned long gpa_mask; 150 - unsigned int gnode_extra; 158 + unsigned short *socket_to_node; 159 + unsigned short *socket_to_pnode; 160 + unsigned short *pnode_to_socket; 161 + struct uv_gam_range_s *gr_table; 162 + unsigned short min_socket; 163 + unsigned short min_pnode; 164 + unsigned char m_val; 165 + unsigned char n_val; 166 + unsigned char gr_table_len; 151 167 unsigned char hub_revision; 152 168 unsigned char apic_pnode_shift; 169 + unsigned char gpa_shift; 153 170 unsigned char m_shift; 154 171 unsigned char n_lshift; 172 + unsigned int gnode_extra; 155 173 unsigned long gnode_upper; 156 174 unsigned long lowmem_remap_top; 157 175 unsigned long lowmem_remap_base; 176 + unsigned long global_gru_base; 177 + unsigned long global_gru_shift; 158 178 unsigned short pnode; 159 179 unsigned short pnode_mask; 160 180 unsigned short coherency_domain_number; 161 181 unsigned short numa_blade_id; 162 - unsigned char blade_processor_id; 163 - unsigned char m_val; 164 - unsigned char n_val; 165 - struct uv_scir_s scir; 182 + unsigned short nr_possible_cpus; 183 + unsigned short nr_online_cpus; 184 + short memory_nid; 166 185 }; 167 186 168 - DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 169 - #define uv_hub_info this_cpu_ptr(&__uv_hub_info) 170 - #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) 187 + /* CPU specific info with a pointer to the hub common info struct */ 188 + struct uv_cpu_info_s { 189 + void *p_uv_hub_info; 190 + unsigned char blade_cpu_id; 191 + struct uv_scir_s scir; 192 + }; 193 + DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 194 + 195 + #define uv_cpu_info this_cpu_ptr(&__uv_cpu_info) 196 + #define uv_cpu_info_per(cpu) (&per_cpu(__uv_cpu_info, cpu)) 197 + 198 + #define uv_scir_info (&uv_cpu_info->scir) 199 + #define uv_cpu_scir_info(cpu) (&uv_cpu_info_per(cpu)->scir) 200 + 201 + /* Node specific hub common info struct */ 202 + extern void **__uv_hub_info_list; 203 + static inline struct uv_hub_info_s *uv_hub_info_list(int node) 204 + { 205 + return (struct uv_hub_info_s *)__uv_hub_info_list[node]; 206 + } 207 + 208 + static inline struct uv_hub_info_s *_uv_hub_info(void) 209 + { 210 + return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info; 211 + } 212 + #define uv_hub_info _uv_hub_info() 213 + 214 + static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu) 215 + { 216 + return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info; 217 + } 218 + 219 + #define UV_HUB_INFO_VERSION 0x7150 220 + extern int uv_hub_info_version(void); 221 + static inline int uv_hub_info_check(int version) 222 + { 223 + if (uv_hub_info_version() == version) 224 + return 0; 225 + 226 + pr_crit("UV: uv_hub_info version(%x) mismatch, expecting(%x)\n", 227 + uv_hub_info_version(), version); 228 + 229 + BUG(); /* Catastrophic - cannot continue on unknown UV system */ 230 + } 231 + #define _uv_hub_info_check() uv_hub_info_check(UV_HUB_INFO_VERSION) 171 232 172 233 /* 173 - * Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2 174 - * hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE. 234 + * HUB revision ranges for each UV HUB architecture. 175 235 * This is a software convention - NOT the hardware revision numbers in 176 236 * the hub chip. 177 237 */ 178 238 #define UV1_HUB_REVISION_BASE 1 179 239 #define UV2_HUB_REVISION_BASE 3 180 240 #define UV3_HUB_REVISION_BASE 5 241 + #define UV4_HUB_REVISION_BASE 7 181 242 243 + #ifdef UV1_HUB_IS_SUPPORTED 182 244 static inline int is_uv1_hub(void) 183 245 { 184 246 return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE; 185 247 } 248 + #else 249 + static inline int is_uv1_hub(void) 250 + { 251 + return 0; 252 + } 253 + #endif 186 254 255 + #ifdef UV2_HUB_IS_SUPPORTED 187 256 static inline int is_uv2_hub(void) 188 257 { 189 258 return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) && 190 259 (uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE)); 191 260 } 261 + #else 262 + static inline int is_uv2_hub(void) 263 + { 264 + return 0; 265 + } 266 + #endif 192 267 268 + #ifdef UV3_HUB_IS_SUPPORTED 193 269 static inline int is_uv3_hub(void) 194 270 { 195 - return uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE; 271 + return ((uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE) && 272 + (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)); 273 + } 274 + #else 275 + static inline int is_uv3_hub(void) 276 + { 277 + return 0; 278 + } 279 + #endif 280 + 281 + #ifdef UV4_HUB_IS_SUPPORTED 282 + static inline int is_uv4_hub(void) 283 + { 284 + return uv_hub_info->hub_revision >= UV4_HUB_REVISION_BASE; 285 + } 286 + #else 287 + static inline int is_uv4_hub(void) 288 + { 289 + return 0; 290 + } 291 + #endif 292 + 293 + static inline int is_uvx_hub(void) 294 + { 295 + if (uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) 296 + return uv_hub_info->hub_revision; 297 + 298 + return 0; 196 299 } 197 300 198 301 static inline int is_uv_hub(void) 199 302 { 303 + #ifdef UV1_HUB_IS_SUPPORTED 200 304 return uv_hub_info->hub_revision; 201 - } 202 - 203 - /* code common to uv2 and uv3 only */ 204 - static inline int is_uvx_hub(void) 205 - { 206 - return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE; 305 + #endif 306 + return is_uvx_hub(); 207 307 } 208 308 209 309 union uvh_apicid { ··· 347 243 #define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 348 244 #define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 349 245 350 - #define UV_LOCAL_MMR_BASE (is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \ 351 - (is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \ 352 - UV3_LOCAL_MMR_BASE)) 353 - #define UV_GLOBAL_MMR32_BASE (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE :\ 354 - (is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE :\ 355 - UV3_GLOBAL_MMR32_BASE)) 356 - #define UV_LOCAL_MMR_SIZE (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ 357 - (is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \ 358 - UV3_LOCAL_MMR_SIZE)) 359 - #define UV_GLOBAL_MMR32_SIZE (is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\ 360 - (is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE :\ 361 - UV3_GLOBAL_MMR32_SIZE)) 246 + #define UV4_LOCAL_MMR_BASE 0xfa000000UL 247 + #define UV4_GLOBAL_MMR32_BASE 0xfc000000UL 248 + #define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 249 + #define UV4_GLOBAL_MMR32_SIZE (16UL * 1024 * 1024) 250 + 251 + #define UV_LOCAL_MMR_BASE ( \ 252 + is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \ 253 + is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \ 254 + is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \ 255 + /*is_uv4_hub*/ UV4_LOCAL_MMR_BASE) 256 + 257 + #define UV_GLOBAL_MMR32_BASE ( \ 258 + is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \ 259 + is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \ 260 + is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \ 261 + /*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE) 262 + 263 + #define UV_LOCAL_MMR_SIZE ( \ 264 + is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ 265 + is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \ 266 + is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \ 267 + /*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE) 268 + 269 + #define UV_GLOBAL_MMR32_SIZE ( \ 270 + is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \ 271 + is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \ 272 + is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \ 273 + /*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE) 274 + 362 275 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 363 276 364 277 #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 365 278 366 279 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 367 - #define UV_GLOBAL_MMR64_PNODE_SHIFT 26 280 + #define _UV_GLOBAL_MMR64_PNODE_SHIFT 26 281 + #define UV_GLOBAL_MMR64_PNODE_SHIFT (uv_hub_info->global_mmr_shift) 368 282 369 283 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 370 284 ··· 429 307 * between socket virtual and socket physical addresses. 430 308 */ 431 309 310 + /* global bits offset - number of local address bits in gpa for this UV arch */ 311 + static inline unsigned int uv_gpa_shift(void) 312 + { 313 + return uv_hub_info->gpa_shift; 314 + } 315 + #define _uv_gpa_shift 316 + 317 + /* Find node that has the address range that contains global address */ 318 + static inline struct uv_gam_range_s *uv_gam_range(unsigned long pa) 319 + { 320 + struct uv_gam_range_s *gr = uv_hub_info->gr_table; 321 + unsigned long pal = (pa & uv_hub_info->gpa_mask) >> UV_GAM_RANGE_SHFT; 322 + int i, num = uv_hub_info->gr_table_len; 323 + 324 + if (gr) { 325 + for (i = 0; i < num; i++, gr++) { 326 + if (pal < gr->limit) 327 + return gr; 328 + } 329 + } 330 + pr_crit("UV: GAM Range for 0x%lx not found at %p!\n", pa, gr); 331 + BUG(); 332 + } 333 + 334 + /* Return base address of node that contains global address */ 335 + static inline unsigned long uv_gam_range_base(unsigned long pa) 336 + { 337 + struct uv_gam_range_s *gr = uv_gam_range(pa); 338 + int base = gr->base; 339 + 340 + if (base < 0) 341 + return 0UL; 342 + 343 + return uv_hub_info->gr_table[base].limit; 344 + } 345 + 346 + /* socket phys RAM --> UV global NASID (UV4+) */ 347 + static inline unsigned long uv_soc_phys_ram_to_nasid(unsigned long paddr) 348 + { 349 + return uv_gam_range(paddr)->nasid; 350 + } 351 + #define _uv_soc_phys_ram_to_nasid 352 + 353 + /* socket virtual --> UV global NASID (UV4+) */ 354 + static inline unsigned long uv_gpa_nasid(void *v) 355 + { 356 + return uv_soc_phys_ram_to_nasid(__pa(v)); 357 + } 358 + 432 359 /* socket phys RAM --> UV global physical address */ 433 360 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 434 361 { 362 + unsigned int m_val = uv_hub_info->m_val; 363 + 435 364 if (paddr < uv_hub_info->lowmem_remap_top) 436 365 paddr |= uv_hub_info->lowmem_remap_base; 437 366 paddr |= uv_hub_info->gnode_upper; 438 - paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 439 - ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift); 367 + if (m_val) 368 + paddr = ((paddr << uv_hub_info->m_shift) 369 + >> uv_hub_info->m_shift) | 370 + ((paddr >> uv_hub_info->m_val) 371 + << uv_hub_info->n_lshift); 372 + else 373 + paddr |= uv_soc_phys_ram_to_nasid(paddr) 374 + << uv_hub_info->gpa_shift; 440 375 return paddr; 441 376 } 442 - 443 377 444 378 /* socket virtual --> UV global physical address */ 445 379 static inline unsigned long uv_gpa(void *v) ··· 516 338 unsigned long paddr; 517 339 unsigned long remap_base = uv_hub_info->lowmem_remap_base; 518 340 unsigned long remap_top = uv_hub_info->lowmem_remap_top; 341 + unsigned int m_val = uv_hub_info->m_val; 519 342 520 - gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 521 - ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); 343 + if (m_val) 344 + gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 345 + ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); 346 + 522 347 paddr = gpa & uv_hub_info->gpa_mask; 523 348 if (paddr >= remap_base && paddr < remap_base + remap_top) 524 349 paddr -= remap_base; 525 350 return paddr; 526 351 } 527 352 528 - 529 - /* gpa -> pnode */ 353 + /* gpa -> gnode */ 530 354 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) 531 355 { 532 - return gpa >> uv_hub_info->n_lshift; 356 + unsigned int n_lshift = uv_hub_info->n_lshift; 357 + 358 + if (n_lshift) 359 + return gpa >> n_lshift; 360 + 361 + return uv_gam_range(gpa)->nasid >> 1; 533 362 } 534 363 535 364 /* gpa -> pnode */ 536 365 static inline int uv_gpa_to_pnode(unsigned long gpa) 537 366 { 538 - unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1; 539 - 540 - return uv_gpa_to_gnode(gpa) & n_mask; 367 + return uv_gpa_to_gnode(gpa) & uv_hub_info->pnode_mask; 541 368 } 542 369 543 - /* gpa -> node offset*/ 370 + /* gpa -> node offset */ 544 371 static inline unsigned long uv_gpa_to_offset(unsigned long gpa) 545 372 { 546 - return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift; 373 + unsigned int m_shift = uv_hub_info->m_shift; 374 + 375 + if (m_shift) 376 + return (gpa << m_shift) >> m_shift; 377 + 378 + return (gpa & uv_hub_info->gpa_mask) - uv_gam_range_base(gpa); 379 + } 380 + 381 + /* Convert socket to node */ 382 + static inline int _uv_socket_to_node(int socket, unsigned short *s2nid) 383 + { 384 + return s2nid ? s2nid[socket - uv_hub_info->min_socket] : socket; 385 + } 386 + 387 + static inline int uv_socket_to_node(int socket) 388 + { 389 + return _uv_socket_to_node(socket, uv_hub_info->socket_to_node); 547 390 } 548 391 549 392 /* pnode, offset --> socket virtual */ 550 393 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 551 394 { 552 - return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); 395 + unsigned int m_val = uv_hub_info->m_val; 396 + unsigned long base; 397 + unsigned short sockid, node, *p2s; 398 + 399 + if (m_val) 400 + return __va(((unsigned long)pnode << m_val) | offset); 401 + 402 + p2s = uv_hub_info->pnode_to_socket; 403 + sockid = p2s ? p2s[pnode - uv_hub_info->min_pnode] : pnode; 404 + node = uv_socket_to_node(sockid); 405 + 406 + /* limit address of previous socket is our base, except node 0 is 0 */ 407 + if (!node) 408 + return __va((unsigned long)offset); 409 + 410 + base = (unsigned long)(uv_hub_info->gr_table[node - 1].limit); 411 + return __va(base << UV_GAM_RANGE_SHFT | offset); 553 412 } 554 413 555 - 556 - /* 557 - * Extract a PNODE from an APICID (full apicid, not processor subset) 558 - */ 414 + /* Extract/Convert a PNODE from an APICID (full apicid, not processor subset) */ 559 415 static inline int uv_apicid_to_pnode(int apicid) 560 416 { 561 - return (apicid >> uv_hub_info->apic_pnode_shift); 417 + int pnode = apicid >> uv_hub_info->apic_pnode_shift; 418 + unsigned short *s2pn = uv_hub_info->socket_to_pnode; 419 + 420 + return s2pn ? s2pn[pnode - uv_hub_info->min_socket] : pnode; 562 421 } 563 422 564 - /* 565 - * Convert an apicid to the socket number on the blade 566 - */ 423 + /* Convert an apicid to the socket number on the blade */ 567 424 static inline int uv_apicid_to_socket(int apicid) 568 425 { 569 426 if (is_uv1_hub()) ··· 647 434 return readq(uv_global_mmr64_address(pnode, offset)); 648 435 } 649 436 650 - /* 651 - * Global MMR space addresses when referenced by the GRU. (GRU does 652 - * NOT use socket addressing). 653 - */ 654 - static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset) 655 - { 656 - return UV_GLOBAL_GRU_MMR_BASE | offset | 657 - ((unsigned long)pnode << uv_hub_info->m_val); 658 - } 659 - 660 437 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) 661 438 { 662 439 writeb(val, uv_global_mmr64_address(pnode, offset)); ··· 686 483 writeb(val, uv_local_mmr_address(offset)); 687 484 } 688 485 689 - /* 690 - * Structures and definitions for converting between cpu, node, pnode, and blade 691 - * numbers. 692 - */ 693 - struct uv_blade_info { 694 - unsigned short nr_possible_cpus; 695 - unsigned short nr_online_cpus; 696 - unsigned short pnode; 697 - short memory_nid; 698 - spinlock_t nmi_lock; /* obsolete, see uv_hub_nmi */ 699 - unsigned long nmi_count; /* obsolete, see uv_hub_nmi */ 700 - }; 701 - extern struct uv_blade_info *uv_blade_info; 702 - extern short *uv_node_to_blade; 703 - extern short *uv_cpu_to_blade; 704 - extern short uv_possible_blades; 705 - 706 486 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 707 487 static inline int uv_blade_processor_id(void) 708 488 { 709 - return uv_hub_info->blade_processor_id; 489 + return uv_cpu_info->blade_cpu_id; 490 + } 491 + 492 + /* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */ 493 + static inline int uv_cpu_blade_processor_id(int cpu) 494 + { 495 + return uv_cpu_info_per(cpu)->blade_cpu_id; 496 + } 497 + #define _uv_cpu_blade_processor_id 1 /* indicate function available */ 498 + 499 + /* Blade number to Node number (UV1..UV4 is 1:1) */ 500 + static inline int uv_blade_to_node(int blade) 501 + { 502 + return blade; 710 503 } 711 504 712 505 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ ··· 711 512 return uv_hub_info->numa_blade_id; 712 513 } 713 514 515 + /* 516 + * Convert linux node number to the UV blade number. 517 + * .. Currently for UV1 thru UV4 the node and the blade are identical. 518 + * .. If this changes then you MUST check references to this function! 519 + */ 520 + static inline int uv_node_to_blade_id(int nid) 521 + { 522 + return nid; 523 + } 524 + 714 525 /* Convert a cpu number to the the UV blade number */ 715 526 static inline int uv_cpu_to_blade_id(int cpu) 716 527 { 717 - return uv_cpu_to_blade[cpu]; 718 - } 719 - 720 - /* Convert linux node number to the UV blade number */ 721 - static inline int uv_node_to_blade_id(int nid) 722 - { 723 - return uv_node_to_blade[nid]; 528 + return uv_node_to_blade_id(cpu_to_node(cpu)); 724 529 } 725 530 726 531 /* Convert a blade id to the PNODE of the blade */ 727 532 static inline int uv_blade_to_pnode(int bid) 728 533 { 729 - return uv_blade_info[bid].pnode; 534 + return uv_hub_info_list(uv_blade_to_node(bid))->pnode; 730 535 } 731 536 732 537 /* Nid of memory node on blade. -1 if no blade-local memory */ 733 538 static inline int uv_blade_to_memory_nid(int bid) 734 539 { 735 - return uv_blade_info[bid].memory_nid; 540 + return uv_hub_info_list(uv_blade_to_node(bid))->memory_nid; 736 541 } 737 542 738 543 /* Determine the number of possible cpus on a blade */ 739 544 static inline int uv_blade_nr_possible_cpus(int bid) 740 545 { 741 - return uv_blade_info[bid].nr_possible_cpus; 546 + return uv_hub_info_list(uv_blade_to_node(bid))->nr_possible_cpus; 742 547 } 743 548 744 549 /* Determine the number of online cpus on a blade */ 745 550 static inline int uv_blade_nr_online_cpus(int bid) 746 551 { 747 - return uv_blade_info[bid].nr_online_cpus; 552 + return uv_hub_info_list(uv_blade_to_node(bid))->nr_online_cpus; 748 553 } 749 554 750 555 /* Convert a cpu id to the PNODE of the blade containing the cpu */ 751 556 static inline int uv_cpu_to_pnode(int cpu) 752 557 { 753 - return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; 558 + return uv_cpu_hub_info(cpu)->pnode; 754 559 } 755 560 756 561 /* Convert a linux node number to the PNODE of the blade */ 757 562 static inline int uv_node_to_pnode(int nid) 758 563 { 759 - return uv_blade_info[uv_node_to_blade_id(nid)].pnode; 564 + return uv_hub_info_list(nid)->pnode; 760 565 } 761 566 762 567 /* Maximum possible number of blades */ 568 + extern short uv_possible_blades; 763 569 static inline int uv_num_possible_blades(void) 764 570 { 765 571 return uv_possible_blades; ··· 782 578 /* Newer SMM NMI handler, not present in all systems */ 783 579 #define UVH_NMI_MMRX UVH_EVENT_OCCURRED0 784 580 #define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS 785 - #define UVH_NMI_MMRX_SHIFT (is_uv1_hub() ? \ 786 - UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :\ 787 - UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT) 581 + #define UVH_NMI_MMRX_SHIFT UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 788 582 #define UVH_NMI_MMRX_TYPE "EXTIO_INT0" 789 583 790 584 /* Non-zero indicates newer SMM NMI handler present */ ··· 824 622 /* Update SCIR state */ 825 623 static inline void uv_set_scir_bits(unsigned char value) 826 624 { 827 - if (uv_hub_info->scir.state != value) { 828 - uv_hub_info->scir.state = value; 829 - uv_write_local_mmr8(uv_hub_info->scir.offset, value); 625 + if (uv_scir_info->state != value) { 626 + uv_scir_info->state = value; 627 + uv_write_local_mmr8(uv_scir_info->offset, value); 830 628 } 831 629 } 832 630 ··· 837 635 838 636 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 839 637 { 840 - if (uv_cpu_hub_info(cpu)->scir.state != value) { 638 + if (uv_cpu_scir_info(cpu)->state != value) { 841 639 uv_write_global_mmr8(uv_cpu_to_pnode(cpu), 842 - uv_cpu_hub_info(cpu)->scir.offset, value); 843 - uv_cpu_hub_info(cpu)->scir.state = value; 640 + uv_cpu_scir_info(cpu)->offset, value); 641 + uv_cpu_scir_info(cpu)->state = value; 844 642 } 845 643 } 846 644 ··· 868 666 869 667 /* 870 668 * Get the minimum revision number of the hub chips within the partition. 871 - * 1 - UV1 rev 1.0 initial silicon 872 - * 2 - UV1 rev 2.0 production silicon 873 - * 3 - UV2 rev 1.0 initial silicon 874 - * 5 - UV3 rev 1.0 initial silicon 669 + * (See UVx_HUB_REVISION_BASE above for specific values.) 875 670 */ 876 671 static inline int uv_get_min_hub_revision_id(void) 877 672 {
+1780 -423
arch/x86/include/asm/uv/uv_mmrs.h
··· 5 5 * 6 6 * SGI UV MMR definitions 7 7 * 8 - * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 8 + * Copyright (C) 2007-2016 Silicon Graphics, Inc. All rights reserved. 9 9 */ 10 10 11 11 #ifndef _ASM_X86_UV_UV_MMRS_H ··· 18 18 * grouped by architecture types. 19 19 * 20 20 * UVH - definitions common to all UV hub types. 21 - * UVXH - definitions common to all UV eXtended hub types (currently 2 & 3). 21 + * UVXH - definitions common to all UV eXtended hub types (currently 2, 3, 4). 22 22 * UV1H - definitions specific to UV type 1 hub. 23 23 * UV2H - definitions specific to UV type 2 hub. 24 24 * UV3H - definitions specific to UV type 3 hub. 25 + * UV4H - definitions specific to UV type 4 hub. 25 26 * 26 27 * So in general, MMR addresses and structures are identical on all hubs types. 27 28 * These MMRs are identified as: ··· 33 32 * } s; 34 33 * }; 35 34 * 36 - * If the MMR exists on all hub types but have different addresses: 35 + * If the MMR exists on all hub types but have different addresses, 36 + * use a conditional operator to define the value at runtime. 37 37 * #define UV1Hxxx a 38 38 * #define UV2Hxxx b 39 39 * #define UV3Hxxx c 40 + * #define UV4Hxxx d 40 41 * #define UVHxxx (is_uv1_hub() ? UV1Hxxx : 41 42 * (is_uv2_hub() ? UV2Hxxx : 42 - * UV3Hxxx)) 43 + * (is_uv3_hub() ? UV3Hxxx : 44 + * UV4Hxxx)) 43 45 * 44 - * If the MMR exists on all hub types > 1 but have different addresses: 46 + * If the MMR exists on all hub types > 1 but have different addresses, the 47 + * variation using "UVX" as the prefix exists. 45 48 * #define UV2Hxxx b 46 49 * #define UV3Hxxx c 47 - * #define UVXHxxx (is_uv2_hub() ? UV2Hxxx : 48 - * UV3Hxxx)) 50 + * #define UV4Hxxx d 51 + * #define UVHxxx (is_uv2_hub() ? UV2Hxxx : 52 + * (is_uv3_hub() ? UV3Hxxx : 53 + * UV4Hxxx)) 49 54 * 50 55 * union uvh_xxx { 51 56 * unsigned long v; ··· 63 56 * } s2; 64 57 * struct uv3h_xxx_s { # Full UV3 definition (*) 65 58 * } s3; 59 + * struct uv4h_xxx_s { # Full UV4 definition (*) 60 + * } s4; 66 61 * }; 67 62 * (* - if present and different than the common struct) 68 63 * ··· 82 73 * } sn; 83 74 * }; 84 75 * 85 - * (GEN Flags: mflags_opt= undefs=0 UV23=UVXH) 76 + * (GEN Flags: mflags_opt= undefs=function UV234=UVXH) 86 77 */ 87 78 88 79 #define UV_MMR_ENABLE (1UL << 63) ··· 92 83 #define UV2_HUB_PART_NUMBER_X 0x1111 93 84 #define UV3_HUB_PART_NUMBER 0x9578 94 85 #define UV3_HUB_PART_NUMBER_X 0x4321 86 + #define UV4_HUB_PART_NUMBER 0x99a1 95 87 96 88 /* Compat: Indicate which UV Hubs are supported. */ 89 + #define UV1_HUB_IS_SUPPORTED 1 97 90 #define UV2_HUB_IS_SUPPORTED 1 98 91 #define UV3_HUB_IS_SUPPORTED 1 92 + #define UV4_HUB_IS_SUPPORTED 1 93 + 94 + /* Error function to catch undefined references */ 95 + extern unsigned long uv_undefined(char *str); 99 96 100 97 /* ========================================================================= */ 101 98 /* UVH_BAU_DATA_BROADCAST */ 102 99 /* ========================================================================= */ 103 100 #define UVH_BAU_DATA_BROADCAST 0x61688UL 104 - #define UVH_BAU_DATA_BROADCAST_32 0x440 101 + 102 + #define UV1H_BAU_DATA_BROADCAST_32 0x440 103 + #define UV2H_BAU_DATA_BROADCAST_32 0x440 104 + #define UV3H_BAU_DATA_BROADCAST_32 0x440 105 + #define UV4H_BAU_DATA_BROADCAST_32 0x360 106 + #define UVH_BAU_DATA_BROADCAST_32 ( \ 107 + is_uv1_hub() ? UV1H_BAU_DATA_BROADCAST_32 : \ 108 + is_uv2_hub() ? UV2H_BAU_DATA_BROADCAST_32 : \ 109 + is_uv3_hub() ? UV3H_BAU_DATA_BROADCAST_32 : \ 110 + /*is_uv4_hub*/ UV4H_BAU_DATA_BROADCAST_32) 105 111 106 112 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 107 113 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL 114 + 108 115 109 116 union uvh_bau_data_broadcast_u { 110 117 unsigned long v; ··· 134 109 /* UVH_BAU_DATA_CONFIG */ 135 110 /* ========================================================================= */ 136 111 #define UVH_BAU_DATA_CONFIG 0x61680UL 137 - #define UVH_BAU_DATA_CONFIG_32 0x438 112 + 113 + #define UV1H_BAU_DATA_CONFIG_32 0x438 114 + #define UV2H_BAU_DATA_CONFIG_32 0x438 115 + #define UV3H_BAU_DATA_CONFIG_32 0x438 116 + #define UV4H_BAU_DATA_CONFIG_32 0x358 117 + #define UVH_BAU_DATA_CONFIG_32 ( \ 118 + is_uv1_hub() ? UV1H_BAU_DATA_CONFIG_32 : \ 119 + is_uv2_hub() ? UV2H_BAU_DATA_CONFIG_32 : \ 120 + is_uv3_hub() ? UV3H_BAU_DATA_CONFIG_32 : \ 121 + /*is_uv4_hub*/ UV4H_BAU_DATA_CONFIG_32) 138 122 139 123 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 140 124 #define UVH_BAU_DATA_CONFIG_DM_SHFT 8 ··· 161 127 #define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL 162 128 #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL 163 129 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 130 + 164 131 165 132 union uvh_bau_data_config_u { 166 133 unsigned long v; ··· 301 266 #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL 302 267 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL 303 268 304 - #define UVXH_EVENT_OCCURRED0_QP_HCERR_SHFT 1 305 269 #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT 2 306 270 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 307 271 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT 4 ··· 309 275 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT 7 310 276 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 311 277 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 312 - #define UVXH_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 313 278 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 314 279 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 315 280 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 316 281 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15 317 282 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT 16 318 - #define UVXH_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 319 - #define UVXH_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 320 - #define UVXH_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 321 - #define UVXH_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 322 - #define UVXH_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 323 - #define UVXH_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 324 - #define UVXH_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 325 - #define UVXH_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 326 - #define UVXH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 327 - #define UVXH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 328 - #define UVXH_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 329 - #define UVXH_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 330 - #define UVXH_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 331 - #define UVXH_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 332 - #define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 333 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 334 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 335 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 336 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 337 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 338 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 339 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 340 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 341 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 342 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 343 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 344 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 345 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 346 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 347 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 348 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 349 - #define UVXH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 350 - #define UVXH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 351 - #define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 352 - #define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 353 - #define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 354 - #define UVXH_EVENT_OCCURRED0_IPI_INT_SHFT 53 355 - #define UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 356 - #define UVXH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 357 - #define UVXH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 358 - #define UVXH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 359 - #define UVXH_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 360 - #define UVXH_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 361 283 #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL 362 284 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL 363 285 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL ··· 322 332 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL 323 333 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL 324 334 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL 325 - #define UVXH_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 326 335 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL 327 336 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL 328 337 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL 329 338 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL 330 339 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL 331 - #define UVXH_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 332 - #define UVXH_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 333 - #define UVXH_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 334 - #define UVXH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 335 - #define UVXH_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 336 - #define UVXH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 337 - #define UVXH_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 338 - #define UVXH_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 339 - #define UVXH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 340 - #define UVXH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 341 - #define UVXH_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 342 - #define UVXH_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 343 - #define UVXH_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 344 - #define UVXH_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 345 - #define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 346 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 347 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 348 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 349 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 350 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 351 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 352 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 353 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 354 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 355 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 356 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 357 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 358 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 359 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 360 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 361 - #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 362 - #define UVXH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 363 - #define UVXH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 364 - #define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 365 - #define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 366 - #define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 367 - #define UVXH_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 368 - #define UVXH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 369 - #define UVXH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 370 - #define UVXH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 371 - #define UVXH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 372 - #define UVXH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 340 + 341 + #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 342 + #define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 343 + #define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 344 + #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 345 + #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 346 + #define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 347 + #define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 348 + #define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 349 + #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 350 + #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 351 + #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 352 + #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 353 + #define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 354 + #define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 355 + #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 356 + #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 357 + #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 358 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 359 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 360 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 361 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 362 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 363 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 364 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 365 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 366 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 367 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 368 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 369 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 370 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 371 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 372 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 373 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 374 + #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 375 + #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 376 + #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 377 + #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 378 + #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 379 + #define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53 380 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 381 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 382 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 383 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 384 + #define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 385 + #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 386 + #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 387 + #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 388 + #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 389 + #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 390 + #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 391 + #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 392 + #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 393 + #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 394 + #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 395 + #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 396 + #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 397 + #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 398 + #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 399 + #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 400 + #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 401 + #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 402 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 403 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 404 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 405 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 406 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 407 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 408 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 409 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 410 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 411 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 412 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 413 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 414 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 415 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 416 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 417 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 418 + #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 419 + #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 420 + #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 421 + #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 422 + #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 423 + #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 424 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 425 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 426 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 427 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 428 + #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 429 + 430 + #define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 431 + #define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 432 + #define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 433 + #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 434 + #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 435 + #define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 436 + #define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 437 + #define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 438 + #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 439 + #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 440 + #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 441 + #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 442 + #define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 443 + #define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 444 + #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 445 + #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 446 + #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 447 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 448 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 449 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 450 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 451 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 452 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 453 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 454 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 455 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 456 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 457 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 458 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 459 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 460 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 461 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 462 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 463 + #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 464 + #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 465 + #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 466 + #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 467 + #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 468 + #define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT 53 469 + #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 470 + #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 471 + #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 472 + #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 473 + #define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 474 + #define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 475 + #define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 476 + #define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 477 + #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 478 + #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 479 + #define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 480 + #define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 481 + #define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 482 + #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 483 + #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 484 + #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 485 + #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 486 + #define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 487 + #define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 488 + #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 489 + #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 490 + #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 491 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 492 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 493 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 494 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 495 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 496 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 497 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 498 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 499 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 500 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 501 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 502 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 503 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 504 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 505 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 506 + #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 507 + #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 508 + #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 509 + #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 510 + #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 511 + #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 512 + #define UV3H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 513 + #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 514 + #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 515 + #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 516 + #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 517 + #define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 518 + 519 + #define UV4H_EVENT_OCCURRED0_KT_HCERR_SHFT 1 520 + #define UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT 10 521 + #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT 17 522 + #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT 18 523 + #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT 19 524 + #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT 20 525 + #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 21 526 + #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 22 527 + #define UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT 23 528 + #define UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT 24 529 + #define UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT 25 530 + #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 26 531 + #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 27 532 + #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 28 533 + #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 29 534 + #define UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT 30 535 + #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT 31 536 + #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT 32 537 + #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT 33 538 + #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT 34 539 + #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 35 540 + #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 36 541 + #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 37 542 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 38 543 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 39 544 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 40 545 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 41 546 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 42 547 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 43 548 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 44 549 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 45 550 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 46 551 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 47 552 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 48 553 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 49 554 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 50 555 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 51 556 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 52 557 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 53 558 + #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 54 559 + #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 55 560 + #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 56 561 + #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 57 562 + #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 58 563 + #define UV4H_EVENT_OCCURRED0_IPI_INT_SHFT 59 564 + #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 60 565 + #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 61 566 + #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 62 567 + #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 63 568 + #define UV4H_EVENT_OCCURRED0_KT_HCERR_MASK 0x0000000000000002UL 569 + #define UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK 0x0000000000000400UL 570 + #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK 0x0000000000020000UL 571 + #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK 0x0000000000040000UL 572 + #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK 0x0000000000080000UL 573 + #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK 0x0000000000100000UL 574 + #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000200000UL 575 + #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000400000UL 576 + #define UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000800000UL 577 + #define UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK 0x0000000001000000UL 578 + #define UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000002000000UL 579 + #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000004000000UL 580 + #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000008000000UL 581 + #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000010000000UL 582 + #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000020000000UL 583 + #define UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000040000000UL 584 + #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK 0x0000000080000000UL 585 + #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK 0x0000000100000000UL 586 + #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK 0x0000000200000000UL 587 + #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK 0x0000000400000000UL 588 + #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000800000000UL 589 + #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000001000000000UL 590 + #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000002000000000UL 591 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000004000000000UL 592 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000008000000000UL 593 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000010000000000UL 594 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000020000000000UL 595 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000040000000000UL 596 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000080000000000UL 597 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000100000000000UL 598 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000200000000000UL 599 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000400000000000UL 600 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000800000000000UL 601 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0001000000000000UL 602 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0002000000000000UL 603 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0004000000000000UL 604 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0008000000000000UL 605 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0010000000000000UL 606 + #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0020000000000000UL 607 + #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0040000000000000UL 608 + #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0080000000000000UL 609 + #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0100000000000000UL 610 + #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0200000000000000UL 611 + #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0400000000000000UL 612 + #define UV4H_EVENT_OCCURRED0_IPI_INT_MASK 0x0800000000000000UL 613 + #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x1000000000000000UL 614 + #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x2000000000000000UL 615 + #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x4000000000000000UL 616 + #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x8000000000000000UL 617 + 618 + #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT ( \ 619 + is_uv1_hub() ? UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \ 620 + is_uv2_hub() ? UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \ 621 + is_uv3_hub() ? UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \ 622 + /*is_uv4_hub*/ UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT) 373 623 374 624 union uvh_event_occurred0_u { 375 625 unsigned long v; ··· 621 391 } s; 622 392 struct uvxh_event_occurred0_s { 623 393 unsigned long lb_hcerr:1; /* RW */ 624 - unsigned long qp_hcerr:1; /* RW */ 394 + unsigned long rsvd_1:1; 625 395 unsigned long rh_hcerr:1; /* RW */ 626 396 unsigned long lh0_hcerr:1; /* RW */ 627 397 unsigned long lh1_hcerr:1; /* RW */ ··· 630 400 unsigned long ni0_hcerr:1; /* RW */ 631 401 unsigned long ni1_hcerr:1; /* RW */ 632 402 unsigned long lb_aoerr0:1; /* RW */ 633 - unsigned long qp_aoerr0:1; /* RW */ 403 + unsigned long rsvd_10:1; 634 404 unsigned long rh_aoerr0:1; /* RW */ 635 405 unsigned long lh0_aoerr0:1; /* RW */ 636 406 unsigned long lh1_aoerr0:1; /* RW */ 637 407 unsigned long gr0_aoerr0:1; /* RW */ 638 408 unsigned long gr1_aoerr0:1; /* RW */ 639 409 unsigned long xb_aoerr0:1; /* RW */ 640 - unsigned long rt_aoerr0:1; /* RW */ 410 + unsigned long rsvd_17_63:47; 411 + } sx; 412 + struct uv4h_event_occurred0_s { 413 + unsigned long lb_hcerr:1; /* RW */ 414 + unsigned long kt_hcerr:1; /* RW */ 415 + unsigned long rh_hcerr:1; /* RW */ 416 + unsigned long lh0_hcerr:1; /* RW */ 417 + unsigned long lh1_hcerr:1; /* RW */ 418 + unsigned long gr0_hcerr:1; /* RW */ 419 + unsigned long gr1_hcerr:1; /* RW */ 420 + unsigned long ni0_hcerr:1; /* RW */ 421 + unsigned long ni1_hcerr:1; /* RW */ 422 + unsigned long lb_aoerr0:1; /* RW */ 423 + unsigned long kt_aoerr0:1; /* RW */ 424 + unsigned long rh_aoerr0:1; /* RW */ 425 + unsigned long lh0_aoerr0:1; /* RW */ 426 + unsigned long lh1_aoerr0:1; /* RW */ 427 + unsigned long gr0_aoerr0:1; /* RW */ 428 + unsigned long gr1_aoerr0:1; /* RW */ 429 + unsigned long xb_aoerr0:1; /* RW */ 430 + unsigned long rtq0_aoerr0:1; /* RW */ 431 + unsigned long rtq1_aoerr0:1; /* RW */ 432 + unsigned long rtq2_aoerr0:1; /* RW */ 433 + unsigned long rtq3_aoerr0:1; /* RW */ 641 434 unsigned long ni0_aoerr0:1; /* RW */ 642 435 unsigned long ni1_aoerr0:1; /* RW */ 643 436 unsigned long lb_aoerr1:1; /* RW */ 644 - unsigned long qp_aoerr1:1; /* RW */ 437 + unsigned long kt_aoerr1:1; /* RW */ 645 438 unsigned long rh_aoerr1:1; /* RW */ 646 439 unsigned long lh0_aoerr1:1; /* RW */ 647 440 unsigned long lh1_aoerr1:1; /* RW */ 648 441 unsigned long gr0_aoerr1:1; /* RW */ 649 442 unsigned long gr1_aoerr1:1; /* RW */ 650 443 unsigned long xb_aoerr1:1; /* RW */ 651 - unsigned long rt_aoerr1:1; /* RW */ 444 + unsigned long rtq0_aoerr1:1; /* RW */ 445 + unsigned long rtq1_aoerr1:1; /* RW */ 446 + unsigned long rtq2_aoerr1:1; /* RW */ 447 + unsigned long rtq3_aoerr1:1; /* RW */ 652 448 unsigned long ni0_aoerr1:1; /* RW */ 653 449 unsigned long ni1_aoerr1:1; /* RW */ 654 450 unsigned long system_shutdown_int:1; /* RW */ ··· 704 448 unsigned long extio_int1:1; /* RW */ 705 449 unsigned long extio_int2:1; /* RW */ 706 450 unsigned long extio_int3:1; /* RW */ 707 - unsigned long profile_int:1; /* RW */ 708 - unsigned long rsvd_59_63:5; 709 - } sx; 451 + } s4; 710 452 }; 711 453 712 454 /* ========================================================================= */ ··· 718 464 /* UVH_EXTIO_INT0_BROADCAST */ 719 465 /* ========================================================================= */ 720 466 #define UVH_EXTIO_INT0_BROADCAST 0x61448UL 721 - #define UVH_EXTIO_INT0_BROADCAST_32 0x3f0 467 + 468 + #define UV1H_EXTIO_INT0_BROADCAST_32 0x3f0 469 + #define UV2H_EXTIO_INT0_BROADCAST_32 0x3f0 470 + #define UV3H_EXTIO_INT0_BROADCAST_32 0x3f0 471 + #define UV4H_EXTIO_INT0_BROADCAST_32 0x310 472 + #define UVH_EXTIO_INT0_BROADCAST_32 ( \ 473 + is_uv1_hub() ? UV1H_EXTIO_INT0_BROADCAST_32 : \ 474 + is_uv2_hub() ? UV2H_EXTIO_INT0_BROADCAST_32 : \ 475 + is_uv3_hub() ? UV3H_EXTIO_INT0_BROADCAST_32 : \ 476 + /*is_uv4_hub*/ UV4H_EXTIO_INT0_BROADCAST_32) 722 477 723 478 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT 0 724 479 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK 0x0000000000000001UL 480 + 725 481 726 482 union uvh_extio_int0_broadcast_u { 727 483 unsigned long v; ··· 762 498 #define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 763 499 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 764 500 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 501 + 765 502 766 503 union uvh_gr0_tlb_int0_config_u { 767 504 unsigned long v; ··· 802 537 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 803 538 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 804 539 540 + 805 541 union uvh_gr0_tlb_int1_config_u { 806 542 unsigned long v; 807 543 struct uvh_gr0_tlb_int1_config_s { ··· 825 559 #define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL 826 560 #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL 827 561 #define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL 828 - #define UVH_GR0_TLB_MMR_CONTROL \ 829 - (is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL : \ 830 - (is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL : \ 831 - UV3H_GR0_TLB_MMR_CONTROL)) 562 + #define UV4H_GR0_TLB_MMR_CONTROL 0x601080UL 563 + #define UVH_GR0_TLB_MMR_CONTROL ( \ 564 + is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL : \ 565 + is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL : \ 566 + is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL : \ 567 + /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL) 832 568 833 569 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 834 - #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 835 570 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 836 571 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 837 572 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 838 573 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 839 - #define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 840 - #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 841 574 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 842 575 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 843 576 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL ··· 866 601 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL 867 602 868 603 #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 869 - #define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 870 604 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 871 605 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 872 606 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 873 607 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 874 608 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 875 - #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 876 - #define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 877 609 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 878 610 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 879 611 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL ··· 913 651 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 914 652 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 915 653 654 + #define UV4H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 655 + #define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 13 656 + #define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 657 + #define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 658 + #define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 659 + #define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 660 + #define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 661 + #define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 662 + #define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_SHFT 59 663 + #define UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000001fffUL 664 + #define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000006000UL 665 + #define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 666 + #define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 667 + #define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 668 + #define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 669 + #define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 670 + #define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 671 + #define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_MASK 0xf800000000000000UL 672 + 673 + #define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK ( \ 674 + is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \ 675 + is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \ 676 + is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \ 677 + /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK) 678 + #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK ( \ 679 + is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \ 680 + is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \ 681 + is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \ 682 + /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK) 683 + #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT ( \ 684 + is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \ 685 + is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \ 686 + is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \ 687 + /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT) 688 + 916 689 union uvh_gr0_tlb_mmr_control_u { 917 690 unsigned long v; 918 691 struct uvh_gr0_tlb_mmr_control_s { 919 - unsigned long index:12; /* RW */ 920 - unsigned long mem_sel:2; /* RW */ 921 - unsigned long rsvd_14_15:2; 692 + unsigned long rsvd_0_15:16; 922 693 unsigned long auto_valid_en:1; /* RW */ 923 694 unsigned long rsvd_17_19:3; 924 695 unsigned long mmr_hash_index_en:1; /* RW */ ··· 985 690 unsigned long rsvd_61_63:3; 986 691 } s1; 987 692 struct uvxh_gr0_tlb_mmr_control_s { 988 - unsigned long index:12; /* RW */ 989 - unsigned long mem_sel:2; /* RW */ 990 - unsigned long rsvd_14_15:2; 693 + unsigned long rsvd_0_15:16; 991 694 unsigned long auto_valid_en:1; /* RW */ 992 695 unsigned long rsvd_17_19:3; 993 696 unsigned long mmr_hash_index_en:1; /* RW */ ··· 996 703 unsigned long rsvd_33_47:15; 997 704 unsigned long rsvd_48:1; 998 705 unsigned long rsvd_49_51:3; 999 - unsigned long rsvd_52:1; 1000 - unsigned long rsvd_53_63:11; 706 + unsigned long rsvd_52_63:12; 1001 707 } sx; 1002 708 struct uv2h_gr0_tlb_mmr_control_s { 1003 709 unsigned long index:12; /* RW */ ··· 1033 741 unsigned long undef_52:1; /* Undefined */ 1034 742 unsigned long rsvd_53_63:11; 1035 743 } s3; 744 + struct uv4h_gr0_tlb_mmr_control_s { 745 + unsigned long index:13; /* RW */ 746 + unsigned long mem_sel:2; /* RW */ 747 + unsigned long rsvd_15:1; 748 + unsigned long auto_valid_en:1; /* RW */ 749 + unsigned long rsvd_17_19:3; 750 + unsigned long mmr_hash_index_en:1; /* RW */ 751 + unsigned long ecc_sel:1; /* RW */ 752 + unsigned long rsvd_22_29:8; 753 + unsigned long mmr_write:1; /* WP */ 754 + unsigned long mmr_read:1; /* WP */ 755 + unsigned long mmr_op_done:1; /* RW */ 756 + unsigned long rsvd_33_47:15; 757 + unsigned long undef_48:1; /* Undefined */ 758 + unsigned long rsvd_49_51:3; 759 + unsigned long rsvd_52_58:7; 760 + unsigned long page_size:5; /* RW */ 761 + } s4; 1036 762 }; 1037 763 1038 764 /* ========================================================================= */ ··· 1059 749 #define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL 1060 750 #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL 1061 751 #define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL 1062 - #define UVH_GR0_TLB_MMR_READ_DATA_HI \ 1063 - (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI : \ 1064 - (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI : \ 1065 - UV3H_GR0_TLB_MMR_READ_DATA_HI)) 752 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI 0x6010a0UL 753 + #define UVH_GR0_TLB_MMR_READ_DATA_HI ( \ 754 + is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI : \ 755 + is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI : \ 756 + is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_HI : \ 757 + /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_HI) 1066 758 1067 759 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1068 - #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1069 - #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1070 - #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1071 - #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1072 - #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1073 - #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1074 - #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1075 760 1076 761 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1077 762 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 ··· 1078 773 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1079 774 1080 775 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1081 - #define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1082 - #define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1083 - #define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1084 - #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1085 - #define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1086 - #define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1087 - #define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1088 776 1089 777 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1090 778 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 ··· 1101 803 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL 1102 804 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1103 805 806 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 807 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_SHFT 34 808 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 49 809 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 51 810 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 52 811 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 53 812 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 813 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x00000003ffffffffUL 814 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_MASK 0x0001fffc00000000UL 815 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0006000000000000UL 816 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0008000000000000UL 817 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0010000000000000UL 818 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0020000000000000UL 819 + #define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 820 + 821 + 1104 822 union uvh_gr0_tlb_mmr_read_data_hi_u { 1105 823 unsigned long v; 1106 - struct uvh_gr0_tlb_mmr_read_data_hi_s { 1107 - unsigned long pfn:41; /* RO */ 1108 - unsigned long gaa:2; /* RO */ 1109 - unsigned long dirty:1; /* RO */ 1110 - unsigned long larger:1; /* RO */ 1111 - unsigned long rsvd_45_63:19; 1112 - } s; 1113 824 struct uv1h_gr0_tlb_mmr_read_data_hi_s { 1114 825 unsigned long pfn:41; /* RO */ 1115 826 unsigned long gaa:2; /* RO */ ··· 1126 819 unsigned long larger:1; /* RO */ 1127 820 unsigned long rsvd_45_63:19; 1128 821 } s1; 1129 - struct uvxh_gr0_tlb_mmr_read_data_hi_s { 1130 - unsigned long pfn:41; /* RO */ 1131 - unsigned long gaa:2; /* RO */ 1132 - unsigned long dirty:1; /* RO */ 1133 - unsigned long larger:1; /* RO */ 1134 - unsigned long rsvd_45_63:19; 1135 - } sx; 1136 822 struct uv2h_gr0_tlb_mmr_read_data_hi_s { 1137 823 unsigned long pfn:41; /* RO */ 1138 824 unsigned long gaa:2; /* RO */ ··· 1142 842 unsigned long undef_46_54:9; /* Undefined */ 1143 843 unsigned long way_ecc:9; /* RO */ 1144 844 } s3; 845 + struct uv4h_gr0_tlb_mmr_read_data_hi_s { 846 + unsigned long pfn:34; /* RO */ 847 + unsigned long pnid:15; /* RO */ 848 + unsigned long gaa:2; /* RO */ 849 + unsigned long dirty:1; /* RO */ 850 + unsigned long larger:1; /* RO */ 851 + unsigned long aa_ext:1; /* RO */ 852 + unsigned long undef_54:1; /* Undefined */ 853 + unsigned long way_ecc:9; /* RO */ 854 + } s4; 1145 855 }; 1146 856 1147 857 /* ========================================================================= */ ··· 1160 850 #define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL 1161 851 #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL 1162 852 #define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL 1163 - #define UVH_GR0_TLB_MMR_READ_DATA_LO \ 1164 - (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO : \ 1165 - (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO : \ 1166 - UV3H_GR0_TLB_MMR_READ_DATA_LO)) 853 + #define UV4H_GR0_TLB_MMR_READ_DATA_LO 0x6010a8UL 854 + #define UVH_GR0_TLB_MMR_READ_DATA_LO ( \ 855 + is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO : \ 856 + is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO : \ 857 + is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_LO : \ 858 + /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_LO) 1167 859 1168 860 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1169 861 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 ··· 1202 890 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1203 891 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1204 892 893 + #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 894 + #define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 895 + #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 896 + #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 897 + #define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 898 + #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 899 + 900 + 1205 901 union uvh_gr0_tlb_mmr_read_data_lo_u { 1206 902 unsigned long v; 1207 903 struct uvh_gr0_tlb_mmr_read_data_lo_s { ··· 1237 917 unsigned long asid:24; /* RO */ 1238 918 unsigned long valid:1; /* RO */ 1239 919 } s3; 920 + struct uv4h_gr0_tlb_mmr_read_data_lo_s { 921 + unsigned long vpn:39; /* RO */ 922 + unsigned long asid:24; /* RO */ 923 + unsigned long valid:1; /* RO */ 924 + } s4; 1240 925 }; 1241 926 1242 927 /* ========================================================================= */ 1243 928 /* UVH_GR1_TLB_INT0_CONFIG */ 1244 929 /* ========================================================================= */ 1245 - #define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL 930 + #define UV1H_GR1_TLB_INT0_CONFIG 0x61f00UL 931 + #define UV2H_GR1_TLB_INT0_CONFIG 0x61f00UL 932 + #define UV3H_GR1_TLB_INT0_CONFIG 0x61f00UL 933 + #define UV4H_GR1_TLB_INT0_CONFIG 0x62100UL 934 + #define UVH_GR1_TLB_INT0_CONFIG ( \ 935 + is_uv1_hub() ? UV1H_GR1_TLB_INT0_CONFIG : \ 936 + is_uv2_hub() ? UV2H_GR1_TLB_INT0_CONFIG : \ 937 + is_uv3_hub() ? UV3H_GR1_TLB_INT0_CONFIG : \ 938 + /*is_uv4_hub*/ UV4H_GR1_TLB_INT0_CONFIG) 1246 939 1247 940 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 1248 941 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 ··· 1273 940 #define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 1274 941 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 1275 942 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 943 + 1276 944 1277 945 union uvh_gr1_tlb_int0_config_u { 1278 946 unsigned long v; ··· 1294 960 /* ========================================================================= */ 1295 961 /* UVH_GR1_TLB_INT1_CONFIG */ 1296 962 /* ========================================================================= */ 1297 - #define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL 963 + #define UV1H_GR1_TLB_INT1_CONFIG 0x61f40UL 964 + #define UV2H_GR1_TLB_INT1_CONFIG 0x61f40UL 965 + #define UV3H_GR1_TLB_INT1_CONFIG 0x61f40UL 966 + #define UV4H_GR1_TLB_INT1_CONFIG 0x62140UL 967 + #define UVH_GR1_TLB_INT1_CONFIG ( \ 968 + is_uv1_hub() ? UV1H_GR1_TLB_INT1_CONFIG : \ 969 + is_uv2_hub() ? UV2H_GR1_TLB_INT1_CONFIG : \ 970 + is_uv3_hub() ? UV3H_GR1_TLB_INT1_CONFIG : \ 971 + /*is_uv4_hub*/ UV4H_GR1_TLB_INT1_CONFIG) 1298 972 1299 973 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 1300 974 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 ··· 1320 978 #define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 1321 979 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 1322 980 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 981 + 1323 982 1324 983 union uvh_gr1_tlb_int1_config_u { 1325 984 unsigned long v; ··· 1344 1001 #define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL 1345 1002 #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL 1346 1003 #define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL 1347 - #define UVH_GR1_TLB_MMR_CONTROL \ 1348 - (is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL : \ 1349 - (is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL : \ 1350 - UV3H_GR1_TLB_MMR_CONTROL)) 1004 + #define UV4H_GR1_TLB_MMR_CONTROL 0x701080UL 1005 + #define UVH_GR1_TLB_MMR_CONTROL ( \ 1006 + is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL : \ 1007 + is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL : \ 1008 + is_uv3_hub() ? UV3H_GR1_TLB_MMR_CONTROL : \ 1009 + /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_CONTROL) 1351 1010 1352 1011 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1353 - #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1354 1012 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1355 1013 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1356 1014 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1357 1015 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1358 - #define UVH_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1359 - #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1360 1016 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1361 1017 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1362 1018 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL ··· 1385 1043 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL 1386 1044 1387 1045 #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1388 - #define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1389 1046 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1390 1047 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1391 1048 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1392 1049 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1393 1050 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1394 - #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1395 - #define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1396 1051 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1397 1052 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1398 1053 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL ··· 1432 1093 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1433 1094 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1434 1095 1096 + #define UV4H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1097 + #define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 13 1098 + #define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1099 + #define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1100 + #define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 1101 + #define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1102 + #define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1103 + #define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1104 + #define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_SHFT 59 1105 + #define UV4H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000001fffUL 1106 + #define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000006000UL 1107 + #define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1108 + #define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1109 + #define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 1110 + #define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1111 + #define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1112 + #define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1113 + #define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_MASK 0xf800000000000000UL 1114 + 1115 + 1435 1116 union uvh_gr1_tlb_mmr_control_u { 1436 1117 unsigned long v; 1437 1118 struct uvh_gr1_tlb_mmr_control_s { 1438 - unsigned long index:12; /* RW */ 1439 - unsigned long mem_sel:2; /* RW */ 1440 - unsigned long rsvd_14_15:2; 1119 + unsigned long rsvd_0_15:16; 1441 1120 unsigned long auto_valid_en:1; /* RW */ 1442 1121 unsigned long rsvd_17_19:3; 1443 1122 unsigned long mmr_hash_index_en:1; /* RW */ ··· 1489 1132 unsigned long rsvd_61_63:3; 1490 1133 } s1; 1491 1134 struct uvxh_gr1_tlb_mmr_control_s { 1492 - unsigned long index:12; /* RW */ 1493 - unsigned long mem_sel:2; /* RW */ 1494 - unsigned long rsvd_14_15:2; 1135 + unsigned long rsvd_0_15:16; 1495 1136 unsigned long auto_valid_en:1; /* RW */ 1496 1137 unsigned long rsvd_17_19:3; 1497 1138 unsigned long mmr_hash_index_en:1; /* RW */ ··· 1500 1145 unsigned long rsvd_33_47:15; 1501 1146 unsigned long rsvd_48:1; 1502 1147 unsigned long rsvd_49_51:3; 1503 - unsigned long rsvd_52:1; 1504 - unsigned long rsvd_53_63:11; 1148 + unsigned long rsvd_52_63:12; 1505 1149 } sx; 1506 1150 struct uv2h_gr1_tlb_mmr_control_s { 1507 1151 unsigned long index:12; /* RW */ ··· 1537 1183 unsigned long undef_52:1; /* Undefined */ 1538 1184 unsigned long rsvd_53_63:11; 1539 1185 } s3; 1186 + struct uv4h_gr1_tlb_mmr_control_s { 1187 + unsigned long index:13; /* RW */ 1188 + unsigned long mem_sel:2; /* RW */ 1189 + unsigned long rsvd_15:1; 1190 + unsigned long auto_valid_en:1; /* RW */ 1191 + unsigned long rsvd_17_19:3; 1192 + unsigned long mmr_hash_index_en:1; /* RW */ 1193 + unsigned long ecc_sel:1; /* RW */ 1194 + unsigned long rsvd_22_29:8; 1195 + unsigned long mmr_write:1; /* WP */ 1196 + unsigned long mmr_read:1; /* WP */ 1197 + unsigned long mmr_op_done:1; /* RW */ 1198 + unsigned long rsvd_33_47:15; 1199 + unsigned long undef_48:1; /* Undefined */ 1200 + unsigned long rsvd_49_51:3; 1201 + unsigned long rsvd_52_58:7; 1202 + unsigned long page_size:5; /* RW */ 1203 + } s4; 1540 1204 }; 1541 1205 1542 1206 /* ========================================================================= */ ··· 1563 1191 #define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL 1564 1192 #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL 1565 1193 #define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL 1566 - #define UVH_GR1_TLB_MMR_READ_DATA_HI \ 1567 - (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI : \ 1568 - (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI : \ 1569 - UV3H_GR1_TLB_MMR_READ_DATA_HI)) 1194 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI 0x7010a0UL 1195 + #define UVH_GR1_TLB_MMR_READ_DATA_HI ( \ 1196 + is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI : \ 1197 + is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI : \ 1198 + is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_HI : \ 1199 + /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_HI) 1570 1200 1571 1201 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1572 - #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1573 - #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1574 - #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1575 - #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1576 - #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1577 - #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1578 - #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1579 1202 1580 1203 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1581 1204 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 ··· 1582 1215 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1583 1216 1584 1217 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1585 - #define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1586 - #define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1587 - #define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1588 - #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1589 - #define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1590 - #define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1591 - #define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1592 1218 1593 1219 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1594 1220 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 ··· 1605 1245 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL 1606 1246 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1607 1247 1248 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1249 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_SHFT 34 1250 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 49 1251 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 51 1252 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 52 1253 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 53 1254 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 1255 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x00000003ffffffffUL 1256 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_MASK 0x0001fffc00000000UL 1257 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0006000000000000UL 1258 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0008000000000000UL 1259 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0010000000000000UL 1260 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0020000000000000UL 1261 + #define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1262 + 1263 + 1608 1264 union uvh_gr1_tlb_mmr_read_data_hi_u { 1609 1265 unsigned long v; 1610 - struct uvh_gr1_tlb_mmr_read_data_hi_s { 1611 - unsigned long pfn:41; /* RO */ 1612 - unsigned long gaa:2; /* RO */ 1613 - unsigned long dirty:1; /* RO */ 1614 - unsigned long larger:1; /* RO */ 1615 - unsigned long rsvd_45_63:19; 1616 - } s; 1617 1266 struct uv1h_gr1_tlb_mmr_read_data_hi_s { 1618 1267 unsigned long pfn:41; /* RO */ 1619 1268 unsigned long gaa:2; /* RO */ ··· 1630 1261 unsigned long larger:1; /* RO */ 1631 1262 unsigned long rsvd_45_63:19; 1632 1263 } s1; 1633 - struct uvxh_gr1_tlb_mmr_read_data_hi_s { 1634 - unsigned long pfn:41; /* RO */ 1635 - unsigned long gaa:2; /* RO */ 1636 - unsigned long dirty:1; /* RO */ 1637 - unsigned long larger:1; /* RO */ 1638 - unsigned long rsvd_45_63:19; 1639 - } sx; 1640 1264 struct uv2h_gr1_tlb_mmr_read_data_hi_s { 1641 1265 unsigned long pfn:41; /* RO */ 1642 1266 unsigned long gaa:2; /* RO */ ··· 1646 1284 unsigned long undef_46_54:9; /* Undefined */ 1647 1285 unsigned long way_ecc:9; /* RO */ 1648 1286 } s3; 1287 + struct uv4h_gr1_tlb_mmr_read_data_hi_s { 1288 + unsigned long pfn:34; /* RO */ 1289 + unsigned long pnid:15; /* RO */ 1290 + unsigned long gaa:2; /* RO */ 1291 + unsigned long dirty:1; /* RO */ 1292 + unsigned long larger:1; /* RO */ 1293 + unsigned long aa_ext:1; /* RO */ 1294 + unsigned long undef_54:1; /* Undefined */ 1295 + unsigned long way_ecc:9; /* RO */ 1296 + } s4; 1649 1297 }; 1650 1298 1651 1299 /* ========================================================================= */ ··· 1664 1292 #define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL 1665 1293 #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL 1666 1294 #define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL 1667 - #define UVH_GR1_TLB_MMR_READ_DATA_LO \ 1668 - (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO : \ 1669 - (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO : \ 1670 - UV3H_GR1_TLB_MMR_READ_DATA_LO)) 1295 + #define UV4H_GR1_TLB_MMR_READ_DATA_LO 0x7010a8UL 1296 + #define UVH_GR1_TLB_MMR_READ_DATA_LO ( \ 1297 + is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO : \ 1298 + is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO : \ 1299 + is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_LO : \ 1300 + /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_LO) 1671 1301 1672 1302 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1673 1303 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 ··· 1706 1332 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1707 1333 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1708 1334 1335 + #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1336 + #define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1337 + #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1338 + #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1339 + #define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1340 + #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1341 + 1342 + 1709 1343 union uvh_gr1_tlb_mmr_read_data_lo_u { 1710 1344 unsigned long v; 1711 1345 struct uvh_gr1_tlb_mmr_read_data_lo_s { ··· 1741 1359 unsigned long asid:24; /* RO */ 1742 1360 unsigned long valid:1; /* RO */ 1743 1361 } s3; 1362 + struct uv4h_gr1_tlb_mmr_read_data_lo_s { 1363 + unsigned long vpn:39; /* RO */ 1364 + unsigned long asid:24; /* RO */ 1365 + unsigned long valid:1; /* RO */ 1366 + } s4; 1744 1367 }; 1745 1368 1746 1369 /* ========================================================================= */ ··· 1755 1368 1756 1369 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 1757 1370 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL 1371 + 1758 1372 1759 1373 union uvh_int_cmpb_u { 1760 1374 unsigned long v; ··· 1770 1382 /* ========================================================================= */ 1771 1383 #define UVH_INT_CMPC 0x22100UL 1772 1384 1385 + 1773 1386 #define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0 1774 1387 #define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL 1775 1388 1776 1389 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT 0 1777 1390 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL 1391 + 1778 1392 1779 1393 union uvh_int_cmpc_u { 1780 1394 unsigned long v; ··· 1791 1401 /* ========================================================================= */ 1792 1402 #define UVH_INT_CMPD 0x22180UL 1793 1403 1404 + 1794 1405 #define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0 1795 1406 #define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL 1796 1407 1797 1408 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT 0 1798 1409 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL 1410 + 1799 1411 1800 1412 union uvh_int_cmpd_u { 1801 1413 unsigned long v; ··· 1811 1419 /* UVH_IPI_INT */ 1812 1420 /* ========================================================================= */ 1813 1421 #define UVH_IPI_INT 0x60500UL 1814 - #define UVH_IPI_INT_32 0x348 1422 + 1423 + #define UV1H_IPI_INT_32 0x348 1424 + #define UV2H_IPI_INT_32 0x348 1425 + #define UV3H_IPI_INT_32 0x348 1426 + #define UV4H_IPI_INT_32 0x268 1427 + #define UVH_IPI_INT_32 ( \ 1428 + is_uv1_hub() ? UV1H_IPI_INT_32 : \ 1429 + is_uv2_hub() ? UV2H_IPI_INT_32 : \ 1430 + is_uv3_hub() ? UV3H_IPI_INT_32 : \ 1431 + /*is_uv4_hub*/ UV4H_IPI_INT_32) 1815 1432 1816 1433 #define UVH_IPI_INT_VECTOR_SHFT 0 1817 1434 #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 ··· 1832 1431 #define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL 1833 1432 #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL 1834 1433 #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL 1434 + 1835 1435 1836 1436 union uvh_ipi_int_u { 1837 1437 unsigned long v; ··· 1850 1448 /* ========================================================================= */ 1851 1449 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ 1852 1450 /* ========================================================================= */ 1853 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1451 + #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1452 + #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1453 + #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1454 + #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST") 1455 + #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST ( \ 1456 + is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \ 1457 + is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \ 1458 + is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \ 1459 + /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST) 1854 1460 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0 1855 1461 1856 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1857 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1858 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1859 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1462 + 1463 + #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1464 + #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1465 + #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1466 + #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1467 + 1468 + 1469 + #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1470 + #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1471 + #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1472 + #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1473 + 1474 + #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1475 + #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1476 + #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1477 + #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1478 + 1860 1479 1861 1480 union uvh_lb_bau_intd_payload_queue_first_u { 1862 1481 unsigned long v; 1863 - struct uvh_lb_bau_intd_payload_queue_first_s { 1482 + struct uv1h_lb_bau_intd_payload_queue_first_s { 1864 1483 unsigned long rsvd_0_3:4; 1865 1484 unsigned long address:39; /* RW */ 1866 1485 unsigned long rsvd_43_48:6; 1867 1486 unsigned long node_id:14; /* RW */ 1868 1487 unsigned long rsvd_63:1; 1869 - } s; 1488 + } s1; 1489 + struct uv2h_lb_bau_intd_payload_queue_first_s { 1490 + unsigned long rsvd_0_3:4; 1491 + unsigned long address:39; /* RW */ 1492 + unsigned long rsvd_43_48:6; 1493 + unsigned long node_id:14; /* RW */ 1494 + unsigned long rsvd_63:1; 1495 + } s2; 1496 + struct uv3h_lb_bau_intd_payload_queue_first_s { 1497 + unsigned long rsvd_0_3:4; 1498 + unsigned long address:39; /* RW */ 1499 + unsigned long rsvd_43_48:6; 1500 + unsigned long node_id:14; /* RW */ 1501 + unsigned long rsvd_63:1; 1502 + } s3; 1870 1503 }; 1871 1504 1872 1505 /* ========================================================================= */ 1873 1506 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ 1874 1507 /* ========================================================================= */ 1875 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1508 + #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1509 + #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1510 + #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1511 + #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST") 1512 + #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST ( \ 1513 + is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \ 1514 + is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \ 1515 + is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \ 1516 + /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST) 1876 1517 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8 1877 1518 1878 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1879 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1519 + 1520 + #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1521 + #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1522 + 1523 + 1524 + #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1525 + #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1526 + 1527 + #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1528 + #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1529 + 1880 1530 1881 1531 union uvh_lb_bau_intd_payload_queue_last_u { 1882 1532 unsigned long v; 1883 - struct uvh_lb_bau_intd_payload_queue_last_s { 1533 + struct uv1h_lb_bau_intd_payload_queue_last_s { 1884 1534 unsigned long rsvd_0_3:4; 1885 1535 unsigned long address:39; /* RW */ 1886 1536 unsigned long rsvd_43_63:21; 1887 - } s; 1537 + } s1; 1538 + struct uv2h_lb_bau_intd_payload_queue_last_s { 1539 + unsigned long rsvd_0_3:4; 1540 + unsigned long address:39; /* RW */ 1541 + unsigned long rsvd_43_63:21; 1542 + } s2; 1543 + struct uv3h_lb_bau_intd_payload_queue_last_s { 1544 + unsigned long rsvd_0_3:4; 1545 + unsigned long address:39; /* RW */ 1546 + unsigned long rsvd_43_63:21; 1547 + } s3; 1888 1548 }; 1889 1549 1890 1550 /* ========================================================================= */ 1891 1551 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ 1892 1552 /* ========================================================================= */ 1893 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1553 + #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1554 + #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1555 + #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1556 + #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL") 1557 + #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL ( \ 1558 + is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \ 1559 + is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \ 1560 + is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \ 1561 + /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL) 1894 1562 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0 1895 1563 1896 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1897 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1564 + 1565 + #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1566 + #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1567 + 1568 + 1569 + #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1570 + #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1571 + 1572 + #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1573 + #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1574 + 1898 1575 1899 1576 union uvh_lb_bau_intd_payload_queue_tail_u { 1900 1577 unsigned long v; 1901 - struct uvh_lb_bau_intd_payload_queue_tail_s { 1578 + struct uv1h_lb_bau_intd_payload_queue_tail_s { 1902 1579 unsigned long rsvd_0_3:4; 1903 1580 unsigned long address:39; /* RW */ 1904 1581 unsigned long rsvd_43_63:21; 1905 - } s; 1582 + } s1; 1583 + struct uv2h_lb_bau_intd_payload_queue_tail_s { 1584 + unsigned long rsvd_0_3:4; 1585 + unsigned long address:39; /* RW */ 1586 + unsigned long rsvd_43_63:21; 1587 + } s2; 1588 + struct uv3h_lb_bau_intd_payload_queue_tail_s { 1589 + unsigned long rsvd_0_3:4; 1590 + unsigned long address:39; /* RW */ 1591 + unsigned long rsvd_43_63:21; 1592 + } s3; 1906 1593 }; 1907 1594 1908 1595 /* ========================================================================= */ 1909 1596 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ 1910 1597 /* ========================================================================= */ 1911 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 1598 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 1599 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 1600 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 1601 + #define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE") 1602 + #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE ( \ 1603 + is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \ 1604 + is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \ 1605 + is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \ 1606 + /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE) 1912 1607 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68 1913 1608 1914 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 1915 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 1916 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 1917 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 1918 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 1919 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 1920 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 1921 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 1922 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 1923 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 1924 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 1925 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 1926 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 1927 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 1928 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 1929 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 1930 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 1931 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 1932 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 1933 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 1934 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 1935 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 1936 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 1937 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 1938 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 1939 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 1940 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 1941 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 1942 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 1943 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 1944 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 1945 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 1609 + 1610 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 1611 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 1612 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 1613 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 1614 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 1615 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 1616 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 1617 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 1618 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 1619 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 1620 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 1621 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 1622 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 1623 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 1624 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 1625 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 1626 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 1627 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 1628 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 1629 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 1630 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 1631 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 1632 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 1633 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 1634 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 1635 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 1636 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 1637 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 1638 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 1639 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 1640 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 1641 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 1642 + 1643 + 1644 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 1645 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 1646 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 1647 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 1648 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 1649 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 1650 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 1651 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 1652 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 1653 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 1654 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 1655 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 1656 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 1657 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 1658 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 1659 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 1660 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 1661 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 1662 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 1663 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 1664 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 1665 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 1666 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 1667 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 1668 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 1669 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 1670 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 1671 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 1672 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 1673 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 1674 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 1675 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 1676 + 1677 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 1678 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 1679 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 1680 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 1681 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 1682 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 1683 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 1684 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 1685 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 1686 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 1687 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 1688 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 1689 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 1690 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 1691 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 1692 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 1693 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 1694 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 1695 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 1696 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 1697 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 1698 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 1699 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 1700 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 1701 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 1702 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 1703 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 1704 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 1705 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 1706 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 1707 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 1708 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 1709 + 1946 1710 1947 1711 union uvh_lb_bau_intd_software_acknowledge_u { 1948 1712 unsigned long v; 1949 - struct uvh_lb_bau_intd_software_acknowledge_s { 1713 + struct uv1h_lb_bau_intd_software_acknowledge_s { 1950 1714 unsigned long pending_0:1; /* RW, W1C */ 1951 1715 unsigned long pending_1:1; /* RW, W1C */ 1952 1716 unsigned long pending_2:1; /* RW, W1C */ ··· 2130 1562 unsigned long timeout_6:1; /* RW, W1C */ 2131 1563 unsigned long timeout_7:1; /* RW, W1C */ 2132 1564 unsigned long rsvd_16_63:48; 2133 - } s; 1565 + } s1; 1566 + struct uv2h_lb_bau_intd_software_acknowledge_s { 1567 + unsigned long pending_0:1; /* RW */ 1568 + unsigned long pending_1:1; /* RW */ 1569 + unsigned long pending_2:1; /* RW */ 1570 + unsigned long pending_3:1; /* RW */ 1571 + unsigned long pending_4:1; /* RW */ 1572 + unsigned long pending_5:1; /* RW */ 1573 + unsigned long pending_6:1; /* RW */ 1574 + unsigned long pending_7:1; /* RW */ 1575 + unsigned long timeout_0:1; /* RW */ 1576 + unsigned long timeout_1:1; /* RW */ 1577 + unsigned long timeout_2:1; /* RW */ 1578 + unsigned long timeout_3:1; /* RW */ 1579 + unsigned long timeout_4:1; /* RW */ 1580 + unsigned long timeout_5:1; /* RW */ 1581 + unsigned long timeout_6:1; /* RW */ 1582 + unsigned long timeout_7:1; /* RW */ 1583 + unsigned long rsvd_16_63:48; 1584 + } s2; 1585 + struct uv3h_lb_bau_intd_software_acknowledge_s { 1586 + unsigned long pending_0:1; /* RW */ 1587 + unsigned long pending_1:1; /* RW */ 1588 + unsigned long pending_2:1; /* RW */ 1589 + unsigned long pending_3:1; /* RW */ 1590 + unsigned long pending_4:1; /* RW */ 1591 + unsigned long pending_5:1; /* RW */ 1592 + unsigned long pending_6:1; /* RW */ 1593 + unsigned long pending_7:1; /* RW */ 1594 + unsigned long timeout_0:1; /* RW */ 1595 + unsigned long timeout_1:1; /* RW */ 1596 + unsigned long timeout_2:1; /* RW */ 1597 + unsigned long timeout_3:1; /* RW */ 1598 + unsigned long timeout_4:1; /* RW */ 1599 + unsigned long timeout_5:1; /* RW */ 1600 + unsigned long timeout_6:1; /* RW */ 1601 + unsigned long timeout_7:1; /* RW */ 1602 + unsigned long rsvd_16_63:48; 1603 + } s3; 2134 1604 }; 2135 1605 2136 1606 /* ========================================================================= */ 2137 1607 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ 2138 1608 /* ========================================================================= */ 2139 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 1609 + #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 1610 + #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 1611 + #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 1612 + #define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS") 1613 + #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS ( \ 1614 + is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \ 1615 + is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \ 1616 + is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \ 1617 + /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS) 2140 1618 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70 2141 1619 2142 1620 2143 1621 /* ========================================================================= */ 2144 1622 /* UVH_LB_BAU_MISC_CONTROL */ 2145 1623 /* ========================================================================= */ 2146 - #define UVH_LB_BAU_MISC_CONTROL 0x320170UL 2147 1624 #define UV1H_LB_BAU_MISC_CONTROL 0x320170UL 2148 1625 #define UV2H_LB_BAU_MISC_CONTROL 0x320170UL 2149 1626 #define UV3H_LB_BAU_MISC_CONTROL 0x320170UL 2150 - #define UVH_LB_BAU_MISC_CONTROL_32 0xa10 2151 - #define UV1H_LB_BAU_MISC_CONTROL_32 0x320170UL 2152 - #define UV2H_LB_BAU_MISC_CONTROL_32 0x320170UL 2153 - #define UV3H_LB_BAU_MISC_CONTROL_32 0x320170UL 1627 + #define UV4H_LB_BAU_MISC_CONTROL 0xc8170UL 1628 + #define UVH_LB_BAU_MISC_CONTROL ( \ 1629 + is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL : \ 1630 + is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL : \ 1631 + is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL : \ 1632 + /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL) 1633 + 1634 + #define UV1H_LB_BAU_MISC_CONTROL_32 0xa10 1635 + #define UV2H_LB_BAU_MISC_CONTROL_32 0xa10 1636 + #define UV3H_LB_BAU_MISC_CONTROL_32 0xa10 1637 + #define UV4H_LB_BAU_MISC_CONTROL_32 0xa18 1638 + #define UVH_LB_BAU_MISC_CONTROL_32 ( \ 1639 + is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_32 : \ 1640 + is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_32 : \ 1641 + is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_32 : \ 1642 + /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_32) 2154 1643 2155 1644 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2156 1645 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 ··· 2215 1590 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2216 1591 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2217 1592 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2218 - #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 2219 - #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 2220 1593 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2221 1594 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2222 1595 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 ··· 2229 1606 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2230 1607 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2231 1608 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2232 - #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 2233 - #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 2234 1609 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2235 1610 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2236 1611 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL ··· 2277 1656 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2278 1657 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2279 1658 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2280 - #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 2281 - #define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 2282 1659 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2283 1660 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2284 1661 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 ··· 2298 1679 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2299 1680 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2300 1681 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2301 - #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 2302 - #define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 2303 1682 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2304 1683 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2305 1684 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL ··· 2414 1797 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL 2415 1798 #define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2416 1799 1800 + #define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1801 + #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1802 + #define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 1803 + #define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 1804 + #define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1805 + #define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1806 + #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_SHFT 15 1807 + #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1808 + #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1809 + #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1810 + #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1811 + #define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1812 + #define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1813 + #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1814 + #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 1815 + #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 1816 + #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 1817 + #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 1818 + #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 1819 + #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 1820 + #define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 1821 + #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36 1822 + #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_SHFT 37 1823 + #define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38 1824 + #define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_SHFT 46 1825 + #define UV4H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1826 + #define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1827 + #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1828 + #define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 1829 + #define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 1830 + #define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 1831 + #define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 1832 + #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_MASK 0x00000000000f8000UL 1833 + #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 1834 + #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 1835 + #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 1836 + #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 1837 + #define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 1838 + #define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 1839 + #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1840 + #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 1841 + #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 1842 + #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 1843 + #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 1844 + #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 1845 + #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 1846 + #define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 1847 + #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL 1848 + #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_MASK 0x0000002000000000UL 1849 + #define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL 1850 + #define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_MASK 0x0000400000000000UL 1851 + #define UV4H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 1852 + 1853 + #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK \ 1854 + uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK") 1855 + #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK ( \ 1856 + is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \ 1857 + is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \ 1858 + is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \ 1859 + /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK) 1860 + #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT \ 1861 + uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT") 1862 + #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT ( \ 1863 + is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \ 1864 + is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \ 1865 + is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \ 1866 + /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT) 1867 + #define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK \ 1868 + uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK") 1869 + #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK ( \ 1870 + is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \ 1871 + is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \ 1872 + is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \ 1873 + /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK) 1874 + #define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT \ 1875 + uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT") 1876 + #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT ( \ 1877 + is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \ 1878 + is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \ 1879 + is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \ 1880 + /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT) 1881 + 2417 1882 union uvh_lb_bau_misc_control_u { 2418 1883 unsigned long v; 2419 1884 struct uvh_lb_bau_misc_control_s { ··· 2505 1806 unsigned long force_lock_nop:1; /* RW */ 2506 1807 unsigned long qpi_agent_presence_vector:3; /* RW */ 2507 1808 unsigned long descriptor_fetch_mode:1; /* RW */ 2508 - unsigned long enable_intd_soft_ack_mode:1; /* RW */ 2509 - unsigned long intd_soft_ack_timeout_period:4; /* RW */ 1809 + unsigned long rsvd_15_19:5; 2510 1810 unsigned long enable_dual_mapping_mode:1; /* RW */ 2511 1811 unsigned long vga_io_port_decode_enable:1; /* RW */ 2512 1812 unsigned long vga_io_port_16_bit_decode:1; /* RW */ ··· 2542 1844 unsigned long force_lock_nop:1; /* RW */ 2543 1845 unsigned long qpi_agent_presence_vector:3; /* RW */ 2544 1846 unsigned long descriptor_fetch_mode:1; /* RW */ 2545 - unsigned long enable_intd_soft_ack_mode:1; /* RW */ 2546 - unsigned long intd_soft_ack_timeout_period:4; /* RW */ 1847 + unsigned long rsvd_15_19:5; 2547 1848 unsigned long enable_dual_mapping_mode:1; /* RW */ 2548 1849 unsigned long vga_io_port_decode_enable:1; /* RW */ 2549 1850 unsigned long vga_io_port_16_bit_decode:1; /* RW */ ··· 2615 1918 unsigned long rsvd_46_47:2; 2616 1919 unsigned long fun:16; /* RW */ 2617 1920 } s3; 1921 + struct uv4h_lb_bau_misc_control_s { 1922 + unsigned long rejection_delay:8; /* RW */ 1923 + unsigned long apic_mode:1; /* RW */ 1924 + unsigned long force_broadcast:1; /* RW */ 1925 + unsigned long force_lock_nop:1; /* RW */ 1926 + unsigned long qpi_agent_presence_vector:3; /* RW */ 1927 + unsigned long descriptor_fetch_mode:1; /* RW */ 1928 + unsigned long rsvd_15_19:5; 1929 + unsigned long enable_dual_mapping_mode:1; /* RW */ 1930 + unsigned long vga_io_port_decode_enable:1; /* RW */ 1931 + unsigned long vga_io_port_16_bit_decode:1; /* RW */ 1932 + unsigned long suppress_dest_registration:1; /* RW */ 1933 + unsigned long programmed_initial_priority:3; /* RW */ 1934 + unsigned long use_incoming_priority:1; /* RW */ 1935 + unsigned long enable_programmed_initial_priority:1;/* RW */ 1936 + unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 1937 + unsigned long apic_mode_status:1; /* RO */ 1938 + unsigned long suppress_interrupts_to_self:1; /* RW */ 1939 + unsigned long enable_lock_based_system_flush:1;/* RW */ 1940 + unsigned long enable_extended_sb_status:1; /* RW */ 1941 + unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 1942 + unsigned long use_legacy_descriptor_formats:1;/* RW */ 1943 + unsigned long suppress_quiesce_msgs_to_qpi:1; /* RW */ 1944 + unsigned long rsvd_37:1; 1945 + unsigned long thread_kill_timebase:8; /* RW */ 1946 + unsigned long address_interleave_select:1; /* RW */ 1947 + unsigned long rsvd_47:1; 1948 + unsigned long fun:16; /* RW */ 1949 + } s4; 2618 1950 }; 2619 1951 2620 1952 /* ========================================================================= */ 2621 1953 /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 2622 1954 /* ========================================================================= */ 2623 - #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 2624 - #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 1955 + #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 1956 + #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 1957 + #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 1958 + #define UV4H_LB_BAU_SB_ACTIVATION_CONTROL 0xc8020UL 1959 + #define UVH_LB_BAU_SB_ACTIVATION_CONTROL ( \ 1960 + is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL : \ 1961 + is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL : \ 1962 + is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL : \ 1963 + /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL) 1964 + 1965 + #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 1966 + #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 1967 + #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 1968 + #define UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9c8 1969 + #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 ( \ 1970 + is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \ 1971 + is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \ 1972 + is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \ 1973 + /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32) 2625 1974 2626 1975 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 2627 1976 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 ··· 2675 1932 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL 2676 1933 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL 2677 1934 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL 1935 + 2678 1936 2679 1937 union uvh_lb_bau_sb_activation_control_u { 2680 1938 unsigned long v; ··· 2690 1946 /* ========================================================================= */ 2691 1947 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ 2692 1948 /* ========================================================================= */ 2693 - #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 2694 - #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 1949 + #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 1950 + #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 1951 + #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 1952 + #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0 0xc8030UL 1953 + #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 ( \ 1954 + is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 : \ 1955 + is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 : \ 1956 + is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 : \ 1957 + /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0) 1958 + 1959 + #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 1960 + #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 1961 + #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 1962 + #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9d0 1963 + #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 ( \ 1964 + is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \ 1965 + is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \ 1966 + is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \ 1967 + /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32) 2695 1968 2696 1969 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 2697 1970 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL 1971 + 2698 1972 2699 1973 union uvh_lb_bau_sb_activation_status_0_u { 2700 1974 unsigned long v; ··· 2724 1962 /* ========================================================================= */ 2725 1963 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ 2726 1964 /* ========================================================================= */ 2727 - #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 2728 - #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 1965 + #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 1966 + #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 1967 + #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 1968 + #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1 0xc8040UL 1969 + #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 ( \ 1970 + is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 : \ 1971 + is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 : \ 1972 + is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 : \ 1973 + /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1) 1974 + 1975 + #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 1976 + #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 1977 + #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 1978 + #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9d8 1979 + #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 ( \ 1980 + is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \ 1981 + is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \ 1982 + is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \ 1983 + /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32) 2729 1984 2730 1985 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 2731 1986 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL 1987 + 2732 1988 2733 1989 union uvh_lb_bau_sb_activation_status_1_u { 2734 1990 unsigned long v; ··· 2758 1978 /* ========================================================================= */ 2759 1979 /* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ 2760 1980 /* ========================================================================= */ 2761 - #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 2762 - #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 1981 + #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 1982 + #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 1983 + #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 1984 + #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE 0xc8010UL 1985 + #define UVH_LB_BAU_SB_DESCRIPTOR_BASE ( \ 1986 + is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE : \ 1987 + is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE : \ 1988 + is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE : \ 1989 + /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE) 1990 + 1991 + #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 1992 + #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 1993 + #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 1994 + #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9c0 1995 + #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 ( \ 1996 + is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \ 1997 + is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \ 1998 + is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \ 1999 + /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32) 2763 2000 2764 2001 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 2765 2002 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 2766 - #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 2767 2003 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL 2004 + 2005 + #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 2006 + 2007 + 2008 + #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 2009 + 2010 + #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 2011 + 2012 + #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x00003ffffffff000UL 2013 + 2768 2014 2769 2015 union uvh_lb_bau_sb_descriptor_base_u { 2770 2016 unsigned long v; 2771 2017 struct uvh_lb_bau_sb_descriptor_base_s { 2772 2018 unsigned long rsvd_0_11:12; 2773 - unsigned long page_address:31; /* RW */ 2774 - unsigned long rsvd_43_48:6; 2019 + unsigned long rsvd_12_48:37; 2775 2020 unsigned long node_id:14; /* RW */ 2776 2021 unsigned long rsvd_63:1; 2777 2022 } s; 2023 + struct uv4h_lb_bau_sb_descriptor_base_s { 2024 + unsigned long rsvd_0_11:12; 2025 + unsigned long page_address:34; /* RW */ 2026 + unsigned long rsvd_46_48:3; 2027 + unsigned long node_id:14; /* RW */ 2028 + unsigned long rsvd_63:1; 2029 + } s4; 2778 2030 }; 2779 2031 2780 2032 /* ========================================================================= */ ··· 2816 2004 #define UV1H_NODE_ID 0x0UL 2817 2005 #define UV2H_NODE_ID 0x0UL 2818 2006 #define UV3H_NODE_ID 0x0UL 2007 + #define UV4H_NODE_ID 0x0UL 2819 2008 2820 2009 #define UVH_NODE_ID_FORCE1_SHFT 0 2821 2010 #define UVH_NODE_ID_MANUFACTURER_SHFT 1 ··· 2893 2080 #define UV3H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2894 2081 #define UV3H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2895 2082 2083 + #define UV4H_NODE_ID_FORCE1_SHFT 0 2084 + #define UV4H_NODE_ID_MANUFACTURER_SHFT 1 2085 + #define UV4H_NODE_ID_PART_NUMBER_SHFT 12 2086 + #define UV4H_NODE_ID_REVISION_SHFT 28 2087 + #define UV4H_NODE_ID_NODE_ID_SHFT 32 2088 + #define UV4H_NODE_ID_ROUTER_SELECT_SHFT 48 2089 + #define UV4H_NODE_ID_RESERVED_2_SHFT 49 2090 + #define UV4H_NODE_ID_NODES_PER_BIT_SHFT 50 2091 + #define UV4H_NODE_ID_NI_PORT_SHFT 57 2092 + #define UV4H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2093 + #define UV4H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2094 + #define UV4H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2095 + #define UV4H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2096 + #define UV4H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2097 + #define UV4H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL 2098 + #define UV4H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL 2099 + #define UV4H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2100 + #define UV4H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2101 + 2102 + 2896 2103 union uvh_node_id_u { 2897 2104 unsigned long v; 2898 2105 struct uvh_node_id_s { ··· 2970 2137 unsigned long ni_port:5; /* RO */ 2971 2138 unsigned long rsvd_62_63:2; 2972 2139 } s3; 2140 + struct uv4h_node_id_s { 2141 + unsigned long force1:1; /* RO */ 2142 + unsigned long manufacturer:11; /* RO */ 2143 + unsigned long part_number:16; /* RO */ 2144 + unsigned long revision:4; /* RO */ 2145 + unsigned long node_id:15; /* RW */ 2146 + unsigned long rsvd_47:1; 2147 + unsigned long router_select:1; /* RO */ 2148 + unsigned long rsvd_49:1; 2149 + unsigned long nodes_per_bit:7; /* RO */ 2150 + unsigned long ni_port:5; /* RO */ 2151 + unsigned long rsvd_62_63:2; 2152 + } s4; 2973 2153 }; 2974 2154 2975 2155 /* ========================================================================= */ 2976 2156 /* UVH_NODE_PRESENT_TABLE */ 2977 2157 /* ========================================================================= */ 2978 2158 #define UVH_NODE_PRESENT_TABLE 0x1400UL 2979 - #define UVH_NODE_PRESENT_TABLE_DEPTH 16 2159 + 2160 + #define UV1H_NODE_PRESENT_TABLE_DEPTH 16 2161 + #define UV2H_NODE_PRESENT_TABLE_DEPTH 16 2162 + #define UV3H_NODE_PRESENT_TABLE_DEPTH 16 2163 + #define UV4H_NODE_PRESENT_TABLE_DEPTH 4 2164 + #define UVH_NODE_PRESENT_TABLE_DEPTH ( \ 2165 + is_uv1_hub() ? UV1H_NODE_PRESENT_TABLE_DEPTH : \ 2166 + is_uv2_hub() ? UV2H_NODE_PRESENT_TABLE_DEPTH : \ 2167 + is_uv3_hub() ? UV3H_NODE_PRESENT_TABLE_DEPTH : \ 2168 + /*is_uv4_hub*/ UV4H_NODE_PRESENT_TABLE_DEPTH) 2980 2169 2981 2170 #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 2982 2171 #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL 2172 + 2983 2173 2984 2174 union uvh_node_present_table_u { 2985 2175 unsigned long v; ··· 3014 2158 /* ========================================================================= */ 3015 2159 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */ 3016 2160 /* ========================================================================= */ 3017 - #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 2161 + #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 2162 + #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 2163 + #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 2164 + #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x4800c8UL 2165 + #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR ( \ 2166 + is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \ 2167 + is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \ 2168 + is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \ 2169 + /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR) 3018 2170 3019 2171 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 3020 2172 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 ··· 3030 2166 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 3031 2167 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 3032 2168 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 2169 + 3033 2170 3034 2171 union uvh_rh_gam_alias210_overlay_config_0_mmr_u { 3035 2172 unsigned long v; ··· 3047 2182 /* ========================================================================= */ 3048 2183 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */ 3049 2184 /* ========================================================================= */ 3050 - #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 2185 + #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 2186 + #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 2187 + #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 2188 + #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x4800d8UL 2189 + #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR ( \ 2190 + is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \ 2191 + is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \ 2192 + is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \ 2193 + /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR) 3051 2194 3052 2195 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 3053 2196 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 ··· 3063 2190 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 3064 2191 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 3065 2192 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 2193 + 3066 2194 3067 2195 union uvh_rh_gam_alias210_overlay_config_1_mmr_u { 3068 2196 unsigned long v; ··· 3080 2206 /* ========================================================================= */ 3081 2207 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */ 3082 2208 /* ========================================================================= */ 3083 - #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 2209 + #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 2210 + #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 2211 + #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 2212 + #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x4800e8UL 2213 + #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR ( \ 2214 + is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \ 2215 + is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \ 2216 + is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \ 2217 + /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR) 3084 2218 3085 2219 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 3086 2220 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 ··· 3096 2214 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 3097 2215 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 3098 2216 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 2217 + 3099 2218 3100 2219 union uvh_rh_gam_alias210_overlay_config_2_mmr_u { 3101 2220 unsigned long v; ··· 3113 2230 /* ========================================================================= */ 3114 2231 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ 3115 2232 /* ========================================================================= */ 3116 - #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 2233 + #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 2234 + #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 2235 + #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 2236 + #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x4800d0UL 2237 + #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR ( \ 2238 + is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \ 2239 + is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \ 2240 + is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \ 2241 + /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR) 3117 2242 3118 2243 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 3119 2244 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2245 + 3120 2246 3121 2247 union uvh_rh_gam_alias210_redirect_config_0_mmr_u { 3122 2248 unsigned long v; ··· 3139 2247 /* ========================================================================= */ 3140 2248 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ 3141 2249 /* ========================================================================= */ 3142 - #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 2250 + #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 2251 + #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 2252 + #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 2253 + #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x4800e0UL 2254 + #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR ( \ 2255 + is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \ 2256 + is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \ 2257 + is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \ 2258 + /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR) 3143 2259 3144 2260 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 3145 2261 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2262 + 3146 2263 3147 2264 union uvh_rh_gam_alias210_redirect_config_1_mmr_u { 3148 2265 unsigned long v; ··· 3165 2264 /* ========================================================================= */ 3166 2265 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ 3167 2266 /* ========================================================================= */ 3168 - #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 2267 + #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 2268 + #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 2269 + #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 2270 + #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x4800f0UL 2271 + #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR ( \ 2272 + is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \ 2273 + is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \ 2274 + is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \ 2275 + /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR) 3169 2276 3170 2277 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 3171 2278 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2279 + 3172 2280 3173 2281 union uvh_rh_gam_alias210_redirect_config_2_mmr_u { 3174 2282 unsigned long v; ··· 3191 2281 /* ========================================================================= */ 3192 2282 /* UVH_RH_GAM_CONFIG_MMR */ 3193 2283 /* ========================================================================= */ 3194 - #define UVH_RH_GAM_CONFIG_MMR 0x1600000UL 3195 2284 #define UV1H_RH_GAM_CONFIG_MMR 0x1600000UL 3196 2285 #define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL 3197 2286 #define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL 2287 + #define UV4H_RH_GAM_CONFIG_MMR 0x480000UL 2288 + #define UVH_RH_GAM_CONFIG_MMR ( \ 2289 + is_uv1_hub() ? UV1H_RH_GAM_CONFIG_MMR : \ 2290 + is_uv2_hub() ? UV2H_RH_GAM_CONFIG_MMR : \ 2291 + is_uv3_hub() ? UV3H_RH_GAM_CONFIG_MMR : \ 2292 + /*is_uv4_hub*/ UV4H_RH_GAM_CONFIG_MMR) 3198 2293 3199 - #define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 3200 2294 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3201 - #define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 3202 2295 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3203 2296 3204 2297 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 ··· 3211 2298 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3212 2299 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL 3213 2300 3214 - #define UVXH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 3215 2301 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3216 - #define UVXH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 3217 2302 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3218 2303 3219 2304 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 ··· 3224 2313 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 3225 2314 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3226 2315 2316 + #define UV4H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 2317 + #define UV4H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 2318 + 2319 + 3227 2320 union uvh_rh_gam_config_mmr_u { 3228 2321 unsigned long v; 3229 2322 struct uvh_rh_gam_config_mmr_s { 3230 - unsigned long m_skt:6; /* RW */ 2323 + unsigned long rsvd_0_5:6; 3231 2324 unsigned long n_skt:4; /* RW */ 3232 2325 unsigned long rsvd_10_63:54; 3233 2326 } s; ··· 3243 2328 unsigned long rsvd_13_63:51; 3244 2329 } s1; 3245 2330 struct uvxh_rh_gam_config_mmr_s { 3246 - unsigned long m_skt:6; /* RW */ 2331 + unsigned long rsvd_0_5:6; 3247 2332 unsigned long n_skt:4; /* RW */ 3248 2333 unsigned long rsvd_10_63:54; 3249 2334 } sx; ··· 3257 2342 unsigned long n_skt:4; /* RW */ 3258 2343 unsigned long rsvd_10_63:54; 3259 2344 } s3; 2345 + struct uv4h_rh_gam_config_mmr_s { 2346 + unsigned long rsvd_0_5:6; 2347 + unsigned long n_skt:4; /* RW */ 2348 + unsigned long rsvd_10_63:54; 2349 + } s4; 3260 2350 }; 3261 2351 3262 2352 /* ========================================================================= */ 3263 2353 /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ 3264 2354 /* ========================================================================= */ 3265 - #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3266 2355 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3267 2356 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3268 2357 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 2358 + #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x480010UL 2359 + #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR ( \ 2360 + is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \ 2361 + is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \ 2362 + is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \ 2363 + /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR) 3269 2364 3270 - #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 3271 2365 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3272 2366 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3273 - #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 3274 2367 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3275 2368 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3276 2369 ··· 3291 2368 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3292 2369 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3293 2370 3294 - #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 3295 2371 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3296 2372 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3297 - #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 3298 2373 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3299 2374 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3300 2375 ··· 3312 2391 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK 0x4000000000000000UL 3313 2392 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3314 2393 2394 + #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 26 2395 + #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 2396 + #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2397 + #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 2398 + #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 2399 + #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2400 + 2401 + #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK ( \ 2402 + is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \ 2403 + is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \ 2404 + is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \ 2405 + /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK) 2406 + #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT ( \ 2407 + is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \ 2408 + is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \ 2409 + is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \ 2410 + /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT) 2411 + 3315 2412 union uvh_rh_gam_gru_overlay_config_mmr_u { 3316 2413 unsigned long v; 3317 2414 struct uvh_rh_gam_gru_overlay_config_mmr_s { 3318 - unsigned long rsvd_0_27:28; 3319 - unsigned long base:18; /* RW */ 3320 - unsigned long rsvd_46_51:6; 2415 + unsigned long rsvd_0_51:52; 3321 2416 unsigned long n_gru:4; /* RW */ 3322 2417 unsigned long rsvd_56_62:7; 3323 2418 unsigned long enable:1; /* RW */ ··· 3349 2412 unsigned long enable:1; /* RW */ 3350 2413 } s1; 3351 2414 struct uvxh_rh_gam_gru_overlay_config_mmr_s { 3352 - unsigned long rsvd_0_27:28; 3353 - unsigned long base:18; /* RW */ 2415 + unsigned long rsvd_0_45:46; 3354 2416 unsigned long rsvd_46_51:6; 3355 2417 unsigned long n_gru:4; /* RW */ 3356 2418 unsigned long rsvd_56_62:7; ··· 3372 2436 unsigned long mode:1; /* RW */ 3373 2437 unsigned long enable:1; /* RW */ 3374 2438 } s3; 2439 + struct uv4h_rh_gam_gru_overlay_config_mmr_s { 2440 + unsigned long rsvd_0_24:25; 2441 + unsigned long undef_25:1; /* Undefined */ 2442 + unsigned long base:20; /* RW */ 2443 + unsigned long rsvd_46_51:6; 2444 + unsigned long n_gru:4; /* RW */ 2445 + unsigned long rsvd_56_62:7; 2446 + unsigned long enable:1; /* RW */ 2447 + } s4; 3375 2448 }; 3376 2449 3377 2450 /* ========================================================================= */ ··· 3388 2443 /* ========================================================================= */ 3389 2444 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 3390 2445 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 2446 + #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR") 2447 + #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR") 2448 + #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR ( \ 2449 + is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \ 2450 + is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \ 2451 + is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \ 2452 + /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR) 2453 + 3391 2454 3392 2455 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 3393 2456 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 ··· 3406 2453 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 3407 2454 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3408 2455 2456 + 3409 2457 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27 3410 2458 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 3411 2459 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 ··· 3415 2461 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL 3416 2462 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 3417 2463 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2464 + 3418 2465 3419 2466 union uvh_rh_gam_mmioh_overlay_config_mmr_u { 3420 2467 unsigned long v; ··· 3440 2485 /* ========================================================================= */ 3441 2486 /* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ 3442 2487 /* ========================================================================= */ 3443 - #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3444 2488 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3445 2489 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3446 2490 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 2491 + #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x480028UL 2492 + #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR ( \ 2493 + is_uv1_hub() ? UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \ 2494 + is_uv2_hub() ? UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \ 2495 + is_uv3_hub() ? UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \ 2496 + /*is_uv4_hub*/ UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR) 3447 2497 3448 2498 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3449 2499 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 ··· 3476 2516 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3477 2517 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3478 2518 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2519 + 2520 + #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 2521 + #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2522 + #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 2523 + #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2524 + 3479 2525 3480 2526 union uvh_rh_gam_mmr_overlay_config_mmr_u { 3481 2527 unsigned long v; ··· 3516 2550 unsigned long rsvd_46_62:17; 3517 2551 unsigned long enable:1; /* RW */ 3518 2552 } s3; 2553 + struct uv4h_rh_gam_mmr_overlay_config_mmr_s { 2554 + unsigned long rsvd_0_25:26; 2555 + unsigned long base:20; /* RW */ 2556 + unsigned long rsvd_46_62:17; 2557 + unsigned long enable:1; /* RW */ 2558 + } s4; 3519 2559 }; 3520 2560 3521 2561 /* ========================================================================= */ 3522 2562 /* UVH_RTC */ 3523 2563 /* ========================================================================= */ 3524 - #define UVH_RTC 0x340000UL 2564 + #define UV1H_RTC 0x340000UL 2565 + #define UV2H_RTC 0x340000UL 2566 + #define UV3H_RTC 0x340000UL 2567 + #define UV4H_RTC 0xe0000UL 2568 + #define UVH_RTC ( \ 2569 + is_uv1_hub() ? UV1H_RTC : \ 2570 + is_uv2_hub() ? UV2H_RTC : \ 2571 + is_uv3_hub() ? UV3H_RTC : \ 2572 + /*is_uv4_hub*/ UV4H_RTC) 3525 2573 3526 2574 #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 3527 2575 #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL 2576 + 3528 2577 3529 2578 union uvh_rtc_u { 3530 2579 unsigned long v; ··· 3571 2590 #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL 3572 2591 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 3573 2592 2593 + 3574 2594 union uvh_rtc1_int_config_u { 3575 2595 unsigned long v; 3576 2596 struct uvh_rtc1_int_config_s { ··· 3591 2609 /* ========================================================================= */ 3592 2610 /* UVH_SCRATCH5 */ 3593 2611 /* ========================================================================= */ 3594 - #define UVH_SCRATCH5 0x2d0200UL 3595 - #define UVH_SCRATCH5_32 0x778 2612 + #define UV1H_SCRATCH5 0x2d0200UL 2613 + #define UV2H_SCRATCH5 0x2d0200UL 2614 + #define UV3H_SCRATCH5 0x2d0200UL 2615 + #define UV4H_SCRATCH5 0xb0200UL 2616 + #define UVH_SCRATCH5 ( \ 2617 + is_uv1_hub() ? UV1H_SCRATCH5 : \ 2618 + is_uv2_hub() ? UV2H_SCRATCH5 : \ 2619 + is_uv3_hub() ? UV3H_SCRATCH5 : \ 2620 + /*is_uv4_hub*/ UV4H_SCRATCH5) 2621 + 2622 + #define UV1H_SCRATCH5_32 0x778 2623 + #define UV2H_SCRATCH5_32 0x778 2624 + #define UV3H_SCRATCH5_32 0x778 2625 + #define UV4H_SCRATCH5_32 0x798 2626 + #define UVH_SCRATCH5_32 ( \ 2627 + is_uv1_hub() ? UV1H_SCRATCH5_32 : \ 2628 + is_uv2_hub() ? UV2H_SCRATCH5_32 : \ 2629 + is_uv3_hub() ? UV3H_SCRATCH5_32 : \ 2630 + /*is_uv4_hub*/ UV4H_SCRATCH5_32) 3596 2631 3597 2632 #define UVH_SCRATCH5_SCRATCH5_SHFT 0 3598 2633 #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL 2634 + 3599 2635 3600 2636 union uvh_scratch5_u { 3601 2637 unsigned long v; ··· 3625 2625 /* ========================================================================= */ 3626 2626 /* UVH_SCRATCH5_ALIAS */ 3627 2627 /* ========================================================================= */ 3628 - #define UVH_SCRATCH5_ALIAS 0x2d0208UL 3629 - #define UVH_SCRATCH5_ALIAS_32 0x780 2628 + #define UV1H_SCRATCH5_ALIAS 0x2d0208UL 2629 + #define UV2H_SCRATCH5_ALIAS 0x2d0208UL 2630 + #define UV3H_SCRATCH5_ALIAS 0x2d0208UL 2631 + #define UV4H_SCRATCH5_ALIAS 0xb0208UL 2632 + #define UVH_SCRATCH5_ALIAS ( \ 2633 + is_uv1_hub() ? UV1H_SCRATCH5_ALIAS : \ 2634 + is_uv2_hub() ? UV2H_SCRATCH5_ALIAS : \ 2635 + is_uv3_hub() ? UV3H_SCRATCH5_ALIAS : \ 2636 + /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS) 2637 + 2638 + #define UV1H_SCRATCH5_ALIAS_32 0x780 2639 + #define UV2H_SCRATCH5_ALIAS_32 0x780 2640 + #define UV3H_SCRATCH5_ALIAS_32 0x780 2641 + #define UV4H_SCRATCH5_ALIAS_32 0x7a0 2642 + #define UVH_SCRATCH5_ALIAS_32 ( \ 2643 + is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_32 : \ 2644 + is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_32 : \ 2645 + is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_32 : \ 2646 + /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_32) 3630 2647 3631 2648 3632 2649 /* ========================================================================= */ 3633 2650 /* UVH_SCRATCH5_ALIAS_2 */ 3634 2651 /* ========================================================================= */ 3635 - #define UVH_SCRATCH5_ALIAS_2 0x2d0210UL 2652 + #define UV1H_SCRATCH5_ALIAS_2 0x2d0210UL 2653 + #define UV2H_SCRATCH5_ALIAS_2 0x2d0210UL 2654 + #define UV3H_SCRATCH5_ALIAS_2 0x2d0210UL 2655 + #define UV4H_SCRATCH5_ALIAS_2 0xb0210UL 2656 + #define UVH_SCRATCH5_ALIAS_2 ( \ 2657 + is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_2 : \ 2658 + is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_2 : \ 2659 + is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_2 : \ 2660 + /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_2) 3636 2661 #define UVH_SCRATCH5_ALIAS_2_32 0x788 3637 2662 3638 2663 ··· 3665 2640 /* UVXH_EVENT_OCCURRED2 */ 3666 2641 /* ========================================================================= */ 3667 2642 #define UVXH_EVENT_OCCURRED2 0x70100UL 3668 - #define UVXH_EVENT_OCCURRED2_32 0xb68 3669 2643 3670 - #define UVXH_EVENT_OCCURRED2_RTC_0_SHFT 0 3671 - #define UVXH_EVENT_OCCURRED2_RTC_1_SHFT 1 3672 - #define UVXH_EVENT_OCCURRED2_RTC_2_SHFT 2 3673 - #define UVXH_EVENT_OCCURRED2_RTC_3_SHFT 3 3674 - #define UVXH_EVENT_OCCURRED2_RTC_4_SHFT 4 3675 - #define UVXH_EVENT_OCCURRED2_RTC_5_SHFT 5 3676 - #define UVXH_EVENT_OCCURRED2_RTC_6_SHFT 6 3677 - #define UVXH_EVENT_OCCURRED2_RTC_7_SHFT 7 3678 - #define UVXH_EVENT_OCCURRED2_RTC_8_SHFT 8 3679 - #define UVXH_EVENT_OCCURRED2_RTC_9_SHFT 9 3680 - #define UVXH_EVENT_OCCURRED2_RTC_10_SHFT 10 3681 - #define UVXH_EVENT_OCCURRED2_RTC_11_SHFT 11 3682 - #define UVXH_EVENT_OCCURRED2_RTC_12_SHFT 12 3683 - #define UVXH_EVENT_OCCURRED2_RTC_13_SHFT 13 3684 - #define UVXH_EVENT_OCCURRED2_RTC_14_SHFT 14 3685 - #define UVXH_EVENT_OCCURRED2_RTC_15_SHFT 15 3686 - #define UVXH_EVENT_OCCURRED2_RTC_16_SHFT 16 3687 - #define UVXH_EVENT_OCCURRED2_RTC_17_SHFT 17 3688 - #define UVXH_EVENT_OCCURRED2_RTC_18_SHFT 18 3689 - #define UVXH_EVENT_OCCURRED2_RTC_19_SHFT 19 3690 - #define UVXH_EVENT_OCCURRED2_RTC_20_SHFT 20 3691 - #define UVXH_EVENT_OCCURRED2_RTC_21_SHFT 21 3692 - #define UVXH_EVENT_OCCURRED2_RTC_22_SHFT 22 3693 - #define UVXH_EVENT_OCCURRED2_RTC_23_SHFT 23 3694 - #define UVXH_EVENT_OCCURRED2_RTC_24_SHFT 24 3695 - #define UVXH_EVENT_OCCURRED2_RTC_25_SHFT 25 3696 - #define UVXH_EVENT_OCCURRED2_RTC_26_SHFT 26 3697 - #define UVXH_EVENT_OCCURRED2_RTC_27_SHFT 27 3698 - #define UVXH_EVENT_OCCURRED2_RTC_28_SHFT 28 3699 - #define UVXH_EVENT_OCCURRED2_RTC_29_SHFT 29 3700 - #define UVXH_EVENT_OCCURRED2_RTC_30_SHFT 30 3701 - #define UVXH_EVENT_OCCURRED2_RTC_31_SHFT 31 3702 - #define UVXH_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 3703 - #define UVXH_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 3704 - #define UVXH_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 3705 - #define UVXH_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 3706 - #define UVXH_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 3707 - #define UVXH_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 3708 - #define UVXH_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 3709 - #define UVXH_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 3710 - #define UVXH_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 3711 - #define UVXH_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 3712 - #define UVXH_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 3713 - #define UVXH_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 3714 - #define UVXH_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 3715 - #define UVXH_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 3716 - #define UVXH_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 3717 - #define UVXH_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 3718 - #define UVXH_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 3719 - #define UVXH_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 3720 - #define UVXH_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 3721 - #define UVXH_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 3722 - #define UVXH_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 3723 - #define UVXH_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 3724 - #define UVXH_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 3725 - #define UVXH_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 3726 - #define UVXH_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 3727 - #define UVXH_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 3728 - #define UVXH_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 3729 - #define UVXH_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 3730 - #define UVXH_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 3731 - #define UVXH_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 3732 - #define UVXH_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 3733 - #define UVXH_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 2644 + #define UV2H_EVENT_OCCURRED2_32 0xb68 2645 + #define UV3H_EVENT_OCCURRED2_32 0xb68 2646 + #define UV4H_EVENT_OCCURRED2_32 0x608 2647 + #define UVH_EVENT_OCCURRED2_32 ( \ 2648 + is_uv2_hub() ? UV2H_EVENT_OCCURRED2_32 : \ 2649 + is_uv3_hub() ? UV3H_EVENT_OCCURRED2_32 : \ 2650 + /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_32) 3734 2651 3735 - union uvxh_event_occurred2_u { 2652 + 2653 + #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0 2654 + #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1 2655 + #define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2 2656 + #define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3 2657 + #define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4 2658 + #define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5 2659 + #define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6 2660 + #define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7 2661 + #define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8 2662 + #define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9 2663 + #define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10 2664 + #define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11 2665 + #define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12 2666 + #define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13 2667 + #define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14 2668 + #define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15 2669 + #define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16 2670 + #define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17 2671 + #define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18 2672 + #define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19 2673 + #define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20 2674 + #define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21 2675 + #define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22 2676 + #define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23 2677 + #define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24 2678 + #define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25 2679 + #define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26 2680 + #define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27 2681 + #define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28 2682 + #define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29 2683 + #define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30 2684 + #define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31 2685 + #define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 2686 + #define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 2687 + #define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 2688 + #define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 2689 + #define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 2690 + #define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 2691 + #define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 2692 + #define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 2693 + #define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 2694 + #define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 2695 + #define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 2696 + #define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 2697 + #define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 2698 + #define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 2699 + #define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 2700 + #define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 2701 + #define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 2702 + #define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 2703 + #define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 2704 + #define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 2705 + #define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 2706 + #define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 2707 + #define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 2708 + #define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 2709 + #define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 2710 + #define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 2711 + #define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 2712 + #define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 2713 + #define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 2714 + #define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 2715 + #define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 2716 + #define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 2717 + 2718 + #define UV3H_EVENT_OCCURRED2_RTC_0_SHFT 0 2719 + #define UV3H_EVENT_OCCURRED2_RTC_1_SHFT 1 2720 + #define UV3H_EVENT_OCCURRED2_RTC_2_SHFT 2 2721 + #define UV3H_EVENT_OCCURRED2_RTC_3_SHFT 3 2722 + #define UV3H_EVENT_OCCURRED2_RTC_4_SHFT 4 2723 + #define UV3H_EVENT_OCCURRED2_RTC_5_SHFT 5 2724 + #define UV3H_EVENT_OCCURRED2_RTC_6_SHFT 6 2725 + #define UV3H_EVENT_OCCURRED2_RTC_7_SHFT 7 2726 + #define UV3H_EVENT_OCCURRED2_RTC_8_SHFT 8 2727 + #define UV3H_EVENT_OCCURRED2_RTC_9_SHFT 9 2728 + #define UV3H_EVENT_OCCURRED2_RTC_10_SHFT 10 2729 + #define UV3H_EVENT_OCCURRED2_RTC_11_SHFT 11 2730 + #define UV3H_EVENT_OCCURRED2_RTC_12_SHFT 12 2731 + #define UV3H_EVENT_OCCURRED2_RTC_13_SHFT 13 2732 + #define UV3H_EVENT_OCCURRED2_RTC_14_SHFT 14 2733 + #define UV3H_EVENT_OCCURRED2_RTC_15_SHFT 15 2734 + #define UV3H_EVENT_OCCURRED2_RTC_16_SHFT 16 2735 + #define UV3H_EVENT_OCCURRED2_RTC_17_SHFT 17 2736 + #define UV3H_EVENT_OCCURRED2_RTC_18_SHFT 18 2737 + #define UV3H_EVENT_OCCURRED2_RTC_19_SHFT 19 2738 + #define UV3H_EVENT_OCCURRED2_RTC_20_SHFT 20 2739 + #define UV3H_EVENT_OCCURRED2_RTC_21_SHFT 21 2740 + #define UV3H_EVENT_OCCURRED2_RTC_22_SHFT 22 2741 + #define UV3H_EVENT_OCCURRED2_RTC_23_SHFT 23 2742 + #define UV3H_EVENT_OCCURRED2_RTC_24_SHFT 24 2743 + #define UV3H_EVENT_OCCURRED2_RTC_25_SHFT 25 2744 + #define UV3H_EVENT_OCCURRED2_RTC_26_SHFT 26 2745 + #define UV3H_EVENT_OCCURRED2_RTC_27_SHFT 27 2746 + #define UV3H_EVENT_OCCURRED2_RTC_28_SHFT 28 2747 + #define UV3H_EVENT_OCCURRED2_RTC_29_SHFT 29 2748 + #define UV3H_EVENT_OCCURRED2_RTC_30_SHFT 30 2749 + #define UV3H_EVENT_OCCURRED2_RTC_31_SHFT 31 2750 + #define UV3H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 2751 + #define UV3H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 2752 + #define UV3H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 2753 + #define UV3H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 2754 + #define UV3H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 2755 + #define UV3H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 2756 + #define UV3H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 2757 + #define UV3H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 2758 + #define UV3H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 2759 + #define UV3H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 2760 + #define UV3H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 2761 + #define UV3H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 2762 + #define UV3H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 2763 + #define UV3H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 2764 + #define UV3H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 2765 + #define UV3H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 2766 + #define UV3H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 2767 + #define UV3H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 2768 + #define UV3H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 2769 + #define UV3H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 2770 + #define UV3H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 2771 + #define UV3H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 2772 + #define UV3H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 2773 + #define UV3H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 2774 + #define UV3H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 2775 + #define UV3H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 2776 + #define UV3H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 2777 + #define UV3H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 2778 + #define UV3H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 2779 + #define UV3H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 2780 + #define UV3H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 2781 + #define UV3H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 2782 + 2783 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_SHFT 0 2784 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_SHFT 1 2785 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_SHFT 2 2786 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_SHFT 3 2787 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_SHFT 4 2788 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_SHFT 5 2789 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_SHFT 6 2790 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_SHFT 7 2791 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_SHFT 8 2792 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_SHFT 9 2793 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_SHFT 10 2794 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_SHFT 11 2795 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_SHFT 12 2796 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_SHFT 13 2797 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_SHFT 14 2798 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_SHFT 15 2799 + #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT 16 2800 + #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT 17 2801 + #define UV4H_EVENT_OCCURRED2_RTC_0_SHFT 18 2802 + #define UV4H_EVENT_OCCURRED2_RTC_1_SHFT 19 2803 + #define UV4H_EVENT_OCCURRED2_RTC_2_SHFT 20 2804 + #define UV4H_EVENT_OCCURRED2_RTC_3_SHFT 21 2805 + #define UV4H_EVENT_OCCURRED2_RTC_4_SHFT 22 2806 + #define UV4H_EVENT_OCCURRED2_RTC_5_SHFT 23 2807 + #define UV4H_EVENT_OCCURRED2_RTC_6_SHFT 24 2808 + #define UV4H_EVENT_OCCURRED2_RTC_7_SHFT 25 2809 + #define UV4H_EVENT_OCCURRED2_RTC_8_SHFT 26 2810 + #define UV4H_EVENT_OCCURRED2_RTC_9_SHFT 27 2811 + #define UV4H_EVENT_OCCURRED2_RTC_10_SHFT 28 2812 + #define UV4H_EVENT_OCCURRED2_RTC_11_SHFT 29 2813 + #define UV4H_EVENT_OCCURRED2_RTC_12_SHFT 30 2814 + #define UV4H_EVENT_OCCURRED2_RTC_13_SHFT 31 2815 + #define UV4H_EVENT_OCCURRED2_RTC_14_SHFT 32 2816 + #define UV4H_EVENT_OCCURRED2_RTC_15_SHFT 33 2817 + #define UV4H_EVENT_OCCURRED2_RTC_16_SHFT 34 2818 + #define UV4H_EVENT_OCCURRED2_RTC_17_SHFT 35 2819 + #define UV4H_EVENT_OCCURRED2_RTC_18_SHFT 36 2820 + #define UV4H_EVENT_OCCURRED2_RTC_19_SHFT 37 2821 + #define UV4H_EVENT_OCCURRED2_RTC_20_SHFT 38 2822 + #define UV4H_EVENT_OCCURRED2_RTC_21_SHFT 39 2823 + #define UV4H_EVENT_OCCURRED2_RTC_22_SHFT 40 2824 + #define UV4H_EVENT_OCCURRED2_RTC_23_SHFT 41 2825 + #define UV4H_EVENT_OCCURRED2_RTC_24_SHFT 42 2826 + #define UV4H_EVENT_OCCURRED2_RTC_25_SHFT 43 2827 + #define UV4H_EVENT_OCCURRED2_RTC_26_SHFT 44 2828 + #define UV4H_EVENT_OCCURRED2_RTC_27_SHFT 45 2829 + #define UV4H_EVENT_OCCURRED2_RTC_28_SHFT 46 2830 + #define UV4H_EVENT_OCCURRED2_RTC_29_SHFT 47 2831 + #define UV4H_EVENT_OCCURRED2_RTC_30_SHFT 48 2832 + #define UV4H_EVENT_OCCURRED2_RTC_31_SHFT 49 2833 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000001UL 2834 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000002UL 2835 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000004UL 2836 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000008UL 2837 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000010UL 2838 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000020UL 2839 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000040UL 2840 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000080UL 2841 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000100UL 2842 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000200UL 2843 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000000400UL 2844 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000000800UL 2845 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000001000UL 2846 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000002000UL 2847 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000004000UL 2848 + #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000008000UL 2849 + #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK 0x0000000000010000UL 2850 + #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK 0x0000000000020000UL 2851 + #define UV4H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000040000UL 2852 + #define UV4H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000080000UL 2853 + #define UV4H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000100000UL 2854 + #define UV4H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000200000UL 2855 + #define UV4H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000400000UL 2856 + #define UV4H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000800000UL 2857 + #define UV4H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000001000000UL 2858 + #define UV4H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000002000000UL 2859 + #define UV4H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000004000000UL 2860 + #define UV4H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000008000000UL 2861 + #define UV4H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000010000000UL 2862 + #define UV4H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000020000000UL 2863 + #define UV4H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000040000000UL 2864 + #define UV4H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000080000000UL 2865 + #define UV4H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000100000000UL 2866 + #define UV4H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000200000000UL 2867 + #define UV4H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000400000000UL 2868 + #define UV4H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000800000000UL 2869 + #define UV4H_EVENT_OCCURRED2_RTC_18_MASK 0x0000001000000000UL 2870 + #define UV4H_EVENT_OCCURRED2_RTC_19_MASK 0x0000002000000000UL 2871 + #define UV4H_EVENT_OCCURRED2_RTC_20_MASK 0x0000004000000000UL 2872 + #define UV4H_EVENT_OCCURRED2_RTC_21_MASK 0x0000008000000000UL 2873 + #define UV4H_EVENT_OCCURRED2_RTC_22_MASK 0x0000010000000000UL 2874 + #define UV4H_EVENT_OCCURRED2_RTC_23_MASK 0x0000020000000000UL 2875 + #define UV4H_EVENT_OCCURRED2_RTC_24_MASK 0x0000040000000000UL 2876 + #define UV4H_EVENT_OCCURRED2_RTC_25_MASK 0x0000080000000000UL 2877 + #define UV4H_EVENT_OCCURRED2_RTC_26_MASK 0x0000100000000000UL 2878 + #define UV4H_EVENT_OCCURRED2_RTC_27_MASK 0x0000200000000000UL 2879 + #define UV4H_EVENT_OCCURRED2_RTC_28_MASK 0x0000400000000000UL 2880 + #define UV4H_EVENT_OCCURRED2_RTC_29_MASK 0x0000800000000000UL 2881 + #define UV4H_EVENT_OCCURRED2_RTC_30_MASK 0x0001000000000000UL 2882 + #define UV4H_EVENT_OCCURRED2_RTC_31_MASK 0x0002000000000000UL 2883 + 2884 + #define UVXH_EVENT_OCCURRED2_RTC_1_MASK ( \ 2885 + is_uv2_hub() ? UV2H_EVENT_OCCURRED2_RTC_1_MASK : \ 2886 + is_uv3_hub() ? UV3H_EVENT_OCCURRED2_RTC_1_MASK : \ 2887 + /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_RTC_1_MASK) 2888 + 2889 + union uvh_event_occurred2_u { 3736 2890 unsigned long v; 3737 - struct uvxh_event_occurred2_s { 2891 + struct uv2h_event_occurred2_s { 3738 2892 unsigned long rtc_0:1; /* RW */ 3739 2893 unsigned long rtc_1:1; /* RW */ 3740 2894 unsigned long rtc_2:1; /* RW */ ··· 3947 2743 unsigned long rtc_30:1; /* RW */ 3948 2744 unsigned long rtc_31:1; /* RW */ 3949 2745 unsigned long rsvd_32_63:32; 3950 - } sx; 2746 + } s2; 2747 + struct uv3h_event_occurred2_s { 2748 + unsigned long rtc_0:1; /* RW */ 2749 + unsigned long rtc_1:1; /* RW */ 2750 + unsigned long rtc_2:1; /* RW */ 2751 + unsigned long rtc_3:1; /* RW */ 2752 + unsigned long rtc_4:1; /* RW */ 2753 + unsigned long rtc_5:1; /* RW */ 2754 + unsigned long rtc_6:1; /* RW */ 2755 + unsigned long rtc_7:1; /* RW */ 2756 + unsigned long rtc_8:1; /* RW */ 2757 + unsigned long rtc_9:1; /* RW */ 2758 + unsigned long rtc_10:1; /* RW */ 2759 + unsigned long rtc_11:1; /* RW */ 2760 + unsigned long rtc_12:1; /* RW */ 2761 + unsigned long rtc_13:1; /* RW */ 2762 + unsigned long rtc_14:1; /* RW */ 2763 + unsigned long rtc_15:1; /* RW */ 2764 + unsigned long rtc_16:1; /* RW */ 2765 + unsigned long rtc_17:1; /* RW */ 2766 + unsigned long rtc_18:1; /* RW */ 2767 + unsigned long rtc_19:1; /* RW */ 2768 + unsigned long rtc_20:1; /* RW */ 2769 + unsigned long rtc_21:1; /* RW */ 2770 + unsigned long rtc_22:1; /* RW */ 2771 + unsigned long rtc_23:1; /* RW */ 2772 + unsigned long rtc_24:1; /* RW */ 2773 + unsigned long rtc_25:1; /* RW */ 2774 + unsigned long rtc_26:1; /* RW */ 2775 + unsigned long rtc_27:1; /* RW */ 2776 + unsigned long rtc_28:1; /* RW */ 2777 + unsigned long rtc_29:1; /* RW */ 2778 + unsigned long rtc_30:1; /* RW */ 2779 + unsigned long rtc_31:1; /* RW */ 2780 + unsigned long rsvd_32_63:32; 2781 + } s3; 2782 + struct uv4h_event_occurred2_s { 2783 + unsigned long message_accelerator_int0:1; /* RW */ 2784 + unsigned long message_accelerator_int1:1; /* RW */ 2785 + unsigned long message_accelerator_int2:1; /* RW */ 2786 + unsigned long message_accelerator_int3:1; /* RW */ 2787 + unsigned long message_accelerator_int4:1; /* RW */ 2788 + unsigned long message_accelerator_int5:1; /* RW */ 2789 + unsigned long message_accelerator_int6:1; /* RW */ 2790 + unsigned long message_accelerator_int7:1; /* RW */ 2791 + unsigned long message_accelerator_int8:1; /* RW */ 2792 + unsigned long message_accelerator_int9:1; /* RW */ 2793 + unsigned long message_accelerator_int10:1; /* RW */ 2794 + unsigned long message_accelerator_int11:1; /* RW */ 2795 + unsigned long message_accelerator_int12:1; /* RW */ 2796 + unsigned long message_accelerator_int13:1; /* RW */ 2797 + unsigned long message_accelerator_int14:1; /* RW */ 2798 + unsigned long message_accelerator_int15:1; /* RW */ 2799 + unsigned long rtc_interval_int:1; /* RW */ 2800 + unsigned long bau_dashboard_int:1; /* RW */ 2801 + unsigned long rtc_0:1; /* RW */ 2802 + unsigned long rtc_1:1; /* RW */ 2803 + unsigned long rtc_2:1; /* RW */ 2804 + unsigned long rtc_3:1; /* RW */ 2805 + unsigned long rtc_4:1; /* RW */ 2806 + unsigned long rtc_5:1; /* RW */ 2807 + unsigned long rtc_6:1; /* RW */ 2808 + unsigned long rtc_7:1; /* RW */ 2809 + unsigned long rtc_8:1; /* RW */ 2810 + unsigned long rtc_9:1; /* RW */ 2811 + unsigned long rtc_10:1; /* RW */ 2812 + unsigned long rtc_11:1; /* RW */ 2813 + unsigned long rtc_12:1; /* RW */ 2814 + unsigned long rtc_13:1; /* RW */ 2815 + unsigned long rtc_14:1; /* RW */ 2816 + unsigned long rtc_15:1; /* RW */ 2817 + unsigned long rtc_16:1; /* RW */ 2818 + unsigned long rtc_17:1; /* RW */ 2819 + unsigned long rtc_18:1; /* RW */ 2820 + unsigned long rtc_19:1; /* RW */ 2821 + unsigned long rtc_20:1; /* RW */ 2822 + unsigned long rtc_21:1; /* RW */ 2823 + unsigned long rtc_22:1; /* RW */ 2824 + unsigned long rtc_23:1; /* RW */ 2825 + unsigned long rtc_24:1; /* RW */ 2826 + unsigned long rtc_25:1; /* RW */ 2827 + unsigned long rtc_26:1; /* RW */ 2828 + unsigned long rtc_27:1; /* RW */ 2829 + unsigned long rtc_28:1; /* RW */ 2830 + unsigned long rtc_29:1; /* RW */ 2831 + unsigned long rtc_30:1; /* RW */ 2832 + unsigned long rtc_31:1; /* RW */ 2833 + unsigned long rsvd_50_63:14; 2834 + } s4; 3951 2835 }; 3952 2836 3953 2837 /* ========================================================================= */ 3954 2838 /* UVXH_EVENT_OCCURRED2_ALIAS */ 3955 2839 /* ========================================================================= */ 3956 2840 #define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL 3957 - #define UVXH_EVENT_OCCURRED2_ALIAS_32 0xb70 2841 + 2842 + #define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70 2843 + #define UV3H_EVENT_OCCURRED2_ALIAS_32 0xb70 2844 + #define UV4H_EVENT_OCCURRED2_ALIAS_32 0x610 2845 + #define UVH_EVENT_OCCURRED2_ALIAS_32 ( \ 2846 + is_uv2_hub() ? UV2H_EVENT_OCCURRED2_ALIAS_32 : \ 2847 + is_uv3_hub() ? UV3H_EVENT_OCCURRED2_ALIAS_32 : \ 2848 + /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_ALIAS_32) 3958 2849 3959 2850 3960 2851 /* ========================================================================= */ 3961 2852 /* UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 */ 3962 2853 /* ========================================================================= */ 3963 - #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 3964 2854 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 3965 2855 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 3966 - #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 3967 - #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL 3968 - #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL 2856 + #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2 0xc8130UL 2857 + #define UVH_LB_BAU_SB_ACTIVATION_STATUS_2 ( \ 2858 + is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 : \ 2859 + is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 : \ 2860 + /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2) 2861 + 2862 + #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 2863 + #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 2864 + #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0xa10 2865 + #define UVH_LB_BAU_SB_ACTIVATION_STATUS_2_32 ( \ 2866 + is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 : \ 2867 + is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 : \ 2868 + /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32) 3969 2869 3970 2870 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 3971 2871 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL ··· 4079 2771 4080 2772 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4081 2773 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 2774 + 2775 + #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 2776 + #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 2777 + 4082 2778 4083 2779 union uvxh_lb_bau_sb_activation_status_2_u { 4084 2780 unsigned long v; ··· 4095 2783 struct uv3h_lb_bau_sb_activation_status_2_s { 4096 2784 unsigned long aux_error:64; /* RW */ 4097 2785 } s3; 2786 + struct uv4h_lb_bau_sb_activation_status_2_s { 2787 + unsigned long aux_error:64; /* RW */ 2788 + } s4; 4098 2789 }; 4099 2790 4100 2791 /* ========================================================================= */ ··· 4130 2815 union uv3h_gr0_gam_gr_config_u { 4131 2816 unsigned long v; 4132 2817 struct uv3h_gr0_gam_gr_config_s { 4133 - unsigned long m_skt:6; /* RW */ 4134 - unsigned long undef_6_9:4; /* Undefined */ 4135 - unsigned long subspace:1; /* RW */ 4136 - unsigned long reserved:53; 4137 - } s3; 4138 - }; 4139 - 4140 - /* ========================================================================= */ 4141 - /* UV3H_GR1_GAM_GR_CONFIG */ 4142 - /* ========================================================================= */ 4143 - #define UV3H_GR1_GAM_GR_CONFIG 0x1000028UL 4144 - 4145 - #define UV3H_GR1_GAM_GR_CONFIG_M_SKT_SHFT 0 4146 - #define UV3H_GR1_GAM_GR_CONFIG_SUBSPACE_SHFT 10 4147 - #define UV3H_GR1_GAM_GR_CONFIG_M_SKT_MASK 0x000000000000003fUL 4148 - #define UV3H_GR1_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL 4149 - 4150 - union uv3h_gr1_gam_gr_config_u { 4151 - unsigned long v; 4152 - struct uv3h_gr1_gam_gr_config_s { 4153 2818 unsigned long m_skt:6; /* RW */ 4154 2819 unsigned long undef_6_9:4; /* Undefined */ 4155 2820 unsigned long subspace:1; /* RW */ ··· 4217 2922 unsigned long nasid:15; /* RW */ 4218 2923 unsigned long rsvd_15_63:49; 4219 2924 } s3; 2925 + }; 2926 + 2927 + /* ========================================================================= */ 2928 + /* UV4H_LB_PROC_INTD_QUEUE_FIRST */ 2929 + /* ========================================================================= */ 2930 + #define UV4H_LB_PROC_INTD_QUEUE_FIRST 0xa4100UL 2931 + 2932 + #define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_SHFT 6 2933 + #define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffc0UL 2934 + 2935 + union uv4h_lb_proc_intd_queue_first_u { 2936 + unsigned long v; 2937 + struct uv4h_lb_proc_intd_queue_first_s { 2938 + unsigned long undef_0_5:6; /* Undefined */ 2939 + unsigned long first_payload_address:40; /* RW */ 2940 + } s4; 2941 + }; 2942 + 2943 + /* ========================================================================= */ 2944 + /* UV4H_LB_PROC_INTD_QUEUE_LAST */ 2945 + /* ========================================================================= */ 2946 + #define UV4H_LB_PROC_INTD_QUEUE_LAST 0xa4108UL 2947 + 2948 + #define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_SHFT 5 2949 + #define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffe0UL 2950 + 2951 + union uv4h_lb_proc_intd_queue_last_u { 2952 + unsigned long v; 2953 + struct uv4h_lb_proc_intd_queue_last_s { 2954 + unsigned long undef_0_4:5; /* Undefined */ 2955 + unsigned long last_payload_address:41; /* RW */ 2956 + } s4; 2957 + }; 2958 + 2959 + /* ========================================================================= */ 2960 + /* UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR */ 2961 + /* ========================================================================= */ 2962 + #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR 0xa4118UL 2963 + 2964 + #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_SHFT 0 2965 + #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_MASK 0x00000000000000ffUL 2966 + 2967 + union uv4h_lb_proc_intd_soft_ack_clear_u { 2968 + unsigned long v; 2969 + struct uv4h_lb_proc_intd_soft_ack_clear_s { 2970 + unsigned long soft_ack_pending_flags:8; /* WP */ 2971 + } s4; 2972 + }; 2973 + 2974 + /* ========================================================================= */ 2975 + /* UV4H_LB_PROC_INTD_SOFT_ACK_PENDING */ 2976 + /* ========================================================================= */ 2977 + #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING 0xa4110UL 2978 + 2979 + #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_SHFT 0 2980 + #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_MASK 0x00000000000000ffUL 2981 + 2982 + union uv4h_lb_proc_intd_soft_ack_pending_u { 2983 + unsigned long v; 2984 + struct uv4h_lb_proc_intd_soft_ack_pending_s { 2985 + unsigned long soft_ack_flags:8; /* RW */ 2986 + } s4; 4220 2987 }; 4221 2988 4222 2989
+673 -189
arch/x86/kernel/apic/x2apic_uv_x.c
··· 48 48 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr; 49 49 static u64 gru_dist_lmask, gru_dist_umask; 50 50 static union uvh_apicid uvh_apicid; 51 + 52 + /* info derived from CPUID */ 53 + static struct { 54 + unsigned int apicid_shift; 55 + unsigned int apicid_mask; 56 + unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */ 57 + unsigned int pnode_mask; 58 + unsigned int gpa_shift; 59 + } uv_cpuid; 60 + 51 61 int uv_min_hub_revision_id; 52 62 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); 53 63 unsigned int uv_apicid_hibits; 54 64 EXPORT_SYMBOL_GPL(uv_apicid_hibits); 55 65 56 66 static struct apic apic_x2apic_uv_x; 67 + static struct uv_hub_info_s uv_hub_info_node0; 68 + 69 + /* Set this to use hardware error handler instead of kernel panic */ 70 + static int disable_uv_undefined_panic = 1; 71 + unsigned long uv_undefined(char *str) 72 + { 73 + if (likely(!disable_uv_undefined_panic)) 74 + panic("UV: error: undefined MMR: %s\n", str); 75 + else 76 + pr_crit("UV: error: undefined MMR: %s\n", str); 77 + return ~0ul; /* cause a machine fault */ 78 + } 79 + EXPORT_SYMBOL(uv_undefined); 57 80 58 81 static unsigned long __init uv_early_read_mmr(unsigned long addr) 59 82 { ··· 131 108 case UV3_HUB_PART_NUMBER_X: 132 109 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE; 133 110 break; 111 + case UV4_HUB_PART_NUMBER: 112 + uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1; 113 + break; 134 114 } 135 115 136 116 uv_hub_info->hub_revision = uv_min_hub_revision_id; 137 - pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1); 117 + uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1; 118 + pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask; 119 + uv_cpuid.gpa_shift = 46; /* default unless changed */ 120 + 121 + pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n", 122 + node_id.s.revision, node_id.s.part_number, node_id.s.node_id, 123 + m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode); 138 124 return pnode; 139 125 } 140 126 141 - static void __init early_get_apic_pnode_shift(void) 127 + /* [copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */ 128 + #define SMT_LEVEL 0 /* leaf 0xb SMT level */ 129 + #define INVALID_TYPE 0 /* leaf 0xb sub-leaf types */ 130 + #define SMT_TYPE 1 131 + #define CORE_TYPE 2 132 + #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff) 133 + #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) 134 + 135 + static void set_x2apic_bits(void) 142 136 { 143 - uvh_apicid.v = uv_early_read_mmr(UVH_APICID); 144 - if (!uvh_apicid.v) 145 - /* 146 - * Old bios, use default value 147 - */ 148 - uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT; 137 + unsigned int eax, ebx, ecx, edx, sub_index; 138 + unsigned int sid_shift; 139 + 140 + cpuid(0, &eax, &ebx, &ecx, &edx); 141 + if (eax < 0xb) { 142 + pr_info("UV: CPU does not have CPUID.11\n"); 143 + return; 144 + } 145 + cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); 146 + if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) { 147 + pr_info("UV: CPUID.11 not implemented\n"); 148 + return; 149 + } 150 + sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 151 + sub_index = 1; 152 + do { 153 + cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx); 154 + if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) { 155 + sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 156 + break; 157 + } 158 + sub_index++; 159 + } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE); 160 + uv_cpuid.apicid_shift = 0; 161 + uv_cpuid.apicid_mask = (~(-1 << sid_shift)); 162 + uv_cpuid.socketid_shift = sid_shift; 163 + } 164 + 165 + static void __init early_get_apic_socketid_shift(void) 166 + { 167 + if (is_uv2_hub() || is_uv3_hub()) 168 + uvh_apicid.v = uv_early_read_mmr(UVH_APICID); 169 + 170 + set_x2apic_bits(); 171 + 172 + pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", 173 + uv_cpuid.apicid_shift, uv_cpuid.apicid_mask); 174 + pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", 175 + uv_cpuid.socketid_shift, uv_cpuid.pnode_mask); 149 176 } 150 177 151 178 /* ··· 223 150 if (strncmp(oem_id, "SGI", 3) != 0) 224 151 return 0; 225 152 153 + /* Setup early hub type field in uv_hub_info for Node 0 */ 154 + uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0; 155 + 226 156 /* 227 157 * Determine UV arch type. 228 158 * SGI: UV100/1000 229 159 * SGI2: UV2000/3000 230 160 * SGI3: UV300 (truncated to 4 chars because of different varieties) 161 + * SGI4: UV400 (truncated to 4 chars because of different varieties) 231 162 */ 232 163 uv_hub_info->hub_revision = 164 + !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE : 233 165 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE : 234 166 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE : 235 167 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0; ··· 243 165 goto badbios; 244 166 245 167 pnodeid = early_get_pnodeid(); 246 - early_get_apic_pnode_shift(); 168 + early_get_apic_socketid_shift(); 247 169 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; 248 170 x86_platform.nmi_init = uv_nmi_init; 249 171 ··· 289 211 } 290 212 EXPORT_SYMBOL_GPL(is_uv_system); 291 213 292 - DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 293 - EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); 214 + void **__uv_hub_info_list; 215 + EXPORT_SYMBOL_GPL(__uv_hub_info_list); 294 216 295 - struct uv_blade_info *uv_blade_info; 296 - EXPORT_SYMBOL_GPL(uv_blade_info); 297 - 298 - short *uv_node_to_blade; 299 - EXPORT_SYMBOL_GPL(uv_node_to_blade); 300 - 301 - short *uv_cpu_to_blade; 302 - EXPORT_SYMBOL_GPL(uv_cpu_to_blade); 217 + DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 218 + EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info); 303 219 304 220 short uv_possible_blades; 305 221 EXPORT_SYMBOL_GPL(uv_possible_blades); 306 222 307 223 unsigned long sn_rtc_cycles_per_second; 308 224 EXPORT_SYMBOL(sn_rtc_cycles_per_second); 225 + 226 + /* the following values are used for the per node hub info struct */ 227 + static __initdata unsigned short *_node_to_pnode; 228 + static __initdata unsigned short _min_socket, _max_socket; 229 + static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len; 230 + static __initdata struct uv_gam_range_entry *uv_gre_table; 231 + static __initdata struct uv_gam_parameters *uv_gp_table; 232 + static __initdata unsigned short *_socket_to_node; 233 + static __initdata unsigned short *_socket_to_pnode; 234 + static __initdata unsigned short *_pnode_to_socket; 235 + static __initdata struct uv_gam_range_s *_gr_table; 236 + #define SOCK_EMPTY ((unsigned short)~0) 237 + 238 + extern int uv_hub_info_version(void) 239 + { 240 + return UV_HUB_INFO_VERSION; 241 + } 242 + EXPORT_SYMBOL(uv_hub_info_version); 243 + 244 + /* Build GAM range lookup table */ 245 + static __init void build_uv_gr_table(void) 246 + { 247 + struct uv_gam_range_entry *gre = uv_gre_table; 248 + struct uv_gam_range_s *grt; 249 + unsigned long last_limit = 0, ram_limit = 0; 250 + int bytes, i, sid, lsid = -1; 251 + 252 + if (!gre) 253 + return; 254 + 255 + bytes = _gr_table_len * sizeof(struct uv_gam_range_s); 256 + grt = kzalloc(bytes, GFP_KERNEL); 257 + BUG_ON(!grt); 258 + _gr_table = grt; 259 + 260 + for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 261 + if (gre->type == UV_GAM_RANGE_TYPE_HOLE) { 262 + if (!ram_limit) { /* mark hole between ram/non-ram */ 263 + ram_limit = last_limit; 264 + last_limit = gre->limit; 265 + lsid++; 266 + continue; 267 + } 268 + last_limit = gre->limit; 269 + pr_info("UV: extra hole in GAM RE table @%d\n", 270 + (int)(gre - uv_gre_table)); 271 + continue; 272 + } 273 + if (_max_socket < gre->sockid) { 274 + pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", 275 + gre->sockid, _max_socket, 276 + (int)(gre - uv_gre_table)); 277 + continue; 278 + } 279 + sid = gre->sockid - _min_socket; 280 + if (lsid < sid) { /* new range */ 281 + grt = &_gr_table[sid]; 282 + grt->base = lsid; 283 + grt->nasid = gre->nasid; 284 + grt->limit = last_limit = gre->limit; 285 + lsid = sid; 286 + continue; 287 + } 288 + if (lsid == sid && !ram_limit) { /* update range */ 289 + if (grt->limit == last_limit) { /* .. if contiguous */ 290 + grt->limit = last_limit = gre->limit; 291 + continue; 292 + } 293 + } 294 + if (!ram_limit) { /* non-contiguous ram range */ 295 + grt++; 296 + grt->base = sid - 1; 297 + grt->nasid = gre->nasid; 298 + grt->limit = last_limit = gre->limit; 299 + continue; 300 + } 301 + grt++; /* non-contiguous/non-ram */ 302 + grt->base = grt - _gr_table; /* base is this entry */ 303 + grt->nasid = gre->nasid; 304 + grt->limit = last_limit = gre->limit; 305 + lsid++; 306 + } 307 + 308 + /* shorten table if possible */ 309 + grt++; 310 + i = grt - _gr_table; 311 + if (i < _gr_table_len) { 312 + void *ret; 313 + 314 + bytes = i * sizeof(struct uv_gam_range_s); 315 + ret = krealloc(_gr_table, bytes, GFP_KERNEL); 316 + if (ret) { 317 + _gr_table = ret; 318 + _gr_table_len = i; 319 + } 320 + } 321 + 322 + /* display resultant gam range table */ 323 + for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) { 324 + int gb = grt->base; 325 + unsigned long start = gb < 0 ? 0 : 326 + (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT; 327 + unsigned long end = 328 + (unsigned long)grt->limit << UV_GAM_RANGE_SHFT; 329 + 330 + pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", 331 + i, grt->nasid, start, end, gb); 332 + } 333 + } 309 334 310 335 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) 311 336 { ··· 536 355 537 356 static unsigned int uv_read_apic_id(void) 538 357 { 539 - 540 358 return x2apic_get_apic_id(apic_read(APIC_ID)); 541 359 } 542 360 ··· 610 430 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); 611 431 } 612 432 613 - /* 614 - * Called on boot cpu. 615 - */ 616 - static __init int boot_pnode_to_blade(int pnode) 617 - { 618 - int blade; 619 - 620 - for (blade = 0; blade < uv_num_possible_blades(); blade++) 621 - if (pnode == uv_blade_info[blade].pnode) 622 - return blade; 623 - BUG(); 624 - } 625 - 626 - struct redir_addr { 627 - unsigned long redirect; 628 - unsigned long alias; 629 - }; 630 - 433 + #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 631 434 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 632 - 633 - static __initdata struct redir_addr redir_addrs[] = { 634 - {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR}, 635 - {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR}, 636 - {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR}, 637 - }; 638 - 639 - static unsigned char get_n_lshift(int m_val) 640 - { 641 - union uv3h_gr0_gam_gr_config_u m_gr_config; 642 - 643 - if (is_uv1_hub()) 644 - return m_val; 645 - 646 - if (is_uv2_hub()) 647 - return m_val == 40 ? 40 : 39; 648 - 649 - m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG); 650 - return m_gr_config.s3.m_skt; 651 - } 652 435 653 436 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) 654 437 { 655 438 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; 656 439 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; 440 + unsigned long m_redirect; 441 + unsigned long m_overlay; 657 442 int i; 658 443 659 - for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) { 660 - alias.v = uv_read_local_mmr(redir_addrs[i].alias); 444 + for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) { 445 + switch (i) { 446 + case 0: 447 + m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR; 448 + m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR; 449 + break; 450 + case 1: 451 + m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR; 452 + m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR; 453 + break; 454 + case 2: 455 + m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR; 456 + m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR; 457 + break; 458 + } 459 + alias.v = uv_read_local_mmr(m_overlay); 661 460 if (alias.s.enable && alias.s.base == 0) { 662 461 *size = (1UL << alias.s.m_alias); 663 - redirect.v = uv_read_local_mmr(redir_addrs[i].redirect); 664 - *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; 462 + redirect.v = uv_read_local_mmr(m_redirect); 463 + *base = (unsigned long)redirect.s.dest_base 464 + << DEST_SHIFT; 665 465 return; 666 466 } 667 467 } ··· 704 544 { 705 545 union uvh_rh_gam_gru_overlay_config_mmr_u gru; 706 546 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; 547 + unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK; 548 + unsigned long base; 707 549 708 550 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); 709 551 if (!gru.s.enable) { ··· 717 555 map_gru_distributed(gru.v); 718 556 return; 719 557 } 720 - map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb); 721 - gru_start_paddr = ((u64)gru.s.base << shift); 558 + base = (gru.v & mask) >> shift; 559 + map_high("GRU", base, shift, shift, max_pnode, map_wb); 560 + gru_start_paddr = ((u64)base << shift); 722 561 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); 723 562 } 724 563 ··· 758 595 }, 759 596 }; 760 597 598 + /* UV3 & UV4 have identical MMIOH overlay configs */ 761 599 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode) 762 600 { 763 601 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay; ··· 838 674 unsigned long mmr, base; 839 675 int shift, enable, m_io, n_io; 840 676 841 - if (is_uv3_hub()) { 677 + if (is_uv3_hub() || is_uv4_hub()) { 842 678 /* Map both MMIOH Regions */ 843 679 map_mmioh_high_uv3(0, min_pnode, max_pnode); 844 680 map_mmioh_high_uv3(1, min_pnode, max_pnode); ··· 903 739 */ 904 740 static void uv_heartbeat(unsigned long ignored) 905 741 { 906 - struct timer_list *timer = &uv_hub_info->scir.timer; 907 - unsigned char bits = uv_hub_info->scir.state; 742 + struct timer_list *timer = &uv_scir_info->timer; 743 + unsigned char bits = uv_scir_info->state; 908 744 909 745 /* flip heartbeat bit */ 910 746 bits ^= SCIR_CPU_HEARTBEAT; ··· 924 760 925 761 static void uv_heartbeat_enable(int cpu) 926 762 { 927 - while (!uv_cpu_hub_info(cpu)->scir.enabled) { 928 - struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; 763 + while (!uv_cpu_scir_info(cpu)->enabled) { 764 + struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer; 929 765 930 766 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); 931 767 setup_timer(timer, uv_heartbeat, cpu); 932 768 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; 933 769 add_timer_on(timer, cpu); 934 - uv_cpu_hub_info(cpu)->scir.enabled = 1; 770 + uv_cpu_scir_info(cpu)->enabled = 1; 935 771 936 772 /* also ensure that boot cpu is enabled */ 937 773 cpu = 0; ··· 941 777 #ifdef CONFIG_HOTPLUG_CPU 942 778 static void uv_heartbeat_disable(int cpu) 943 779 { 944 - if (uv_cpu_hub_info(cpu)->scir.enabled) { 945 - uv_cpu_hub_info(cpu)->scir.enabled = 0; 946 - del_timer(&uv_cpu_hub_info(cpu)->scir.timer); 780 + if (uv_cpu_scir_info(cpu)->enabled) { 781 + uv_cpu_scir_info(cpu)->enabled = 0; 782 + del_timer(&uv_cpu_scir_info(cpu)->timer); 947 783 } 948 784 uv_set_cpu_scir_bits(cpu, 0xff); 949 785 } ··· 1026 862 void uv_cpu_init(void) 1027 863 { 1028 864 /* CPU 0 initialization will be done via uv_system_init. */ 1029 - if (!uv_blade_info) 865 + if (smp_processor_id() == 0) 1030 866 return; 1031 867 1032 - uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; 868 + uv_hub_info->nr_online_cpus++; 1033 869 1034 870 if (get_uv_system_type() == UV_NON_UNIQUE_APIC) 1035 871 set_x2apic_extra_bits(uv_hub_info->pnode); 1036 872 } 1037 873 874 + struct mn { 875 + unsigned char m_val; 876 + unsigned char n_val; 877 + unsigned char m_shift; 878 + unsigned char n_lshift; 879 + }; 880 + 881 + static void get_mn(struct mn *mnp) 882 + { 883 + union uvh_rh_gam_config_mmr_u m_n_config; 884 + union uv3h_gr0_gam_gr_config_u m_gr_config; 885 + 886 + m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR); 887 + mnp->n_val = m_n_config.s.n_skt; 888 + if (is_uv4_hub()) { 889 + mnp->m_val = 0; 890 + mnp->n_lshift = 0; 891 + } else if (is_uv3_hub()) { 892 + mnp->m_val = m_n_config.s3.m_skt; 893 + m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG); 894 + mnp->n_lshift = m_gr_config.s3.m_skt; 895 + } else if (is_uv2_hub()) { 896 + mnp->m_val = m_n_config.s2.m_skt; 897 + mnp->n_lshift = mnp->m_val == 40 ? 40 : 39; 898 + } else if (is_uv1_hub()) { 899 + mnp->m_val = m_n_config.s1.m_skt; 900 + mnp->n_lshift = mnp->m_val; 901 + } 902 + mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; 903 + } 904 + 905 + void __init uv_init_hub_info(struct uv_hub_info_s *hub_info) 906 + { 907 + struct mn mn = {0}; /* avoid unitialized warnings */ 908 + union uvh_node_id_u node_id; 909 + 910 + get_mn(&mn); 911 + hub_info->m_val = mn.m_val; 912 + hub_info->n_val = mn.n_val; 913 + hub_info->m_shift = mn.m_shift; 914 + hub_info->n_lshift = mn.n_lshift ? mn.n_lshift : 0; 915 + 916 + hub_info->hub_revision = uv_hub_info->hub_revision; 917 + hub_info->pnode_mask = uv_cpuid.pnode_mask; 918 + hub_info->min_pnode = _min_pnode; 919 + hub_info->min_socket = _min_socket; 920 + hub_info->pnode_to_socket = _pnode_to_socket; 921 + hub_info->socket_to_node = _socket_to_node; 922 + hub_info->socket_to_pnode = _socket_to_pnode; 923 + hub_info->gr_table_len = _gr_table_len; 924 + hub_info->gr_table = _gr_table; 925 + hub_info->gpa_mask = mn.m_val ? 926 + (1UL << (mn.m_val + mn.n_val)) - 1 : 927 + (1UL << uv_cpuid.gpa_shift) - 1; 928 + 929 + node_id.v = uv_read_local_mmr(UVH_NODE_ID); 930 + hub_info->gnode_extra = 931 + (node_id.s.node_id & ~((1 << mn.n_val) - 1)) >> 1; 932 + 933 + hub_info->gnode_upper = 934 + ((unsigned long)hub_info->gnode_extra << mn.m_val); 935 + 936 + if (uv_gp_table) { 937 + hub_info->global_mmr_base = uv_gp_table->mmr_base; 938 + hub_info->global_mmr_shift = uv_gp_table->mmr_shift; 939 + hub_info->global_gru_base = uv_gp_table->gru_base; 940 + hub_info->global_gru_shift = uv_gp_table->gru_shift; 941 + hub_info->gpa_shift = uv_gp_table->gpa_shift; 942 + hub_info->gpa_mask = (1UL << hub_info->gpa_shift) - 1; 943 + } else { 944 + hub_info->global_mmr_base = 945 + uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & 946 + ~UV_MMR_ENABLE; 947 + hub_info->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT; 948 + } 949 + 950 + get_lowmem_redirect( 951 + &hub_info->lowmem_remap_base, &hub_info->lowmem_remap_top); 952 + 953 + hub_info->apic_pnode_shift = uv_cpuid.socketid_shift; 954 + 955 + /* show system specific info */ 956 + pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", 957 + hub_info->n_val, hub_info->m_val, 958 + hub_info->m_shift, hub_info->n_lshift); 959 + 960 + pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", 961 + hub_info->gpa_mask, hub_info->gpa_shift, 962 + hub_info->pnode_mask, hub_info->apic_pnode_shift); 963 + 964 + pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", 965 + hub_info->global_mmr_base, hub_info->global_mmr_shift, 966 + hub_info->global_gru_base, hub_info->global_gru_shift); 967 + 968 + pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", 969 + hub_info->gnode_upper, hub_info->gnode_extra); 970 + } 971 + 972 + static void __init decode_gam_params(unsigned long ptr) 973 + { 974 + uv_gp_table = (struct uv_gam_parameters *)ptr; 975 + 976 + pr_info("UV: GAM Params...\n"); 977 + pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n", 978 + uv_gp_table->mmr_base, uv_gp_table->mmr_shift, 979 + uv_gp_table->gru_base, uv_gp_table->gru_shift, 980 + uv_gp_table->gpa_shift); 981 + } 982 + 983 + static void __init decode_gam_rng_tbl(unsigned long ptr) 984 + { 985 + struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr; 986 + unsigned long lgre = 0; 987 + int index = 0; 988 + int sock_min = 999999, pnode_min = 99999; 989 + int sock_max = -1, pnode_max = -1; 990 + 991 + uv_gre_table = gre; 992 + for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 993 + if (!index) { 994 + pr_info("UV: GAM Range Table...\n"); 995 + pr_info("UV: # %20s %14s %5s %4s %5s %3s %2s %3s\n", 996 + "Range", "", "Size", "Type", "NASID", 997 + "SID", "PN", "PXM"); 998 + } 999 + pr_info( 1000 + "UV: %2d: 0x%014lx-0x%014lx %5luG %3d %04x %02x %02x %3d\n", 1001 + index++, 1002 + (unsigned long)lgre << UV_GAM_RANGE_SHFT, 1003 + (unsigned long)gre->limit << UV_GAM_RANGE_SHFT, 1004 + ((unsigned long)(gre->limit - lgre)) >> 1005 + (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */ 1006 + gre->type, gre->nasid, gre->sockid, 1007 + gre->pnode, gre->pxm); 1008 + 1009 + lgre = gre->limit; 1010 + if (sock_min > gre->sockid) 1011 + sock_min = gre->sockid; 1012 + if (sock_max < gre->sockid) 1013 + sock_max = gre->sockid; 1014 + if (pnode_min > gre->pnode) 1015 + pnode_min = gre->pnode; 1016 + if (pnode_max < gre->pnode) 1017 + pnode_max = gre->pnode; 1018 + } 1019 + _min_socket = sock_min; 1020 + _max_socket = sock_max; 1021 + _min_pnode = pnode_min; 1022 + _max_pnode = pnode_max; 1023 + _gr_table_len = index; 1024 + pr_info( 1025 + "UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", 1026 + index, _min_socket, _max_socket, _min_pnode, _max_pnode); 1027 + } 1028 + 1029 + static void __init decode_uv_systab(void) 1030 + { 1031 + struct uv_systab *st; 1032 + int i; 1033 + 1034 + st = uv_systab; 1035 + if ((!st || st->revision < UV_SYSTAB_VERSION_UV4) && !is_uv4_hub()) 1036 + return; 1037 + if (st->revision != UV_SYSTAB_VERSION_UV4_LATEST) { 1038 + pr_crit( 1039 + "UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", 1040 + st->revision, UV_SYSTAB_VERSION_UV4_LATEST); 1041 + BUG(); 1042 + } 1043 + 1044 + for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 1045 + unsigned long ptr = st->entry[i].offset; 1046 + 1047 + if (!ptr) 1048 + continue; 1049 + 1050 + ptr = ptr + (unsigned long)st; 1051 + 1052 + switch (st->entry[i].type) { 1053 + case UV_SYSTAB_TYPE_GAM_PARAMS: 1054 + decode_gam_params(ptr); 1055 + break; 1056 + 1057 + case UV_SYSTAB_TYPE_GAM_RNG_TBL: 1058 + decode_gam_rng_tbl(ptr); 1059 + break; 1060 + } 1061 + } 1062 + } 1063 + 1064 + /* 1065 + * Setup physical blade translations from UVH_NODE_PRESENT_TABLE 1066 + * .. NB: UVH_NODE_PRESENT_TABLE is going away, 1067 + * .. being replaced by GAM Range Table 1068 + */ 1069 + static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info) 1070 + { 1071 + int i, uv_pb = 0; 1072 + 1073 + pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH); 1074 + for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 1075 + unsigned long np; 1076 + 1077 + np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 1078 + if (np) 1079 + pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np); 1080 + 1081 + uv_pb += hweight64(np); 1082 + } 1083 + if (uv_possible_blades != uv_pb) 1084 + uv_possible_blades = uv_pb; 1085 + } 1086 + 1087 + static void __init build_socket_tables(void) 1088 + { 1089 + struct uv_gam_range_entry *gre = uv_gre_table; 1090 + int num, nump; 1091 + int cpu, i, lnid; 1092 + int minsock = _min_socket; 1093 + int maxsock = _max_socket; 1094 + int minpnode = _min_pnode; 1095 + int maxpnode = _max_pnode; 1096 + size_t bytes; 1097 + 1098 + if (!gre) { 1099 + if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) { 1100 + pr_info("UV: No UVsystab socket table, ignoring\n"); 1101 + return; /* not required */ 1102 + } 1103 + pr_crit( 1104 + "UV: Error: UVsystab address translations not available!\n"); 1105 + BUG(); 1106 + } 1107 + 1108 + /* build socket id -> node id, pnode */ 1109 + num = maxsock - minsock + 1; 1110 + bytes = num * sizeof(_socket_to_node[0]); 1111 + _socket_to_node = kmalloc(bytes, GFP_KERNEL); 1112 + _socket_to_pnode = kmalloc(bytes, GFP_KERNEL); 1113 + 1114 + nump = maxpnode - minpnode + 1; 1115 + bytes = nump * sizeof(_pnode_to_socket[0]); 1116 + _pnode_to_socket = kmalloc(bytes, GFP_KERNEL); 1117 + BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket); 1118 + 1119 + for (i = 0; i < num; i++) 1120 + _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY; 1121 + 1122 + for (i = 0; i < nump; i++) 1123 + _pnode_to_socket[i] = SOCK_EMPTY; 1124 + 1125 + /* fill in pnode/node/addr conversion list values */ 1126 + pr_info("UV: GAM Building socket/pnode/pxm conversion tables\n"); 1127 + for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1128 + if (gre->type == UV_GAM_RANGE_TYPE_HOLE) 1129 + continue; 1130 + i = gre->sockid - minsock; 1131 + if (_socket_to_pnode[i] != SOCK_EMPTY) 1132 + continue; /* duplicate */ 1133 + _socket_to_pnode[i] = gre->pnode; 1134 + _socket_to_node[i] = gre->pxm; 1135 + 1136 + i = gre->pnode - minpnode; 1137 + _pnode_to_socket[i] = gre->sockid; 1138 + 1139 + pr_info( 1140 + "UV: sid:%02x type:%d nasid:%04x pn:%02x pxm:%2d pn2s:%2x\n", 1141 + gre->sockid, gre->type, gre->nasid, 1142 + _socket_to_pnode[gre->sockid - minsock], 1143 + _socket_to_node[gre->sockid - minsock], 1144 + _pnode_to_socket[gre->pnode - minpnode]); 1145 + } 1146 + 1147 + /* check socket -> node values */ 1148 + lnid = -1; 1149 + for_each_present_cpu(cpu) { 1150 + int nid = cpu_to_node(cpu); 1151 + int apicid, sockid; 1152 + 1153 + if (lnid == nid) 1154 + continue; 1155 + lnid = nid; 1156 + apicid = per_cpu(x86_cpu_to_apicid, cpu); 1157 + sockid = apicid >> uv_cpuid.socketid_shift; 1158 + i = sockid - minsock; 1159 + 1160 + if (nid != _socket_to_node[i]) { 1161 + pr_warn( 1162 + "UV: %02x: type:%d socket:%02x PXM:%02x != node:%2d\n", 1163 + i, sockid, gre->type, _socket_to_node[i], nid); 1164 + _socket_to_node[i] = nid; 1165 + } 1166 + } 1167 + 1168 + /* Setup physical blade to pnode translation from GAM Range Table */ 1169 + bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]); 1170 + _node_to_pnode = kmalloc(bytes, GFP_KERNEL); 1171 + BUG_ON(!_node_to_pnode); 1172 + 1173 + for (lnid = 0; lnid < num_possible_nodes(); lnid++) { 1174 + unsigned short sockid; 1175 + 1176 + for (sockid = minsock; sockid <= maxsock; sockid++) { 1177 + if (lnid == _socket_to_node[sockid - minsock]) { 1178 + _node_to_pnode[lnid] = 1179 + _socket_to_pnode[sockid - minsock]; 1180 + break; 1181 + } 1182 + } 1183 + if (sockid > maxsock) { 1184 + pr_err("UV: socket for node %d not found!\n", lnid); 1185 + BUG(); 1186 + } 1187 + } 1188 + 1189 + /* 1190 + * If socket id == pnode or socket id == node for all nodes, 1191 + * system runs faster by removing corresponding conversion table. 1192 + */ 1193 + pr_info("UV: Checking socket->node/pnode for identity maps\n"); 1194 + if (minsock == 0) { 1195 + for (i = 0; i < num; i++) 1196 + if (_socket_to_node[i] == SOCK_EMPTY || 1197 + i != _socket_to_node[i]) 1198 + break; 1199 + if (i >= num) { 1200 + kfree(_socket_to_node); 1201 + _socket_to_node = NULL; 1202 + pr_info("UV: 1:1 socket_to_node table removed\n"); 1203 + } 1204 + } 1205 + if (minsock == minpnode) { 1206 + for (i = 0; i < num; i++) 1207 + if (_socket_to_pnode[i] != SOCK_EMPTY && 1208 + _socket_to_pnode[i] != i + minpnode) 1209 + break; 1210 + if (i >= num) { 1211 + kfree(_socket_to_pnode); 1212 + _socket_to_pnode = NULL; 1213 + pr_info("UV: 1:1 socket_to_pnode table removed\n"); 1214 + } 1215 + } 1216 + } 1217 + 1038 1218 void __init uv_system_init(void) 1039 1219 { 1040 - union uvh_rh_gam_config_mmr_u m_n_config; 1041 - union uvh_node_id_u node_id; 1042 - unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size; 1043 - int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val; 1044 - int gnode_extra, min_pnode = 999999, max_pnode = -1; 1045 - unsigned long mmr_base, present, paddr; 1046 - unsigned short pnode_mask; 1047 - unsigned char n_lshift; 1048 - char *hub = (is_uv1_hub() ? "UV100/1000" : 1049 - (is_uv2_hub() ? "UV2000/3000" : 1050 - (is_uv3_hub() ? "UV300" : NULL))); 1220 + struct uv_hub_info_s hub_info = {0}; 1221 + int bytes, cpu, nodeid; 1222 + unsigned short min_pnode = 9999, max_pnode = 0; 1223 + char *hub = is_uv4_hub() ? "UV400" : 1224 + is_uv3_hub() ? "UV300" : 1225 + is_uv2_hub() ? "UV2000/3000" : 1226 + is_uv1_hub() ? "UV100/1000" : NULL; 1051 1227 1052 1228 if (!hub) { 1053 1229 pr_err("UV: Unknown/unsupported UV hub\n"); ··· 1397 893 1398 894 map_low_mmrs(); 1399 895 1400 - m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR ); 1401 - m_val = m_n_config.s.m_skt; 1402 - n_val = m_n_config.s.n_skt; 1403 - pnode_mask = (1 << n_val) - 1; 1404 - n_lshift = get_n_lshift(m_val); 1405 - mmr_base = 1406 - uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & 1407 - ~UV_MMR_ENABLE; 1408 - 1409 - node_id.v = uv_read_local_mmr(UVH_NODE_ID); 1410 - gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1; 1411 - gnode_upper = ((unsigned long)gnode_extra << m_val); 1412 - pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x n_lshift 0x%x\n", 1413 - n_val, m_val, pnode_mask, gnode_upper, gnode_extra, 1414 - n_lshift); 1415 - 1416 - pr_info("UV: global MMR base 0x%lx\n", mmr_base); 1417 - 1418 - for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) 1419 - uv_possible_blades += 1420 - hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8)); 896 + uv_bios_init(); /* get uv_systab for decoding */ 897 + decode_uv_systab(); 898 + build_socket_tables(); 899 + build_uv_gr_table(); 900 + uv_init_hub_info(&hub_info); 901 + uv_possible_blades = num_possible_nodes(); 902 + if (!_node_to_pnode) 903 + boot_init_possible_blades(&hub_info); 1421 904 1422 905 /* uv_num_possible_blades() is really the hub count */ 1423 - pr_info("UV: Found %d blades, %d hubs\n", 1424 - is_uv1_hub() ? uv_num_possible_blades() : 1425 - (uv_num_possible_blades() + 1) / 2, 1426 - uv_num_possible_blades()); 906 + pr_info("UV: Found %d hubs, %d nodes, %d cpus\n", 907 + uv_num_possible_blades(), 908 + num_possible_nodes(), 909 + num_possible_cpus()); 1427 910 1428 - bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); 1429 - uv_blade_info = kzalloc(bytes, GFP_KERNEL); 1430 - BUG_ON(!uv_blade_info); 1431 - 1432 - for (blade = 0; blade < uv_num_possible_blades(); blade++) 1433 - uv_blade_info[blade].memory_nid = -1; 1434 - 1435 - get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); 1436 - 1437 - bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); 1438 - uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); 1439 - BUG_ON(!uv_node_to_blade); 1440 - memset(uv_node_to_blade, 255, bytes); 1441 - 1442 - bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); 1443 - uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); 1444 - BUG_ON(!uv_cpu_to_blade); 1445 - memset(uv_cpu_to_blade, 255, bytes); 1446 - 1447 - blade = 0; 1448 - for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 1449 - present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 1450 - for (j = 0; j < 64; j++) { 1451 - if (!test_bit(j, &present)) 1452 - continue; 1453 - pnode = (i * 64 + j) & pnode_mask; 1454 - uv_blade_info[blade].pnode = pnode; 1455 - uv_blade_info[blade].nr_possible_cpus = 0; 1456 - uv_blade_info[blade].nr_online_cpus = 0; 1457 - spin_lock_init(&uv_blade_info[blade].nmi_lock); 1458 - min_pnode = min(pnode, min_pnode); 1459 - max_pnode = max(pnode, max_pnode); 1460 - blade++; 1461 - } 1462 - } 1463 - 1464 - uv_bios_init(); 1465 911 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, 1466 912 &sn_region_size, &system_serial_number); 913 + hub_info.coherency_domain_number = sn_coherency_id; 1467 914 uv_rtc_init(); 1468 915 1469 - for_each_present_cpu(cpu) { 916 + bytes = sizeof(void *) * uv_num_possible_blades(); 917 + __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL); 918 + BUG_ON(!__uv_hub_info_list); 919 + 920 + bytes = sizeof(struct uv_hub_info_s); 921 + for_each_node(nodeid) { 922 + struct uv_hub_info_s *new_hub; 923 + 924 + if (__uv_hub_info_list[nodeid]) { 925 + pr_err("UV: Node %d UV HUB already initialized!?\n", 926 + nodeid); 927 + BUG(); 928 + } 929 + 930 + /* Allocate new per hub info list */ 931 + new_hub = (nodeid == 0) ? 932 + &uv_hub_info_node0 : 933 + kzalloc_node(bytes, GFP_KERNEL, nodeid); 934 + BUG_ON(!new_hub); 935 + __uv_hub_info_list[nodeid] = new_hub; 936 + new_hub = uv_hub_info_list(nodeid); 937 + BUG_ON(!new_hub); 938 + *new_hub = hub_info; 939 + 940 + /* Use information from GAM table if available */ 941 + if (_node_to_pnode) 942 + new_hub->pnode = _node_to_pnode[nodeid]; 943 + else /* Fill in during cpu loop */ 944 + new_hub->pnode = 0xffff; 945 + new_hub->numa_blade_id = uv_node_to_blade_id(nodeid); 946 + new_hub->memory_nid = -1; 947 + new_hub->nr_possible_cpus = 0; 948 + new_hub->nr_online_cpus = 0; 949 + } 950 + 951 + /* Initialize per cpu info */ 952 + for_each_possible_cpu(cpu) { 1470 953 int apicid = per_cpu(x86_cpu_to_apicid, cpu); 954 + int numa_node_id; 955 + unsigned short pnode; 1471 956 1472 - nid = cpu_to_node(cpu); 1473 - /* 1474 - * apic_pnode_shift must be set before calling uv_apicid_to_pnode(); 1475 - */ 1476 - uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask; 1477 - uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift; 1478 - uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision; 1479 - 1480 - uv_cpu_hub_info(cpu)->m_shift = 64 - m_val; 1481 - uv_cpu_hub_info(cpu)->n_lshift = n_lshift; 1482 - 957 + nodeid = cpu_to_node(cpu); 958 + numa_node_id = numa_cpu_node(cpu); 1483 959 pnode = uv_apicid_to_pnode(apicid); 1484 - blade = boot_pnode_to_blade(pnode); 1485 - lcpu = uv_blade_info[blade].nr_possible_cpus; 1486 - uv_blade_info[blade].nr_possible_cpus++; 1487 960 1488 - /* Any node on the blade, else will contain -1. */ 1489 - uv_blade_info[blade].memory_nid = nid; 1490 - 1491 - uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; 1492 - uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size; 1493 - uv_cpu_hub_info(cpu)->m_val = m_val; 1494 - uv_cpu_hub_info(cpu)->n_val = n_val; 1495 - uv_cpu_hub_info(cpu)->numa_blade_id = blade; 1496 - uv_cpu_hub_info(cpu)->blade_processor_id = lcpu; 1497 - uv_cpu_hub_info(cpu)->pnode = pnode; 1498 - uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1; 1499 - uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper; 1500 - uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra; 1501 - uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; 1502 - uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id; 1503 - uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid); 1504 - uv_node_to_blade[nid] = blade; 1505 - uv_cpu_to_blade[cpu] = blade; 961 + uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid); 962 + uv_cpu_info_per(cpu)->blade_cpu_id = 963 + uv_cpu_hub_info(cpu)->nr_possible_cpus++; 964 + if (uv_cpu_hub_info(cpu)->memory_nid == -1) 965 + uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu); 966 + if (nodeid != numa_node_id && /* init memoryless node */ 967 + uv_hub_info_list(numa_node_id)->pnode == 0xffff) 968 + uv_hub_info_list(numa_node_id)->pnode = pnode; 969 + else if (uv_cpu_hub_info(cpu)->pnode == 0xffff) 970 + uv_cpu_hub_info(cpu)->pnode = pnode; 971 + uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid); 1506 972 } 1507 973 1508 - /* Add blade/pnode info for nodes without cpus */ 1509 - for_each_online_node(nid) { 1510 - if (uv_node_to_blade[nid] >= 0) 1511 - continue; 1512 - paddr = node_start_pfn(nid) << PAGE_SHIFT; 1513 - pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); 1514 - blade = boot_pnode_to_blade(pnode); 1515 - uv_node_to_blade[nid] = blade; 974 + for_each_node(nodeid) { 975 + unsigned short pnode = uv_hub_info_list(nodeid)->pnode; 976 + 977 + /* Add pnode info for pre-GAM list nodes without cpus */ 978 + if (pnode == 0xffff) { 979 + unsigned long paddr; 980 + 981 + paddr = node_start_pfn(nodeid) << PAGE_SHIFT; 982 + pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); 983 + uv_hub_info_list(nodeid)->pnode = pnode; 984 + } 985 + min_pnode = min(pnode, min_pnode); 986 + max_pnode = max(pnode, max_pnode); 987 + pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n", 988 + nodeid, 989 + uv_hub_info_list(nodeid)->pnode, 990 + uv_hub_info_list(nodeid)->nr_possible_cpus); 1516 991 } 1517 992 993 + pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode); 1518 994 map_gru_high(max_pnode); 1519 995 map_mmr_high(max_pnode); 1520 996 map_mmioh_high(min_pnode, max_pnode);
+23 -25
arch/x86/platform/uv/bios_uv.c
··· 21 21 22 22 #include <linux/efi.h> 23 23 #include <linux/export.h> 24 + #include <linux/slab.h> 24 25 #include <asm/efi.h> 25 26 #include <linux/io.h> 26 27 #include <asm/uv/bios.h> 27 28 #include <asm/uv/uv_hub.h> 28 29 29 - static struct uv_systab uv_systab; 30 + struct uv_systab *uv_systab; 30 31 31 32 s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5) 32 33 { 33 - struct uv_systab *tab = &uv_systab; 34 + struct uv_systab *tab = uv_systab; 34 35 s64 ret; 35 36 36 - if (!tab->function) 37 + if (!tab || !tab->function) 37 38 /* 38 39 * BIOS does not support UV systab 39 40 */ ··· 184 183 } 185 184 EXPORT_SYMBOL_GPL(uv_bios_set_legacy_vga_target); 186 185 187 - 188 186 #ifdef CONFIG_EFI 189 187 void uv_bios_init(void) 190 188 { 191 - struct uv_systab *tab; 192 - 193 - if ((efi.uv_systab == EFI_INVALID_TABLE_ADDR) || 194 - (efi.uv_systab == (unsigned long)NULL)) { 195 - printk(KERN_CRIT "No EFI UV System Table.\n"); 196 - uv_systab.function = (unsigned long)NULL; 189 + uv_systab = NULL; 190 + if ((efi.uv_systab == EFI_INVALID_TABLE_ADDR) || !efi.uv_systab) { 191 + pr_crit("UV: UVsystab: missing\n"); 197 192 return; 198 193 } 199 194 200 - tab = (struct uv_systab *)ioremap(efi.uv_systab, 201 - sizeof(struct uv_systab)); 202 - if (strncmp(tab->signature, "UVST", 4) != 0) 203 - printk(KERN_ERR "bad signature in UV system table!"); 195 + uv_systab = ioremap(efi.uv_systab, sizeof(struct uv_systab)); 196 + if (!uv_systab || strncmp(uv_systab->signature, UV_SYSTAB_SIG, 4)) { 197 + pr_err("UV: UVsystab: bad signature!\n"); 198 + iounmap(uv_systab); 199 + return; 200 + } 204 201 205 - /* 206 - * Copy table to permanent spot for later use. 207 - */ 208 - memcpy(&uv_systab, tab, sizeof(struct uv_systab)); 209 - iounmap(tab); 210 - 211 - printk(KERN_INFO "EFI UV System Table Revision %d\n", 212 - uv_systab.revision); 202 + if (uv_systab->revision >= UV_SYSTAB_VERSION_UV4) { 203 + iounmap(uv_systab); 204 + uv_systab = ioremap(efi.uv_systab, uv_systab->size); 205 + if (!uv_systab) { 206 + pr_err("UV: UVsystab: ioremap(%d) failed!\n", 207 + uv_systab->size); 208 + return; 209 + } 210 + } 211 + pr_info("UV: UVsystab: Revision:%x\n", uv_systab->revision); 213 212 } 214 - #else /* !CONFIG_EFI */ 215 - 216 - void uv_bios_init(void) { } 217 213 #endif
+27 -11
arch/x86/platform/uv/tlb_uv.c
··· 37 37 }; 38 38 39 39 static int timeout_us; 40 - static int nobau; 40 + static bool nobau = true; 41 41 static int nobau_perm; 42 42 static cycles_t congested_cycles; 43 43 ··· 106 106 "enable: number times use of the BAU was re-enabled" 107 107 }; 108 108 109 - static int __init 110 - setup_nobau(char *arg) 109 + static int __init setup_bau(char *arg) 111 110 { 112 - nobau = 1; 111 + int result; 112 + 113 + if (!arg) 114 + return -EINVAL; 115 + 116 + result = strtobool(arg, &nobau); 117 + if (result) 118 + return result; 119 + 120 + /* we need to flip the logic here, so that bau=y sets nobau to false */ 121 + nobau = !nobau; 122 + 123 + if (!nobau) 124 + pr_info("UV BAU Enabled\n"); 125 + else 126 + pr_info("UV BAU Disabled\n"); 127 + 113 128 return 0; 114 129 } 115 - early_param("nobau", setup_nobau); 130 + early_param("bau", setup_bau); 116 131 117 132 /* base pnode in this partition */ 118 133 static int uv_base_pnode __read_mostly; ··· 146 131 pr_info("BAU not initialized; cannot be turned on\n"); 147 132 return; 148 133 } 149 - nobau = 0; 134 + nobau = false; 150 135 for_each_present_cpu(cpu) { 151 136 bcp = &per_cpu(bau_control, cpu); 152 - bcp->nobau = 0; 137 + bcp->nobau = false; 153 138 } 154 139 pr_info("BAU turned on\n"); 155 140 return; ··· 161 146 int cpu; 162 147 struct bau_control *bcp; 163 148 164 - nobau = 1; 149 + nobau = true; 165 150 for_each_present_cpu(cpu) { 166 151 bcp = &per_cpu(bau_control, cpu); 167 - bcp->nobau = 1; 152 + bcp->nobau = true; 168 153 } 169 154 pr_info("BAU turned off\n"); 170 155 return; ··· 1901 1886 bcp = &per_cpu(bau_control, cpu); 1902 1887 bcp->baudisabled = 0; 1903 1888 if (nobau) 1904 - bcp->nobau = 1; 1889 + bcp->nobau = true; 1905 1890 bcp->statp = &per_cpu(ptcstats, cpu); 1906 1891 /* time interval to catch a hardware stay-busy bug */ 1907 1892 bcp->timeout_interval = usec_2_cycles(2*timeout_us); ··· 2040 2025 return 1; 2041 2026 } 2042 2027 bcp->uvhub_master = *hmasterp; 2043 - bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id; 2028 + bcp->uvhub_cpu = uv_cpu_blade_processor_id(cpu); 2029 + 2044 2030 if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) { 2045 2031 printk(KERN_EMERG "%d cpus per uvhub invalid\n", 2046 2032 bcp->uvhub_cpu);
+1 -1
arch/x86/platform/uv/uv_sysfs.c
··· 34 34 static ssize_t coherence_id_show(struct kobject *kobj, 35 35 struct kobj_attribute *attr, char *buf) 36 36 { 37 - return snprintf(buf, PAGE_SIZE, "%ld\n", partition_coherence_id()); 37 + return snprintf(buf, PAGE_SIZE, "%ld\n", uv_partition_coherence_id()); 38 38 } 39 39 40 40 static struct kobj_attribute partition_id_attr =
+3 -3
arch/x86/platform/uv/uv_time.c
··· 165 165 for_each_present_cpu(cpu) { 166 166 int nid = cpu_to_node(cpu); 167 167 int bid = uv_cpu_to_blade_id(cpu); 168 - int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 168 + int bcpu = uv_cpu_blade_processor_id(cpu); 169 169 struct uv_rtc_timer_head *head = blade_info[bid]; 170 170 171 171 if (!head) { ··· 226 226 int pnode = uv_cpu_to_pnode(cpu); 227 227 int bid = uv_cpu_to_blade_id(cpu); 228 228 struct uv_rtc_timer_head *head = blade_info[bid]; 229 - int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 229 + int bcpu = uv_cpu_blade_processor_id(cpu); 230 230 u64 *t = &head->cpu[bcpu].expires; 231 231 unsigned long flags; 232 232 int next_cpu; ··· 262 262 int pnode = uv_cpu_to_pnode(cpu); 263 263 int bid = uv_cpu_to_blade_id(cpu); 264 264 struct uv_rtc_timer_head *head = blade_info[bid]; 265 - int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 265 + int bcpu = uv_cpu_blade_processor_id(cpu); 266 266 u64 *t = &head->cpu[bcpu].expires; 267 267 unsigned long flags; 268 268 int rc = 0;
+22 -16
drivers/misc/sgi-gru/grukservices.c
··· 718 718 static int send_message_put_nacked(void *cb, struct gru_message_queue_desc *mqd, 719 719 void *mesg, int lines) 720 720 { 721 - unsigned long m, *val = mesg, gpa, save; 722 - int ret; 721 + unsigned long m; 722 + int ret, loops = 200; /* experimentally determined */ 723 723 724 724 m = mqd->mq_gpa + (gru_get_amo_value_head(cb) << 6); 725 725 if (lines == 2) { ··· 735 735 return MQE_OK; 736 736 737 737 /* 738 - * Send a cross-partition interrupt to the SSI that contains the target 739 - * message queue. Normally, the interrupt is automatically delivered by 740 - * hardware but some error conditions require explicit delivery. 741 - * Use the GRU to deliver the interrupt. Otherwise partition failures 738 + * Send a noop message in order to deliver a cross-partition interrupt 739 + * to the SSI that contains the target message queue. Normally, the 740 + * interrupt is automatically delivered by hardware following mesq 741 + * operations, but some error conditions require explicit delivery. 742 + * The noop message will trigger delivery. Otherwise partition failures 742 743 * could cause unrecovered errors. 743 744 */ 744 - gpa = uv_global_gru_mmr_address(mqd->interrupt_pnode, UVH_IPI_INT); 745 - save = *val; 746 - *val = uv_hub_ipi_value(mqd->interrupt_apicid, mqd->interrupt_vector, 747 - dest_Fixed); 748 - gru_vstore_phys(cb, gpa, gru_get_tri(mesg), IAA_REGISTER, IMA); 749 - ret = gru_wait(cb); 750 - *val = save; 751 - if (ret != CBS_IDLE) 752 - return MQE_UNEXPECTED_CB_ERR; 753 - return MQE_OK; 745 + do { 746 + ret = send_noop_message(cb, mqd, mesg); 747 + } while ((ret == MQIE_AGAIN || ret == MQE_CONGESTION) && (loops-- > 0)); 748 + 749 + if (ret == MQIE_AGAIN || ret == MQE_CONGESTION) { 750 + /* 751 + * Don't indicate to the app to resend the message, as it's 752 + * already been successfully sent. We simply send an OK 753 + * (rather than fail the send with MQE_UNEXPECTED_CB_ERR), 754 + * assuming that the other side is receiving enough 755 + * interrupts to get this message processed anyway. 756 + */ 757 + ret = MQE_OK; 758 + } 759 + return ret; 754 760 } 755 761 756 762 /*