Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'ras_for_3.8' into x86/urgent

Retract MCE-specific UAPI exports which are unused and shouldn't be
used.

Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

+84 -87
+84
arch/x86/include/asm/mce.h
··· 3 3 4 4 #include <uapi/asm/mce.h> 5 5 6 + /* 7 + * Machine Check support for x86 8 + */ 9 + 10 + /* MCG_CAP register defines */ 11 + #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ 12 + #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ 13 + #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ 14 + #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ 15 + #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ 16 + #define MCG_EXT_CNT_SHIFT 16 17 + #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) 18 + #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 19 + 20 + /* MCG_STATUS register defines */ 21 + #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 22 + #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 23 + #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 24 + 25 + /* MCi_STATUS register defines */ 26 + #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 27 + #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 28 + #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 29 + #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 30 + #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 31 + #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 32 + #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 33 + #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 34 + #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 35 + #define MCACOD 0xffff /* MCA Error Code */ 36 + 37 + /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */ 38 + #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */ 39 + #define MCACOD_SCRUBMSK 0xfff0 40 + #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */ 41 + #define MCACOD_DATA 0x0134 /* Data Load */ 42 + #define MCACOD_INSTR 0x0150 /* Instruction Fetch */ 43 + 44 + /* MCi_MISC register defines */ 45 + #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f) 46 + #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7) 47 + #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */ 48 + #define MCI_MISC_ADDR_LINEAR 1 /* linear address */ 49 + #define MCI_MISC_ADDR_PHYS 2 /* physical address */ 50 + #define MCI_MISC_ADDR_MEM 3 /* memory address */ 51 + #define MCI_MISC_ADDR_GENERIC 7 /* generic */ 52 + 53 + /* CTL2 register defines */ 54 + #define MCI_CTL2_CMCI_EN (1ULL << 30) 55 + #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL 56 + 57 + #define MCJ_CTX_MASK 3 58 + #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) 59 + #define MCJ_CTX_RANDOM 0 /* inject context: random */ 60 + #define MCJ_CTX_PROCESS 0x1 /* inject context: process */ 61 + #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */ 62 + #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */ 63 + #define MCJ_EXCEPTION 0x8 /* raise as exception */ 64 + #define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */ 65 + 66 + #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ 67 + 68 + /* Software defined banks */ 69 + #define MCE_EXTENDED_BANK 128 70 + #define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0) 71 + #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) 72 + 73 + #define MCE_LOG_LEN 32 74 + #define MCE_LOG_SIGNATURE "MACHINECHECK" 75 + 76 + /* 77 + * This structure contains all data related to the MCE log. Also 78 + * carries a signature to make it easier to find from external 79 + * debugging tools. Each entry is only valid when its finished flag 80 + * is set. 81 + */ 82 + struct mce_log { 83 + char signature[12]; /* "MACHINECHECK" */ 84 + unsigned len; /* = MCE_LOG_LEN */ 85 + unsigned next; 86 + unsigned flags; 87 + unsigned recordlen; /* length of struct mce */ 88 + struct mce entry[MCE_LOG_LEN]; 89 + }; 6 90 7 91 struct mca_config { 8 92 bool dont_log_ce;
-87
arch/x86/include/uapi/asm/mce.h
··· 4 4 #include <linux/types.h> 5 5 #include <asm/ioctls.h> 6 6 7 - /* 8 - * Machine Check support for x86 9 - */ 10 - 11 - /* MCG_CAP register defines */ 12 - #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ 13 - #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ 14 - #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ 15 - #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ 16 - #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ 17 - #define MCG_EXT_CNT_SHIFT 16 18 - #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) 19 - #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 20 - 21 - /* MCG_STATUS register defines */ 22 - #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 23 - #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 24 - #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 25 - 26 - /* MCi_STATUS register defines */ 27 - #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 28 - #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 29 - #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 30 - #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 31 - #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 32 - #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 33 - #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 34 - #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 35 - #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 36 - #define MCACOD 0xffff /* MCA Error Code */ 37 - 38 - /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */ 39 - #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */ 40 - #define MCACOD_SCRUBMSK 0xfff0 41 - #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */ 42 - #define MCACOD_DATA 0x0134 /* Data Load */ 43 - #define MCACOD_INSTR 0x0150 /* Instruction Fetch */ 44 - 45 - /* MCi_MISC register defines */ 46 - #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f) 47 - #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7) 48 - #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */ 49 - #define MCI_MISC_ADDR_LINEAR 1 /* linear address */ 50 - #define MCI_MISC_ADDR_PHYS 2 /* physical address */ 51 - #define MCI_MISC_ADDR_MEM 3 /* memory address */ 52 - #define MCI_MISC_ADDR_GENERIC 7 /* generic */ 53 - 54 - /* CTL2 register defines */ 55 - #define MCI_CTL2_CMCI_EN (1ULL << 30) 56 - #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL 57 - 58 - #define MCJ_CTX_MASK 3 59 - #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) 60 - #define MCJ_CTX_RANDOM 0 /* inject context: random */ 61 - #define MCJ_CTX_PROCESS 0x1 /* inject context: process */ 62 - #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */ 63 - #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */ 64 - #define MCJ_EXCEPTION 0x8 /* raise as exception */ 65 - #define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */ 66 - 67 7 /* Fields are zero when not available */ 68 8 struct mce { 69 9 __u64 status; ··· 27 87 __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */ 28 88 }; 29 89 30 - /* 31 - * This structure contains all data related to the MCE log. Also 32 - * carries a signature to make it easier to find from external 33 - * debugging tools. Each entry is only valid when its finished flag 34 - * is set. 35 - */ 36 - 37 - #define MCE_LOG_LEN 32 38 - 39 - struct mce_log { 40 - char signature[12]; /* "MACHINECHECK" */ 41 - unsigned len; /* = MCE_LOG_LEN */ 42 - unsigned next; 43 - unsigned flags; 44 - unsigned recordlen; /* length of struct mce */ 45 - struct mce entry[MCE_LOG_LEN]; 46 - }; 47 - 48 - #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ 49 - 50 - #define MCE_LOG_SIGNATURE "MACHINECHECK" 51 - 52 90 #define MCE_GET_RECORD_LEN _IOR('M', 1, int) 53 91 #define MCE_GET_LOG_LEN _IOR('M', 2, int) 54 92 #define MCE_GETCLEAR_FLAGS _IOR('M', 3, int) 55 - 56 - /* Software defined banks */ 57 - #define MCE_EXTENDED_BANK 128 58 - #define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0 59 - #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) 60 93 61 94 #endif /* _UAPI_ASM_X86_MCE_H */