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linux
clk: meson: add vclk driver
The VCLK and VCLK_DIV clocks have supplementary bits.
The VCLK gate has a "SOFT RESET" bit to toggle after the whole
VCLK sub-tree rate has been set, this is implemented in
the gate enable callback.
The VCLK_DIV clocks as enable and reset bits used to disable
and reset the divider, associated with CLK_SET_RATE_GATE it ensures
the rate is set while the divider is disabled and in reset mode.
The VCLK_DIV enable bit isn't implemented as a gate since it's part
of the divider logic and vendor does this exact sequence to ensure
the divider is correctly set.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-2-99ecdfdc87fc@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
authored by
Neil Armstrong
and committed by
Jerome Brunet
bb5aa085
16182ac3
+197
+4
drivers/clk/meson/Kconfig
+4
drivers/clk/meson/Kconfig
+1
drivers/clk/meson/Makefile
+1
drivers/clk/meson/Makefile
+141
drivers/clk/meson/vclk.c
+141
drivers/clk/meson/vclk.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
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*/
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#include <linux/module.h>
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#include "vclk.h"
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/* The VCLK gate has a supplementary reset bit to pulse after ungating */
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static inline struct meson_vclk_gate_data *
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clk_get_meson_vclk_gate_data(struct clk_regmap *clk)
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{
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return (struct meson_vclk_gate_data *)clk->data;
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}
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static int meson_vclk_gate_enable(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
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meson_parm_write(clk->map, &vclk->enable, 1);
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/* Do a reset pulse */
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meson_parm_write(clk->map, &vclk->reset, 1);
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meson_parm_write(clk->map, &vclk->reset, 0);
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return 0;
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}
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static void meson_vclk_gate_disable(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
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meson_parm_write(clk->map, &vclk->enable, 0);
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}
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static int meson_vclk_gate_is_enabled(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
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return meson_parm_read(clk->map, &vclk->enable);
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}
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const struct clk_ops meson_vclk_gate_ops = {
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.enable = meson_vclk_gate_enable,
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.disable = meson_vclk_gate_disable,
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.is_enabled = meson_vclk_gate_is_enabled,
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};
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EXPORT_SYMBOL_GPL(meson_vclk_gate_ops);
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/* The VCLK Divider has supplementary reset & enable bits */
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static inline struct meson_vclk_div_data *
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clk_get_meson_vclk_div_data(struct clk_regmap *clk)
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{
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return (struct meson_vclk_div_data *)clk->data;
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}
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static unsigned long meson_vclk_div_recalc_rate(struct clk_hw *hw,
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unsigned long prate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
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return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->div),
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vclk->table, vclk->flags, vclk->div.width);
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}
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static int meson_vclk_div_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
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return divider_determine_rate(hw, req, vclk->table, vclk->div.width,
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vclk->flags);
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}
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static int meson_vclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
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int ret;
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ret = divider_get_val(rate, parent_rate, vclk->table, vclk->div.width,
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vclk->flags);
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if (ret < 0)
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return ret;
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meson_parm_write(clk->map, &vclk->div, ret);
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return 0;
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};
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static int meson_vclk_div_enable(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
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/* Unreset the divider when ungating */
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meson_parm_write(clk->map, &vclk->reset, 0);
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meson_parm_write(clk->map, &vclk->enable, 1);
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return 0;
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}
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static void meson_vclk_div_disable(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
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/* Reset the divider when gating */
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meson_parm_write(clk->map, &vclk->enable, 0);
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meson_parm_write(clk->map, &vclk->reset, 1);
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}
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static int meson_vclk_div_is_enabled(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
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return meson_parm_read(clk->map, &vclk->enable);
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}
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const struct clk_ops meson_vclk_div_ops = {
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.recalc_rate = meson_vclk_div_recalc_rate,
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.determine_rate = meson_vclk_div_determine_rate,
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.set_rate = meson_vclk_div_set_rate,
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.enable = meson_vclk_div_enable,
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.disable = meson_vclk_div_disable,
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.is_enabled = meson_vclk_div_is_enabled,
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};
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EXPORT_SYMBOL_GPL(meson_vclk_div_ops);
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MODULE_DESCRIPTION("Amlogic vclk clock driver");
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MODULE_AUTHOR("Neil Armstrong <neil.armstrong@linaro.org>");
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MODULE_LICENSE("GPL v2");
+51
drivers/clk/meson/vclk.h
+51
drivers/clk/meson/vclk.h
···
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
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*/
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#ifndef __VCLK_H
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#define __VCLK_H
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#include "clk-regmap.h"
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#include "parm.h"
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/**
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* struct meson_vclk_gate_data - vclk_gate regmap backed specific data
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*
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* @enable: vclk enable field
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* @reset: vclk reset field
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* @flags: hardware-specific flags
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*
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* Flags:
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* Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored
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*/
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struct meson_vclk_gate_data {
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struct parm enable;
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struct parm reset;
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u8 flags;
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};
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extern const struct clk_ops meson_vclk_gate_ops;
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/**
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* struct meson_vclk_div_data - vclk_div regmap back specific data
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*
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* @div: divider field
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* @enable: vclk divider enable field
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* @reset: vclk divider reset field
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* @table: array of value/divider pairs, last entry should have div = 0
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*
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* Flags:
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* Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored
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*/
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struct meson_vclk_div_data {
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struct parm div;
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struct parm enable;
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struct parm reset;
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const struct clk_div_table *table;
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u8 flags;
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};
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extern const struct clk_ops meson_vclk_div_ops;
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#endif /* __VCLK_H */