···1414# Code maturity level options1515#1616CONFIG_EXPERIMENTAL=y1717-# CONFIG_CLEAN_COMPILE is not set1818-CONFIG_BROKEN=y1717+CONFIG_CLEAN_COMPILE=y1918CONFIG_BROKEN_ON_SMP=y20192120#···359360#360361# IEEE 1394 (FireWire) support361362#362362-# CONFIG_IEEE1394 is not set363363364364#365365# I2O device support···779781# CONFIG_DEVFS_FS is not set780782# CONFIG_DEVPTS_FS_XATTR is not set781783# CONFIG_TMPFS is not set782782-# CONFIG_HUGETLBFS is not set783784# CONFIG_HUGETLB_PAGE is not set784785CONFIG_RAMFS=y785786
+1-6
arch/arm/configs/collie_defconfig
···1313# Code maturity level options1414#1515CONFIG_EXPERIMENTAL=y1616-# CONFIG_CLEAN_COMPILE is not set1717-CONFIG_BROKEN=y1616+CONFIG_CLEAN_COMPILE=y1817CONFIG_BROKEN_ON_SMP=y1918CONFIG_LOCK_KERNEL=y2019CONFIG_INIT_ENV_ARG_LIMIT=32···307308# CONFIG_MTD_ROM is not set308309# CONFIG_MTD_ABSENT is not set309310CONFIG_MTD_OBSOLETE_CHIPS=y310310-# CONFIG_MTD_AMDSTD is not set311311CONFIG_MTD_SHARP=y312312-# CONFIG_MTD_JEDEC is not set313312314313#315314# Mapping drivers for chip access···393396#394397# IEEE 1394 (FireWire) support395398#396396-# CONFIG_IEEE1394 is not set397399398400#399401# I2O device support···737741CONFIG_PROC_FS=y738742CONFIG_SYSFS=y739743CONFIG_TMPFS=y740740-# CONFIG_HUGETLBFS is not set741744# CONFIG_HUGETLB_PAGE is not set742745CONFIG_RAMFS=y743746# CONFIG_RELAYFS_FS is not set
+1-4
arch/arm/configs/s3c2410_defconfig
···1313# Code maturity level options1414#1515CONFIG_EXPERIMENTAL=y1616-# CONFIG_CLEAN_COMPILE is not set1717-CONFIG_BROKEN=y1616+CONFIG_CLEAN_COMPILE=y1817CONFIG_BROKEN_ON_SMP=y1918CONFIG_INIT_ENV_ARG_LIMIT=322019···472473#473474# IEEE 1394 (FireWire) support474475#475475-# CONFIG_IEEE1394 is not set476476477477#478478# I2O device support···894896CONFIG_PROC_FS=y895897CONFIG_SYSFS=y896898# CONFIG_TMPFS is not set897897-# CONFIG_HUGETLBFS is not set898899# CONFIG_HUGETLB_PAGE is not set899900CONFIG_RAMFS=y900901# CONFIG_RELAYFS_FS is not set
···469469 if (fb->fb.var.bits_per_pixel <= 8)470470 val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;471471 else if (fb->fb.var.bits_per_pixel <= 16)472472- val = CM_CTRL_LCDMUXSEL_VGA_16BPP;472472+ val = CM_CTRL_LCDMUXSEL_VGA_16BPP473473+ | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1474474+ | CM_CTRL_STATIC1 | CM_CTRL_STATIC2;473475 else474476 val = 0; /* no idea for this, don't trust the docs */475477
+2-1
arch/arm/mach-s3c2410/cpu.h
···1717 * 14-Jan-2005 BJD Added s3c24xx_init_clocks() call1818 * 10-Mar-2005 LCVR Changed S3C2410_{VA,SZ} to S3C24XX_{VA,SZ} & IODESC_ENT1919 * 14-Mar-2005 BJD Updated for __iomem2020+ * 15-Jan-2006 LCVR Updated S3C2410_PA_##x to new S3C24XX_PA_##x macro2021*/21222223/* todo - fix when rmk changes iodescs to use `void __iomem *` */23242424-#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C2410_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }2525+#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }25262627#ifndef MHZ2728#define MHZ (1000*1000)
···3535#undef S3C2410_GPIOREG3636#undef S3C2410_WDOGREG37373838-#define S3C2410_GPIOREG(x) ((S3C2410_PA_GPIO + (x)))3939-#define S3C2410_WDOGREG(x) ((S3C2410_PA_WATCHDOG + (x)))3838+#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))3939+#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))40404141/* how many bytes we allow into the FIFO at a time in FIFO mode */4242#define FIFO_MAX (14)43434444-#define uart_base S3C2410_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT)4444+#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT)45454646static __inline__ void4747uart_wr(unsigned int reg, unsigned int val)